Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel, and belongs to the technical field of display. The array substrate comprises a substrate, a first common electrode layer, a first insulating layer, a semiconductor layer, a first metal layer, a pixel electrode, a second insulating layer and a second common electrode layer. The first common electrode layer is arranged on the substrate; the first insulating layer covers the first common electrode layer; the semiconductor layer is arranged on the first insulating layer; the first metal layer comprises a first electrode, and the first electrode is arranged on the semiconductor layer; one part of the pixel electrode is at least overlapped with the side surface of the first electrode, and another part of the pixel electrode is arranged on the side surface of the semiconductor layer and directly contacts the side surface of the semiconductor layer; the second insulating layer covers the first metal layer and the semiconductor layer; one part of the second common electrode layer is arranged on the second insulating layer, and the second common electrode layer, the pixel electrode and the first common electrode layer are overlapped. The application can improve the display effect, reduce the number of mask plates used and reduce the production cost.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] In LCD panels, with the development of AI technology, users are increasingly demanding low-frequency driving. However, due to the large leakage current in the off-state of amorphous silicon (a-Si) substrates, brightness decays significantly during low-frequency driving, resulting in a large brightness difference between positive and negative frames and causing screen flicker, which affects the display effect.

[0003] On the other hand, current solutions for improving display performance involve a relatively large number of process steps, leading to decreased production efficiency and increased production costs.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Utility Model Content

[0005] The purpose of this application is to provide an array substrate and a display panel that can improve the display effect, reduce the number of photomasks used, and reduce production costs.

[0006] To solve the above problems, the technical solution of this application is as follows: In a first aspect, this application proposes an array substrate, comprising: Substrate; A first common electrode layer is disposed on one side of the substrate; A first insulating layer is disposed on one side of the substrate and covers the first common electrode layer; A semiconductor layer is disposed on the side of the first insulating layer away from the substrate; A first metal layer includes a first electrode, which is disposed on the side of the semiconductor layer away from the substrate; A pixel electrode, wherein a portion of the pixel electrode is at least attached to the side of the first electrode, and another portion of the pixel electrode is disposed on the side of the semiconductor layer and in direct contact with the side of the semiconductor layer; A second insulating layer is disposed on the side of the first metal layer away from the substrate, and covers the first metal layer and the semiconductor layer; A second common electrode layer, a portion of which is disposed on the side of the second insulating layer away from the substrate, and the second common electrode layer, the pixel electrode, and the first common electrode layer overlap in the thickness direction of the array substrate.

[0007] In one embodiment of this application, the first metal layer further includes multiple data lines; In a plan view of the array substrate, multiple data lines are arranged at intervals along a first direction, and the pixel electrode is disposed between two adjacent data lines. In the thickness direction of the array substrate, the second common electrode layer overlaps with the data line, the first common electrode layer overlaps with the data line, and the orthographic projection of the pixel electrode on the substrate is spaced apart from the orthographic projection of the data line on the substrate.

[0008] In one embodiment of this application, the second common electrode layer includes: A plurality of second common electrodes, one of which overlaps with one of the pixel electrodes in the thickness direction of the array substrate, wherein the second common electrodes and the data lines are spaced apart in a plan view of the array substrate; and A connecting portion is connected to the second common electrode, and the connecting portion overlaps with the data line in the thickness direction of the array substrate.

[0009] In one embodiment of this application, the array substrate further includes a second metal layer disposed between the substrate and the first insulating layer, the second metal layer comprising: A gate electrode, wherein the gate electrode overlaps with the semiconductor layer in the thickness direction of the array substrate; Multiple scan lines are connected to the gate. In a plan view of the array substrate, the multiple scan lines are arranged at intervals along a second direction. The pixel electrode is disposed between two adjacent scan lines. At least a portion of the first common electrode layer is insulated from the gate.

[0010] In one embodiment of this application, the first common electrode layer includes a plurality of first common electrodes, the first common electrodes being insulated from the gate, and the first common electrodes, the pixel electrode, and the second common electrode overlapping in the thickness direction of the array substrate; In a plan view of the array substrate, the first common electrode is located between two adjacent scan lines, and the first common electrode is spaced apart from the scan lines.

[0011] In one embodiment of this application, the second metal layer is disposed between the first common electrode layer and the first insulating layer; The first common electrode layer further includes a first sub-part, which is spaced apart from the first common electrode. The gate is disposed between the first sub-part and the first insulating layer. The orthographic projection of the first sub-part on the substrate is spaced apart from the orthographic projection of the pixel electrode on the substrate.

[0012] In one embodiment of this application, the second common electrode is electrically connected to the first common electrode.

[0013] In one embodiment of this application, the second metal layer further includes a second sub-part, which is spaced apart from the gate and is located on the side of the first common electrode away from the substrate; A first via is provided in the first insulating layer and the second insulating layer. The first via exposes the second sub-part. Another part of the second common electrode passes through the first via and is connected to the second sub-part.

[0014] In one embodiment of this application, the first metal layer further includes a second electrode, which is disposed at a distance from the first electrode; The semiconductor layer includes a channel and a first doped portion and a second doped portion connected to both sides of the channel; The first electrode is disposed on the side of the first doped portion away from the substrate, and the second electrode is disposed on the side of the second doped portion away from the substrate; The orthographic projection of the side of the first electrode away from the second electrode onto the substrate is within the range of the orthographic projection of the first doped portion onto the substrate, and the orthographic projection of the side of the second electrode away from the first electrode onto the substrate is within the range of the orthographic projection of the second doped portion onto the substrate; The pixel electrode is in direct contact with the side of the first doped portion.

[0015] Secondly, this application proposes a display panel including an array substrate, the array substrate comprising: Substrate; A first common electrode layer is disposed on one side of the substrate; A first insulating layer is disposed on one side of the substrate and covers the first common electrode layer; A semiconductor layer is disposed on the side of the first insulating layer away from the substrate; A first metal layer includes a first electrode, which is disposed on the side of the semiconductor layer away from the substrate; A pixel electrode, wherein a portion of the pixel electrode is at least attached to the side of the first electrode, and another portion of the pixel electrode is disposed on the side of the semiconductor layer and in direct contact with the side of the semiconductor layer; A second insulating layer is disposed on the side of the first metal layer away from the substrate, and covers the first metal layer and the semiconductor layer; A second common electrode layer, a portion of which is disposed on the side of the second insulating layer away from the substrate, and the second common electrode layer, the pixel electrode, and the first common electrode layer overlap in the thickness direction of the array substrate.

[0016] In this application, on the one hand, while a capacitor structure is formed between the pixel electrode and the first common electrode layer, a capacitor structure is also formed between the pixel electrode and the second common electrode layer. This can significantly increase the storage capacitance of each sub-pixel. During low-frequency driving, it can slow down the rate of decrease in pixel electrode voltage, improve the problem of significant brightness decay caused by large off-state leakage current in amorphous silicon substrates, reduce the brightness difference between positive and negative frames, improve screen flicker, and enhance display performance. On the other hand, in conventional processes, after forming a semiconductor material layer on the first insulating layer, a mask is needed to pattern the semiconductor material layer before the semiconductor layer can be formed. After forming a first metal material layer on the semiconductor layer, another mask is needed to pattern the first metal material layer before the first metal layer can be formed. Therefore, conventional processes require at least two masks to fabricate the semiconductor layer and the first metal layer. In this application, the semiconductor layer and the first metal layer can be patterned using a halftone mask. Specifically, after forming a semiconductor material layer on the first insulating layer, the semiconductor material layer is not patterned immediately. A first metal material layer is then formed on the semiconductor material layer, and a halftone mask is used to pattern the first metal material layer and the semiconductor material layer to form the semiconductor layer and the first electrode. Because the semiconductor layer and the first electrode are patterned using a single halftone mask, the side of the first electrode closest to the semiconductor layer is in direct contact with the semiconductor layer, and this side cannot contact the pixel electrode. The pixel electrode can only achieve electrical connection by overlapping with the side of the first electrode or the side of the first electrode furthest from the semiconductor layer. Compared to the conventional process of patterning the semiconductor layer and the first metal layer using two separate masks, this application reduces the number of masks used by at least one, thus lowering production costs. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a schematic diagram of one embodiment of the array substrate of this application; Figure 2 This is a plan view of an embodiment of the array substrate of this application; Figure 3 This is a plan view of another embodiment of the array substrate of this application; Figure 4 This is a plan view of the second common electrode layer of this application; Figure 5 This is a schematic diagram of another embodiment of the array substrate of this application; Figure 6 This is a schematic diagram of yet another embodiment of the array substrate of this application.

[0020] Explanation of reference numerals in the attached figures: 100, Array substrate; D1, First direction; D2, Second direction; Z, Thickness direction; 1. Substrate; 2. First common electrode layer; 21. First common electrode; 22. First sub-section; 3. First insulating layer; 4. Semiconductor layer; 41. Channel; 42. First doped portion; 43. Second doped portion; 5. First metal layer; 51. First electrode; 52. Second electrode; 53. Data line; 6. Pixel electrode; 7. Second insulating layer; 8. Second common electrode layer; 81. Second common electrode; 82. Connecting part; 9. Second metal layer; 91. Gate; 92. Scan line; 93. Second sub-section. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0022] This application discloses a display panel that can be applied to a display device, such as a tablet computer, e-reader, electronic display screen, laptop computer, mobile phone, augmented reality (AR) / virtual reality (VR) device, media player, wearable device, digital camera, car navigation system, etc.

[0023] Optionally, the display panel includes an array substrate and an opposing substrate disposed opposite each other, and a liquid crystal layer located between the array substrate and the opposing substrate.

[0024] Please see Figure 1 This application also proposes an array substrate 100, which includes a substrate 1, a first common electrode layer 2, a first insulating layer 3, a semiconductor layer 4, a first metal layer 5, a pixel electrode 6, a second insulating layer 7, and a second common electrode layer 8.

[0025] The first common electrode layer 2 is disposed on one side of the substrate 1.

[0026] The first insulating layer 3 is disposed on one side of the substrate 1 and covers the first common electrode layer 2.

[0027] The semiconductor layer 4 is disposed on the side of the first insulating layer 3 away from the substrate 1.

[0028] The first metal layer 5 includes a first electrode 51. The first electrode 51 is disposed on the side of the semiconductor layer 4 away from the substrate 1.

[0029] A portion of the pixel electrode 6 is at least attached to the side of the first electrode 51. Another portion of the pixel electrode 6 is disposed on the side of the semiconductor layer 4 and is in direct contact with the side of the semiconductor layer 4.

[0030] The second insulating layer 7 is disposed on the side of the first metal layer 5 away from the substrate 1, and covers the first metal layer 5 and the semiconductor layer 4.

[0031] A portion of the second common electrode layer 8 is disposed on the side of the second insulating layer 7 away from the substrate 1. The second common electrode layer 8, the pixel electrode 6, and the first common electrode layer 2 overlap in the thickness direction Z of the array substrate 100.

[0032] In this application, on the one hand, while a capacitor structure is formed between the pixel electrode 6 and the first common electrode layer 2, a capacitor structure is also formed between the pixel electrode 6 and the second common electrode layer 8. This can significantly increase the storage capacitance of each sub-pixel. During low-frequency driving, it can slow down the rate of voltage drop of the pixel electrode 6, improve the problem of significant brightness decay caused by large off-state leakage current of the amorphous silicon substrate, reduce the brightness difference between positive and negative frames, improve the phenomenon of screen flicker, and improve the display effect.

[0033] On the other hand, in conventional processes, after forming a semiconductor material layer on the first insulating layer, a photomask is needed to pattern the semiconductor material layer before the semiconductor layer can be formed. After forming a first metal material layer on the semiconductor layer, another photomask is needed to pattern the first metal material layer before the first metal layer can be formed. Therefore, conventional processes require at least two photomasks to fabricate the semiconductor layer and the first metal layer.

[0034] In this application, the semiconductor layer 4 and the first metal layer 5 can be patterned using a single photomask. Specifically, after forming a semiconductor material layer on the first insulating layer, the semiconductor material layer is not patterned immediately. Instead, a first metal material layer is formed on the semiconductor material layer. Then, a halftone photomask is used to pattern the first metal material layer and the semiconductor material layer, forming the semiconductor layer and the first electrode. Because the semiconductor layer and the first electrode are patterned using a single photomask, the side of the first electrode closest to the semiconductor layer is in direct contact with the semiconductor layer, and this side cannot contact the pixel electrode. The pixel electrode can only achieve electrical connection by overlapping with the side of the first electrode. Compared to the conventional process of patterning the semiconductor layer 4 and the first metal layer 5 using two separate photomasks, this application reduces the number of photomasks used by at least one, thus lowering production costs.

[0035] Optionally, the first metal layer 5 further includes a second electrode 52. The second electrode 52 is disposed at a distance from the first electrode 51.

[0036] The semiconductor layer 4 includes a channel 41 and a first doped portion 42 and a second doped portion 43 connected to both sides of the channel 41.

[0037] The first electrode 51 is disposed on the side of the first doped portion 42 away from the substrate 1. The second electrode 52 is disposed on the side of the second doped portion 43 away from the substrate 1.

[0038] The orthographic projection of the side of the first electrode 51 away from the second electrode 52 onto the substrate 1 falls within the range of the orthographic projection of the first doped portion 42 onto the substrate 1. The orthographic projection of the side of the second electrode 52 away from the first electrode 51 onto the substrate 1 falls within the range of the orthographic projection of the second doped portion 43 onto the substrate 1.

[0039] The pixel electrode 6 is in direct contact with the side of the first doped portion 42.

[0040] In this embodiment, the first metal layer 5 and the semiconductor layer 4 can be patterned using a photomask. This application can reduce the number of photomasks used, thereby reducing production costs. Specific steps for reducing the number of photomasks are described in the following method for fabricating the array substrate 100.

[0041] This application discloses a method for fabricating an array substrate 100, comprising the following steps: Step S1: A first common electrode layer 2 is formed on the substrate 1, and a first insulating layer 3 is formed on the first common electrode layer 2.

[0042] Step S2: A semiconductor material layer is formed on the first insulating layer 3.

[0043] Step S3: Form a first metal material layer on the semiconductor material layer.

[0044] Step S4: Form a first photoresist layer on the first metal material layer. A first halftone mask is provided, comprising a first transparent area, a first partially transparent area, and a first opaque area. After exposing and developing the first photoresist layer through the first halftone mask, the portion of the first photoresist layer covered by the first transparent area is removed, corresponding to the portion of the first insulating layer 3 exposed outside the semiconductor layer 4. The portion of the first photoresist layer covered by the first partially transparent area forms a first photoresist, corresponding to the portion of the semiconductor layer 4 located between the first electrode 51 and the second electrode 52 (i.e., the channel 41). The portion of the first photoresist layer covered by the first opaque area forms two spaced-apart second photoresists, one corresponding to the first electrode 51 and the other to the second electrode 52. The thickness of the first photoresist is less than the thickness of the second photoresist, and the first photoresist connects the two second photoresists.

[0045] Step S5: Use an etching process to remove the areas of the semiconductor material layer and the first metal material layer that are not covered by the first photoresist and the second photoresist, to form the semiconductor layer 4 and the first metal film layer disposed on the semiconductor layer 4.

[0046] Step S6: Remove the first photoresist using an ashing process. Simultaneously, a portion of the thickness of the second photoresist is removed. At this point, the portion of the first metal film layer corresponding to the first photoresist is exposed between the two second photoresists.

[0047] Step S7: Then, use an etching process to remove the portion of the first metal film layer not covered by the second photoresist, forming a first electrode 51 and a second electrode 52 spaced apart. A second photoresist is provided on the first electrode 51, and a second photoresist is provided on the second electrode 52.

[0048] Step S8: Use an ashing process to remove the second photoresist, thereby exposing the first electrode 51 and the second electrode 52.

[0049] Please refer to steps S1-S8. After step S2, the semiconductor material layer is not patterned immediately. Instead, a first metal material layer is formed on the semiconductor material layer in step S3. After forming the first metal material layer, in steps S4-S8, a halftone mask is used to pattern the first metal material layer and the semiconductor material layer, achieving the effect of patterning the semiconductor layer and the first metal layer using only one halftone mask. In this embodiment, the semiconductor layer 4 and the first electrode 51 can be fabricated using only one first halftone mask. Compared with the traditional solution that uses at least two masks to etch the semiconductor layer 4 and the first electrode 51 respectively, this application reduces the number of masks by at least one, thus reducing production costs.

[0050] Optionally, the side of the first electrode 51 away from the second electrode 52 is flush with the side of the first doped portion 42 away from the second doped portion 43.

[0051] In this application, please refer to steps S5 and S7. In both etching steps, since the second photoresist is located on the first electrode 51, the side surface of the first electrode 51 and the side surface of the first doped portion 42 located below the first electrode 51 can be made into a flush shape after the second etching.

[0052] Please see Figure 2 Optionally, the first metal layer 5 also includes multiple data lines 53.

[0053] In a plan view of the array substrate 100, multiple data lines 53 are arranged at intervals along a first direction D1. Pixel electrodes 6 are disposed between two adjacent data lines 53.

[0054] Please see Figure 3 In the thickness direction Z of the array substrate 100, the second common electrode layer 8 overlaps with the data line 53. The first common electrode layer 2 also overlaps with the data line 53. The orthogonal projection of the pixel electrode 6 on the substrate 1 and the orthogonal projection of the data line 53 on the substrate 1 are spaced apart.

[0055] In this embodiment, while a capacitor structure is formed between the pixel electrode 6 and the first common electrode layer 2, a capacitor structure is also formed between the pixel electrode 6 and the second common electrode layer 8. This can significantly increase the storage capacitance of each sub-pixel. During low-frequency driving, it can slow down the rate of voltage drop of the pixel electrode 6, improve the problem of significant brightness decay caused by large off-state leakage current in the amorphous silicon substrate, reduce the brightness difference between positive and negative frames, improve screen flicker, and enhance the display effect. In addition, the second common electrode layer 8 overlaps with the data line 53, which can shield the electric field of the data line 53 and improve the display effect.

[0056] Please see Figure 4 Optionally, the second common electrode layer 8 includes a plurality of second common electrodes 81 and a connecting portion 82.

[0057] A second common electrode 81 and a pixel electrode 6 overlap in the thickness direction Z of the array substrate 100. The second common electrode 81 and the data line 53 are spaced apart in a plan view of the array substrate 100.

[0058] The connection portion 82 is connected to the second common electrode 81. The connection portion 82 and the data line 53 overlap in the thickness direction Z of the array substrate 100.

[0059] In this embodiment, a capacitor structure is formed between the pixel electrode 6 and the second common electrode 81, which can increase the storage capacitance of each sub-pixel. During low-frequency driving, it can slow down the rate of voltage drop of the pixel electrode 6, improve the problem of significant brightness decay caused by large off-state leakage current of the amorphous silicon substrate, reduce the brightness difference between positive and negative frames, improve screen flicker, and enhance the display effect. The connecting part 82 connects multiple second common electrodes 81 and shields the electric field of the data line 53, further improving the display effect.

[0060] Optionally, the array substrate 100 further includes a second metal layer 9. The second metal layer 9 is disposed between the substrate 1 and the first insulating layer 3.

[0061] The second metal layer 9 includes a gate 91 and multiple scan lines 92. The gate 91 overlaps with the semiconductor layer 4 in the thickness direction Z of the array substrate 100. The scan lines 92 are connected to the gate 91.

[0062] In a plan view of the array substrate 100, multiple scan lines 92 are arranged at intervals along a second direction D2. Pixel electrodes 6 are disposed between adjacent scan lines 92. At least a portion of the first common electrode layer 2 is insulated from the gate 91.

[0063] In this embodiment, the gate 91 is used to control the on / off state of the channel 41 of the semiconductor layer 4. In conventional schemes, the second metal layer 9 and the first common electrode layer 2 are respectively fabricated using two separate photomasks. However, this application also proposes a scheme to form the second metal layer 9 and the first common electrode layer 2 using the same photomask, so as to reduce the production cost of the array substrate 100. The specific scheme is described in the next embodiment.

[0064] Optionally, the first common electrode layer 2 includes a plurality of first common electrodes 21. The first common electrodes 21 are insulated from the gate 91. The first common electrodes 21, the pixel electrode 6, and the second common electrode 81 overlap in the thickness direction Z of the array substrate 100.

[0065] In a plan view of the array substrate 100, the first common electrode 21 is located between two adjacent scan lines 92. The first common electrode 21 is spaced apart from the scan lines 92.

[0066] In this embodiment, a capacitor structure is formed between the pixel electrode 6 and the first common electrode 21, which can increase the storage capacitance of each sub-pixel. During low-frequency driving, the voltage drop rate of the pixel electrode 6 can be slowed down, which can improve the problem of significant brightness decay caused by large off-state leakage current of the amorphous silicon substrate, reduce the brightness difference between positive and negative frames, improve the phenomenon of screen flicker, and improve the display effect.

[0067] Please see Figure 5 Optionally, the second metal layer 9 is disposed between the first common electrode layer 2 and the first insulating layer 3.

[0068] The first common electrode layer 2 also includes a first sub-section 22. The first sub-section 22 is disposed at a distance from the first common electrode 21. The gate 91 is disposed between the first sub-section 22 and the first insulating layer 3. The orthographic projection of the first sub-section 22 on the substrate 1 is disposed at a distance from the orthographic projection of the pixel electrode 6 on the substrate 1.

[0069] In this embodiment, the second metal layer 9 and the first common electrode layer 2 can be formed using the same mask to reduce the production cost of the array substrate 100.

[0070] Step S1 of the method for fabricating the array substrate 100 proposed in this application includes the following steps: Step S11: Form a first transparent electrode layer on substrate 1.

[0071] Step S12: Form a second metal material layer on substrate 1.

[0072] Step S13: Form a second photoresist layer on the second metal layer 9. Provide a second halftone mask. The second halftone mask includes a second transparent area, a second partially transparent area, and a second opaque area. After exposing and developing the second photoresist layer through the second halftone mask, the portion of the second photoresist layer covered by the second transparent area is removed, and the removed portion corresponds to the portion of the substrate 1 exposed outside the first common electrode layer 2; the portion of the second photoresist layer covered by the second partially transparent area forms a third photoresist, which is disposed corresponding to the first common electrode 21; the portion of the second photoresist layer covered by the first opaque area forms a fourth photoresist, which is disposed corresponding to the gate 91. The thickness of the third photoresist is less than the thickness of the fourth photoresist, and the third and fourth photoresists are spaced apart.

[0073] Step S14: Using an etching process, remove the areas of the first transparent electrode layer and the second metal material layer not covered by the third and fourth photoresists to form a first common electrode layer 2 and a second metal film layer disposed on the first common electrode layer 2. The first common electrode layer 2 includes a first sub-part 22 and a first common electrode 21 spaced apart. A first portion of the second metal film layer is covered on the first common electrode layer 2, and a second portion of the second metal film layer is covered on the first sub-part 22. The first portion of the second metal film layer and the second portion of the second metal film layer are spaced apart. The third photoresist covers the first portion of the second metal film layer, and the fourth photoresist covers the second portion of the second metal film layer.

[0074] Step S15: Remove the third photoresist using an ashing process. Simultaneously, a portion of the thickness of the fourth photoresist is removed. At this point, the portion of the second metal film layer corresponding to the third photoresist is exposed.

[0075] Step S16: An etching process is then used to remove the portion of the second metal film layer not covered by the fourth photoresist, exposing the upper surface of the first common electrode 21. The unetched portion of the second metal film layer forms the gate 91. The gate 91 is provided with the fourth photoresist.

[0076] Step S17: Use an ashing process to remove the fourth photoresist, thereby exposing the gate 91.

[0077] Please refer to steps S11-S17. In this embodiment, the fabrication of the first common electrode layer 2 and the gate 91 can be completed using only one second halftone mask. Compared with the traditional solution that uses at least two masks to etch the first common electrode layer 2 and the gate 91 respectively, this application reduces the number of at least one mask and lowers the production cost.

[0078] Optionally, the second common electrode 81 is electrically connected to the first common electrode 21.

[0079] In this embodiment, the second common electrode 81 is electrically connected to the first common electrode 21, which can improve the uniformity of the displayed image and enhance the display effect.

[0080] Please see Figure 6 Optionally, the second metal layer 9 further includes a second sub-section 93. The second sub-section 93 is disposed at a distance from the gate 91. The second sub-section 93 is located on the side of the first common electrode 21 away from the substrate 1.

[0081] A first through-hole is provided in the first insulating layer 3 and the second insulating layer 7. The first through-hole exposes the second sub-part 93. Another part of the second common electrode 81 passes through the first through-hole and is connected to the second sub-part 93.

[0082] In this embodiment, if the second common electrode 81 directly connects to the first common electrode 21 through the first via, the depth of the first via is too deep. Due to internal stress, the portion of the second common electrode 81 passing through the first via is prone to breakage. Therefore, this embodiment reduces the depth of the first via by providing a second sub-part 93. Specifically, the second sub-part 93 is located on the upper surface of the first common electrode 21 and is in direct contact with and electrically connected to the first common electrode 21. The first via is formed in the first insulating layer 3 and the second insulating layer 7, exposing the upper surface of the second sub-part 93. A portion of the second common electrode 81 passes through the first via and overlaps with the second sub-part 93, and is electrically connected.

[0083] On the other hand, forming the first sub-part 22 does not require the use of an additional mask template; only corresponding adjustments need to be made in the fabrication method of the array substrate 100 in this application.

[0084] In step S13: Two fourth photoresists are formed. One fourth photoresist is disposed corresponding to the gate 91, and the other fourth photoresist is disposed corresponding to the second sub-section 93.

[0085] In step S16: The unetched portion of the second metal film layer forms a gate 91 and a sub-section 93 spaced apart.

[0086] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0087] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0088] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0089] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, include: Substrate; A first common electrode layer is disposed on one side of the substrate; A first insulating layer is disposed on one side of the substrate and covers the first common electrode layer; A semiconductor layer is disposed on the side of the first insulating layer away from the substrate; A first metal layer includes a first electrode, which is disposed on the side of the semiconductor layer away from the substrate; A pixel electrode, wherein a portion of the pixel electrode is at least attached to the side of the first electrode, and another portion of the pixel electrode is disposed on the side of the semiconductor layer and in direct contact with the side of the semiconductor layer; A second insulating layer is disposed on the side of the first metal layer away from the substrate, and covers the first metal layer and the semiconductor layer; A second common electrode layer, a portion of which is disposed on the side of the second insulating layer away from the substrate, and the second common electrode layer, the pixel electrode, and the first common electrode layer overlap in the thickness direction of the array substrate.

2. The array substrate as described in claim 1, characterized in that, The first metal layer also includes multiple data lines; In a plan view of the array substrate, multiple data lines are arranged at intervals along a first direction, and the pixel electrode is disposed between two adjacent data lines. In the thickness direction of the array substrate, the second common electrode layer overlaps with the data line, the first common electrode layer overlaps with the data line, and the orthographic projection of the pixel electrode on the substrate is spaced apart from the orthographic projection of the data line on the substrate.

3. The array substrate as described in claim 2, characterized in that, The second common electrode layer includes: A plurality of second common electrodes, one of which overlaps with one of the pixel electrodes in the thickness direction of the array substrate, wherein the second common electrodes and the data lines are spaced apart in a plan view of the array substrate; and A connecting portion is connected to the second common electrode, and the connecting portion overlaps with the data line in the thickness direction of the array substrate.

4. The array substrate as described in claim 3, characterized in that, The array substrate further includes a second metal layer disposed between the substrate and the first insulating layer, the second metal layer comprising: A gate electrode, wherein the gate electrode overlaps with the semiconductor layer in the thickness direction of the array substrate; Multiple scan lines are connected to the gate. In a plan view of the array substrate, the multiple scan lines are arranged at intervals along a second direction. The pixel electrode is disposed between two adjacent scan lines. At least a portion of the first common electrode layer is insulated from the gate.

5. The array substrate as described in claim 4, characterized in that, The first common electrode layer includes a plurality of first common electrodes, the first common electrodes being insulated from the gate, and the first common electrodes, the pixel electrodes, and the second common electrodes overlapping in the thickness direction of the array substrate; In a plan view of the array substrate, the first common electrode is located between two adjacent scan lines, and the first common electrode is spaced apart from the scan lines.

6. The array substrate as described in claim 5, characterized in that, The second metal layer is disposed between the first common electrode layer and the first insulating layer; The first common electrode layer further includes a first sub-part, which is spaced apart from the first common electrode. The gate is disposed between the first sub-part and the first insulating layer. The orthographic projection of the first sub-part on the substrate is spaced apart from the orthographic projection of the pixel electrode on the substrate.

7. The array substrate as described in claim 5, characterized in that, The second common electrode is electrically connected to the first common electrode.

8. The array substrate as described in claim 6, characterized in that, The second metal layer further includes a second sub-section, which is spaced apart from the gate and is located on the side of the first common electrode away from the substrate. A first via is provided in the first insulating layer and the second insulating layer. The first via exposes the second sub-part. Another part of the second common electrode passes through the first via and is connected to the second sub-part.

9. The array substrate as described in any one of claims 1-8, characterized in that, The first metal layer further includes a second electrode, which is disposed at a distance from the first electrode; The semiconductor layer includes a channel and a first doped portion and a second doped portion connected to both sides of the channel; The first electrode is disposed on the side of the first doped portion away from the substrate, and the second electrode is disposed on the side of the second doped portion away from the substrate; The orthographic projection of the side of the first electrode away from the second electrode onto the substrate is within the range of the orthographic projection of the first doped portion onto the substrate, and the orthographic projection of the side of the second electrode away from the first electrode onto the substrate is within the range of the orthographic projection of the second doped portion onto the substrate; The pixel electrode is in direct contact with the side of the first doped portion.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

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