An automatically switched multi-FPGA chip debugging system

Abstract

This utility model relates to the field of wireless communication technology, and in particular to an automatic switching multi-FPGA chip debugging system, including a JTAG interface, a network port, a microcontroller logic control circuit, a multiplexer chip, at least two FPGAs, and a power supply circuit. At least two FPGAs are connected in series to form a JTAG daisy chain. The network port receives network debugging signals and transmits them to the microcontroller logic control circuit. The microcontroller logic control circuit outputs switch control signals. The multiplexer chip selects different signals to the JTAG daisy chain based on the switch control signals. The power supply circuit provides power to the JTAG interface, network port, microcontroller logic control circuit, multiplexer chip, and FPGAs. It supports both network debugging and local simulation debugging. When a network debugging command is received, the system switches to network debugging mode via the microcontroller logic control circuit and the multiplexer chip. If no network debugging command is received, it switches to local simulation debugging, greatly facilitating on-site debugging and improving work efficiency.

Description

Technical Field

[0001] This utility model relates to the field of wireless communication technology, and in particular to an automatic switching multi-FPGA chip debugging system. Background Technology

[0002] FPGA debugging, downloading, and programming all require JTAG interface. Each FPGA manufacturer provides its own JTAG emulator. Circuits debugged via JTAG emulator are simple, but because the emulator connects to a PC via USB cable, its application scenarios are limited, such as on radar antennas or in a closed system. Current technology is inflexible, requiring either choosing between two debugging methods or manual switching via DIP switches. Network debugging is convenient and supports remote access, but it relies on the microcontroller being functioning correctly; if the microcontroller malfunctions, debugging is impossible. Manual switching requires removing the product from the rack or even disassembling structural components to move the DIP switches. Utility Model Content

[0003] The purpose of this invention is to provide an automatic switching multi-FPGA chip debugging system to solve the problems existing in the prior art.

[0004] The above-mentioned technical objective of this utility model is achieved through the following technical solution:

[0005] An automatically switching multi-FPGA chip debugging system includes a JTAG interface, a network port, a microcontroller logic control circuit, a multiplexer chip, at least two FPGAs, and a power supply circuit. The at least two FPGAs are connected in series to form a JTAG daisy chain. The JTAG interface is used to connect to a JTAG emulator and output a first JTAG signal. The network port is used to receive network debugging signals and transmit them to the microcontroller logic control circuit. The microcontroller logic control circuit is used to convert the network debugging signals into a second JTAG signal and output a switch control signal. The multiplexer chip is used to select and output either the first or the second JTAG signal to the JTAG daisy chain according to the switch control signal. The power supply circuit provides power to the JTAG interface, network port, microcontroller logic control circuit, multiplexer chip, and FPGAs.

[0006] By adopting the above technical solution, both network debugging and local simulation debugging can be supported without any software or hardware reconfiguration. When a network debugging command is received, the microcontroller logic control circuit and multiplexer chip switch to network debugging mode. If no network debugging command is received, or network debugging ends, or a network timeout occurs, the system switches to local simulation debugging, greatly facilitating on-site debugging and improving work efficiency.

[0007] In a further embodiment, the JTAG interface is provided with TDO, TMS, TDI and TCK pins. The TDO pin of the JTAG interface is used to output the TDO signal of the first JTAG signal, the TMS pin is used to output the TMS signal, the TDI pin is used to output the TDI signal, and the TCK pin is used to output the TCK signal.

[0008] By adopting the above technical solution, it is ensured that the four key signals of the first JTAG signal—Test Data Output (TDO), Test Mode Selection (TMS), Test Data Input (TDI), and Test Clock (TCK)—can be transmitted independently through dedicated pins. This provides a standardized signal path for accurate switching of subsequent signals and FPGA debugging, ensuring compliance with the JTAG protocol and accuracy of signal transmission.

[0009] In a further embodiment, the multiplexer chip is a TMUX1574, which has pins 1A, 2A, 3A, 4A, 1B1, 1B2, 2B1, 2B2, 3B1, 3B2, 4B1, and 4B2, a control pin S, an enable pin OE, a power supply pin VCC, and a ground pin GND. The TDO pin of the JTAG interface is electrically connected to pin 1B2 of the multiplexer chip, the TMS pin is electrically connected to pin 2B2, the TDI pin is electrically connected to pin 3B2, and the TCK pin is electrically connected to pin 4B2.

[0010] By adopting the above technical solution, the 4-channel bidirectional multiplexer TMUX1574 is selected as the signal switching core. Its multi-channel characteristics can accurately match the four core signals of JTAG signals: TDO, TMS, TDI, and TCK. The signals of the JTAG interface are connected to the B2 channels of the multiplexer chip (1B2, 2B2, 3B2, and 4B2), realizing the physical connection between the first JTAG signal and the multiplexer chip. This provides the hardware foundation for subsequent selection of this signal via the control pin S. Furthermore, the low latency of the TMUX1574 ensures the real-time transmission of JTAG signals, meeting the requirements for signal synchronization during debugging.

[0011] In a further embodiment, each of the plurality of FPGAs includes TDO, TMS, TDI, TCK, VP_0, VN_0, M0, M1 and M2 pins. The TMS and TCK pins of the plurality of FPGAs are connected to each other in a one-to-one correspondence. The M0, M1 and M2 pins of the plurality of FPGAs are connected to each other in a one-to-one correspondence. They are connected to the VCC of the power supply circuit through a first resistor. The VP_0 and VN_0 pins of the FPGAs are interconnected and both are grounded.

[0012] By adopting the above technical solution, the TMS and TCK pins are connected together to ensure that all FPGAs receive the mode control signal and clock signal synchronously, which meets the timing requirements of JTAG daisy chain; the M0, M1, and M2 pins are pulled up to VCC through the first resistor, which can stably configure the FPGA to enter the JTAG debug mode and avoid mode errors caused by floating pins; the VP_0 and VN_0 pins are grounded as differential references, which can reduce the interference of external noise on the JTAG signal and improve the stability and anti-interference capability of multi-FPGA chain debugging.

[0013] In a further embodiment, the microcontroller logic control circuit uses an FMQL10S400 chip. The microcontroller logic control circuit has pins C20, B19, B20, and J15, and a switch control signal output terminal G14. Pin C20 of the microcontroller logic control circuit is used to output the TDO signal of the second JTAG signal, pin B19 is used to output the TMS signal, pin B20 is used to output the TDI signal, and pin J15 is used to output the TCK signal. The TDO signal is electrically connected to pin 1B1 of the multiplexer chip, the TMS signal is electrically connected to pin 2B1, the TDI signal is electrically connected to pin 3B1, and the TCK signal is electrically connected to pin 4B1. The switch control signal output terminal G14 of the microcontroller logic control circuit is electrically connected to the control pin S of the multiplexer chip.

[0014] By adopting the above technical solution, the FMQL10S400 chip combines network signal processing and logic control capabilities. It can accurately convert network debugging signals received from the network port into a second JTAG signal (TDO, TMS, TDI, TCK), and input these signals to a multiplexer chip via channels B1 (1B1, 2B1, 3B1, 4B1), achieving hardware adaptation of the network debugging signals. Simultaneously, its output switch control signal is directly connected to the control pin S of the multiplexer chip, enabling precise control of signal channel switching. This provides the core control logic for automatic switching between network debugging and local debugging, ensuring rapid and reliable switching response.

[0015] In a further embodiment, the OE and ground pin GND of the multiplexer chip are both grounded, the power supply pin VCC is electrically connected to the VCC output terminal of the power supply circuit, the control pin S of the multiplexer chip is electrically connected to the VCC output terminal of the power supply circuit through a second resistor, and the switch control signal output terminal G14 is connected between the control pin S and the second resistor.

[0016] By adopting the above technical solution, grounding the OE pin keeps the multiplexer chip in an enabled state, ensuring real-time signal transmission; power supply to the VCC pin ensures normal chip operation; the control pin S is pulled up to VCC through a second resistor, allowing the chip to default to selecting channel B2, the first JTAG signal, when the microcontroller does not output a control signal, avoiding signal confusion caused by the pin being left floating and improving the system's default operating stability; at the same time, the switch control signal output terminal G14 is directly connected to the control pin S, allowing for rapid channel switching via the high and low levels output by the microcontroller, balancing default state reliability and switching flexibility.

[0017] In a further embodiment, the 1A of the multiplexer chip is connected to the TDI of the first FPGA, the TDO of the first FPGA is connected to the TDI of the second FPGA, and so on. The 3A of the multiplexer chip is connected to the TCK of the first FPGA, the 4A of the multiplexer chip is connected to the TMS of the first FPGA, and the 2A of the multiplexer chip is connected to the TDO of the last FPGA.

[0018] By adopting the above technical solution, the TDI signal output by 1A is input from the first FPGA and transmitted to all FPGAs through the TDO-TDI cascade between FPGAs, realizing the chain transmission of debugging commands; the TCK signal output by 3A and the TMS signal output by 4A are connected to the first FPGA and synchronized to all FPGAs through the common pin between FPGAs to ensure timing consistency; 2A receives the TDO signal from the last FPGA to realize the summary and feedback of debugging data from all FPGAs, ensuring that the signal output by the multi-channel selection chip can accurately cover all FPGAs and that the feedback signal can be completely transmitted back, realizing efficient collaborative debugging of multiple FPGAs.

[0019] In summary, this utility model has the following beneficial effects:

[0020] 1. The TDI signal output by 1A is input from the first FPGA and transmitted to all FPGAs through the TDO-TDI cascade between FPGAs, realizing the chain transmission of debugging commands; the TCK signal output by 3A and the TMS signal output by 4A are connected to the first FPGA and synchronized to all FPGAs through the common pin between FPGAs to ensure timing consistency; 2A receives the TDO signal from the last FPGA to realize the summary and back transmission of debugging feedback data from all FPGAs, ensuring that the signal output by the multi-channel selection chip can accurately cover all FPGAs and that the feedback signal can be completely transmitted back, realizing the effect of efficient collaborative debugging of multiple FPGAs. Attached Figure Description

[0021] Figure 1 This is the overall flowchart of this utility model;

[0022] Figure 2This is a flowchart of the network debugging and simulation debugging switching process of this utility model;

[0023] Figure 3 This is a schematic diagram of the multi-channel selection chip of this utility model;

[0024] Figure 4 This is a schematic diagram of the microcontroller logic control circuit of this utility model;

[0025] Figure 5 This is the schematic diagram of the FPGA of this utility model. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings.

[0027] Identical parts are indicated by the same reference numerals. It should be noted that the terms "front," "rear," "left," "right," "upper," and "lower" used in the following description refer to the attached figures. Figure 1 In this specification, the terms "bottom surface" and "top surface," "inner" and "outer" refer to the direction toward or away from the geometry of a specific component. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this specification, "a plurality of" means two or more, unless otherwise explicitly and specifically defined by the direction of the center.

[0028] Example 1:

[0029] like Figures 1-5 As shown, an automatic switching multi-FPGA chip debugging system includes a JTAG interface, a network port, a microcontroller logic control circuit, a multiplexer chip, at least two FPGAs, and a power supply circuit. At least two FPGAs are connected in series to form a JTAG daisy chain. The JTAG interface is used to connect to a JTAG emulator and output a first JTAG signal. The network port is used to receive network debugging signals and transmit them to the microcontroller logic control circuit. The microcontroller logic control circuit converts the network debugging signals into a second JTAG signal and outputs a switch control signal. The multiplexer chip selects to output either the first or second JTAG signal to the JTAG daisy chain based on the switch control signal. The power supply circuit provides power to the JTAG interface, network port, microcontroller logic control circuit, multiplexer chip, and FPGAs.

[0030] The JTAG interface has TDO, TMS, TDI, and TCK pins. The TDO pin is the test data output pin, used to send debug feedback data from the FPGA back to the JTAG emulator. The TMS pin is the test mode selection pin, controlling the switching of the JTAG state machine between different modes through high and low level changes. The TDI pin is the test data input pin, receiving debug commands from the JTAG emulator. The TCK pin is the test clock pin, providing a synchronization clock signal to ensure all JTAG operations are executed in a unified timing sequence. The TDO pin of the JTAG interface is used to output the TDO signal of the first JTAG signal, the TMS pin is used to output the TMS signal, the TDI pin is used to output the TDI signal, and the TCK pin is used to output the TCK signal.

[0031] The multiplexer chip is TMUX1574, with pins 1A, 2A, 3A, 4A, 1B1, 1B2, 2B1, 2B2, 3B1, 3B2, 4B1, and 4B2, a control pin S, an enable pin OE, a power supply pin VCC, and a ground pin GND. Pins 1A, 2A, 3A, and 4A are common outputs used to transmit the selected JTAG signal to the FPGA daisy chain. Pins 1B1, 2B1, 3B1, and 4B1 are inputs to channel B1, receiving the second JTAG signal converted by the microcontroller's logic control circuit. Pins 1B2, 2B2, 3B2, and 4B2 are inputs to channel B2, receiving the first JTAG signal output from the JTAG interface. The control pin S switches between channels by high and low levels: a high level selects channel B2, and a low level selects channel B1. The enable pin OE is active low, controlling whether the chip is operational. The power supply pin VCC and the ground pin GND provide the operating voltage and signal reference ground, respectively. The TDO pin of the JTAG interface is electrically connected to pin 1B2 of the multiplexer chip, the TMS pin is electrically connected to pin 2B2, the TDI pin is electrically connected to pin 3B2, and the TCK pin is electrically connected to pin 4B2. A 4-channel bidirectional multiplexer TMUX1574 is selected as the signal switching core. Its multi-channel characteristics can accurately match the four core signals of the JTAG signal, and its bidirectional transmission capability supports bidirectional communication for debugging command issuance and feedback data return. The JTAG interface signal is connected to the B2 channel of the multiplexer chip, realizing the physical connection between the first JTAG signal and the multiplexer chip.

[0032] Multiple FPGAs each include pins TDO, TMS, TDI, TCK, VP_0, VN_0, M0, M1, and M2. TDO is the test data output pin, outputting debug feedback data for this FPGA. TDI is the test data input pin, receiving debug commands from the preceding FPGA or multiplexer chip. TMS is the test mode selection pin, receiving mode control signals to switch operating modes. TCK is the test clock pin, receiving a synchronization clock to ensure operational timing. M0, M1, and M2 are configuration mode pins; their combined levels determine the FPGA's startup and debug modes. VP_0 and VN_0 are JTAG differential signal reference pins, used to stabilize differential signals and reduce noise interference. The TMS and TCK pins of multiple FPGAs are interconnected one-to-one, as are the M0, M1, and M2 pins, and are connected to the VCC of the power supply circuit via a first resistor. The VP_0 and VN_0 pins of the FPGAs are interconnected and both grounded.

[0033] The microcontroller logic control circuit uses the FMQL10S400 chip. The circuit includes pins C20, B19, B20, and J15, and a switch control signal output terminal G14. Pin C20 outputs the TDO signal for the second JTAG signal; pin B19 outputs the TMS signal; pin B20 outputs the TDI signal; and pin J15 outputs the TCK signal. The TDO signal is electrically connected to pin 1B1 of the multiplexer chip; the TMS signal is electrically connected to pin 2B1; the TDI signal is electrically connected to pin 3B1; and the TCK signal is electrically connected to pin 4B1. Furthermore, the switch control signal output terminal G14 is electrically connected to the control pin S of the multiplexer chip.

[0034] The OE and GND pins of the multiplexer chip are both grounded. The power supply pin VCC is electrically connected to the VCC output of the power supply circuit. The control pin S of the multiplexer chip is electrically connected to the VCC output of the power supply circuit through a second resistor. A switch control signal output terminal G14 is connected between the control pin S and the second resistor. The OE pin is grounded because it is active low. Being grounded ensures that the multiplexer chip is always enabled, ensuring real-time signal transmission and avoiding debugging interruptions caused by fluctuations in the enable signal. The power supply pin VCC is connected to the output of the power supply circuit to provide a stable operating voltage for the chip, ensuring the normal operation of the internal switching circuit. The control pin S is pulled up to VCC through the second resistor to ensure that pin S is at a high level by default when the microcontroller does not output a control signal, thus defaulting to channel B2, the first JTAG signal, avoiding signal confusion caused by a floating pin and improving the system's default operating stability. The switch control signal output terminal G14 is directly connected to the control pin S, and the high or low level output by the microcontroller can quickly override the effect of the pull-up resistor to achieve instant channel switching.

[0035] The 1A of the multiplexer chip is connected to the TDI of the first FPGA, the TDO of the first FPGA is connected to the TDI of the second FPGA, and so on. The 3A of the multiplexer chip is connected to the TCK of the first FPGA, the 4A of the multiplexer chip is connected to the TMS of the first FPGA, and the 2A of the multiplexer chip is connected to the TDO of the last FPGA. 1A connects to the TDI of the first FPGA because TDI is the instruction input terminal. Debug instructions need to be transmitted from the first FPGA, and then the first TDO connects to the TDI of the next FPGA in a chain connection to ensure that instructions can be passed to all FPGAs step by step, achieving comprehensive coverage of debug instructions. 3A connects to the TCK of the first FPGA, and 4A connects to the TMS of the first FPGA. The TCK and TMS of all FPGAs are shorted to each other because the clock signal and mode control signal need to act synchronously on all FPGAs. By connecting the first FPGA and then synchronizing it to other FPGAs, signal delay differences can be reduced, ensuring that the JTAG state machines of each FPGA operate synchronously. 2A connects to the TDO of the last FPGA because the TDO signal of the last FPGA has collected the feedback data from all the preceding FPGAs. Connecting 2A allows the debug results of all FPGAs to be uniformly transmitted back to the multiplexer chip, and then switched to the corresponding channel for output.

[0036] Specific implementation process: The power supply circuit immediately supplies power to the JTAG interface, network port, microcontroller logic control circuit (FMQL10S400), multiplexer chip (TMUX1574), and all FPGAs. The M0, M1, and M2 pins of multiple FPGAs are pulled up to the power supply circuit VCC through the first resistor, and stably configured in JTAG debug mode. The VP_0 and VN_0 pins are interconnected and grounded to reduce noise. The TMS and TCK pins are shorted to each other. The TDO and TDI pins are cascaded according to the first TDO and the second TDI to form a JTAG daisy chain. The enable pin OE of the TMUX1574 is grounded and always enabled. The power supply pin VCC is connected to the power supply. The control pin S is pulled up to VCC through the second resistor, defaults to high level, and selects the B2 channel corresponding to the JTAG interface. After the FMQL10S400 completes hardware initialization, the switch control signal output terminal G14 is in a high impedance state and starts network port detection. The JTAG interface and network port enter the waiting access and waiting connection states, respectively.

[0037] After initialization, if no valid network debugging signal is detected on the network port, the system automatically enters the local debugging mode of the JTAG emulator. The first JTAG signal TDO, TMS, TDI, and TCK are output from the JTAG interface and connected to channels 1B2, 2B2, 3B2, and 4B2 of the TMUX1574. Since the control pin S is high by default, the signals are output from channels 1A, 3A, and 4A of the TMUX1574. The TDI signal is daisy-chained to all FPGAs after being input from the first FPGA TDI. The TMS and TCK signals are synchronously transmitted to all FPGAs. After each FPGA executes the debugging command, the feedback data is output from the last FPGA TDO to channel 2A of the TMUX1574, and then transmitted back to the JTAG interface via channel B2. Finally, it is uploaded to the PC debugging software through the emulator.

[0038] When a remote PC sends a debug request to the network port via the XVC protocol, the system switches to network remote debug mode. The network port transmits the received network debug signal to the FMQL10S400. After parsing, the FMQL10S400 converts it into a second JTAG signal and simultaneously outputs a low level to pull down the control pin S of the TMUX1574, switching it to channel B1 1B1, 2B1, 3B1, 4B1. The second JTAG signal is output from TMUX1574 1A, 3A, 4A to the FPGA daisy chain. The FPGA feedback data is transmitted back to the FMQL10S400 via channels 2A and B1, and then converted into Ethernet data packets by the FMQL10S400, which are transmitted to the remote PC via the network port for display by the debug software.

[0039] When the remote PC sends a debug termination command, or the network is disconnected, or the FMQL10S400 detects a network timeout and there are no data packets for 5 consecutive seconds, the FMQL10S400 will first complete the current debug cycle or trigger an abnormal interrupt. Then, it will switch the switch control signal output terminal G14 to a high impedance state. The control pin S of the TMUX1574 will return to a high level under the pull-up effect of the second resistor, switch back to channel B2, and the system will automatically return to the local debug mode of the JTAG emulator.

[0040] If the FMQL10S400 experiences a power supply failure, firmware error, or other malfunction, its switch control signal output terminal G14 will remain in a high-impedance state. At this time, the control pin S of the TMUX1574 will always be at a high level due to the pull-up effect of the second resistor, maintaining the conduction of the B2 channel. Users only need to connect a JTAG emulator to establish a path with the FPGA daisy chain through the JTAG interface, the B2 channel of the TMUX1574, and achieve emergency debugging, avoiding the inability to debug the system due to microcontroller failure.

[0041] In the embodiments disclosed in this utility model, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments disclosed in this utility model according to the specific circumstances.

[0042] This specific embodiment is merely an explanation of the present utility model and is not intended to limit the present utility model. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but as long as they are within the scope of the claims of the present utility model, they are protected by patent law.

Claims

1. A multi-FPGA chip debugging system with automatic switching, characterized in that: The system includes a JTAG interface, a network port, a microcontroller logic control circuit, a multiplexer chip, at least two FPGAs, and a power supply circuit. The at least two FPGAs are connected in series to form a JTAG daisy chain. The JTAG interface is used to connect to a JTAG emulator and output a first JTAG signal. The network port is used to receive network debugging signals and transmit them to the microcontroller logic control circuit. The microcontroller logic control circuit is used to convert the network debugging signals into a second JTAG signal and output a switch control signal. The multiplexer chip is used to select and output either the first or the second JTAG signal to the JTAG daisy chain according to the switch control signal. The power supply circuit provides power to the JTAG interface, network port, microcontroller logic control circuit, multiplexer chip, and FPGAs.

2. The automatic switching multi-FPGA chip debugging system according to claim 1, characterized in that: The JTAG interface is equipped with TDO, TMS, TDI and TCK pins. The TDO pin of the JTAG interface is used to output the TDO signal of the first JTAG signal, the TMS pin is used to output the TMS signal, the TDI pin is used to output the TDI signal, and the TCK pin is used to output the TCK signal.

3. The automatic switching multi-FPGA chip debugging system according to claim 2, characterized in that: The multiplexer chip is a TMUX1574, which has pins 1A, 2A, 3A, 4A, 1B1, 1B2, 2B1, 2B2, 3B1, 3B2, 4B1, and 4B2, a control pin S, an enable pin OE, a power supply pin VCC, and a ground pin GND. The TDO pin of the JTAG interface is electrically connected to pin 1B2 of the multiplexer chip, the TMS pin is electrically connected to pin 2B2, the TDI pin is electrically connected to pin 3B2, and the TCK pin is electrically connected to pin 4B2.

4. The automatic switching multi-FPGA chip debugging system according to claim 3, characterized in that: Each of the FPGAs includes TDO, TMS, TDI, TCK, VP_0, VN_0, M0, M1, and M2 pins. The TMS and TCK pins of the FPGAs are connected to each other in a one-to-one correspondence. The M0, M1, and M2 pins of the FPGAs are also connected to each other in a one-to-one correspondence. They are connected to the VCC of the power supply circuit through a first resistor. The VP_0 and VN_0 pins of the FPGAs are interconnected and both are grounded.

5. The automatic switching multi-FPGA chip debugging system according to claim 3, characterized in that: The microcontroller logic control circuit uses the FMQL10S400 chip. The microcontroller logic control circuit has pins C20, B19, B20, and J15, and a switch control signal output terminal G14. Pin C20 is used to output the TDO signal of the second JTAG signal, pin B19 is used to output the TMS signal, pin B20 is used to output the TDI signal, and pin J15 is used to output the TCK signal. The TDO signal is electrically connected to pin 1B1 of the multiplexer chip, the TMS signal is electrically connected to pin 2B1, the TDI signal is electrically connected to pin 3B1, and the TCK signal is electrically connected to pin 4B1. Furthermore, the switch control signal output terminal G14 of the microcontroller logic control circuit is electrically connected to the control pin S of the multiplexer chip.

6. The automatic switching multi-FPGA chip debugging system according to claim 5, characterized in that: The OE and ground pins GND of the multiplexer chip are both grounded, and the power supply pin VCC is electrically connected to the VCC output terminal of the power supply circuit. The control pin S of the multiplexer chip is electrically connected to the VCC output terminal of the power supply circuit through a second resistor. The switch control signal output terminal G14 is connected between the control pin S and the second resistor.

7. The automatic switching multi-FPGA chip debugging system according to claim 3, characterized in that: The 1A of the multiplexer chip is connected to the TDI of the first FPGA, the TDO of the first FPGA is connected to the TDI of the second FPGA, and so on. The 3A of the multiplexer chip is connected to the TCK of the first FPGA, the 4A of the multiplexer chip is connected to the TMS of the first FPGA, and the 2A of the multiplexer chip is connected to the TDO of the last FPGA.

Images