A USB isolation expander

Abstract

The utility model discloses a USB isolation expander, include: main control unit, voltage stabilizing power supply, computer, power isolation module, card reader module, host computer, lower level machine, USB current -limiting module, two -way current / power consumption monitor, debugging interface and contain one control chip and four USB downstream port's USB -HUB control module, AD converter, computer gives voltage stabilizing power supply and power isolation module power supply, voltage stabilizing power supply module provides voltage stabilizing power supply, power isolation module provides isolated power supply, current -limiting module is the power supply for USB downstream port, and computer and host computer, lower level machine and control chip, control chip and a plurality of USB downstream port, lower level machine and main control unit between through USB connection, and host computer and lower level machine pass through the capacitor coupling isolation, and debugging interface connects main control unit and external embedded equipment, and USB downstream port passes through ADC and connects monitor, the utility model discloses has realized the isolation expansion of USB.

Description

Technical Field

[0001] This utility model relates to the field of USB extension technology, and in particular to a USB isolation extender. Background Technology

[0002] In embedded development, developers often need to use serial debugging tools, ST-Link debuggers, and JTAG debuggers simultaneously, all of which require USB ports on the computer. However, ordinary computers have a limited number of USB ports and lack electrical isolation capabilities. When debugging high-voltage, high-current embedded systems, operational errors or accidental short circuits can cause high voltage to backflow into the host computer via the debugging interface, potentially burning out the USB port or even damaging the motherboard, resulting in significant financial losses. Therefore, it is essential to introduce electrical isolation mechanisms or select debugging equipment with isolation capabilities to block the transmission path of dangerous signals at the source, effectively ensuring the safety of the development process and the stability of the hardware. Summary of the Invention

[0003] The purpose of this utility model is to solve the problem of the limited number of computer USB ports and the lack of electrical isolation function, and to propose a USB isolation extender, comprising: ESP32-C3 main control unit, regulated power supply, computer, power isolation module, card reader module, host computer, slave computer, USB current limiting module, bidirectional current / power consumption monitor, debugging interface, USB-HUB control module, analog-to-digital converter; The USB-HUB control module includes a USB-HUB control chip and four USB downstream ports; The computer is used to provide power to the regulated power supply and power isolation module; The voltage regulator is used to provide regulated power to the card reader module and the host computer; The power isolation module is used to provide isolated power to the ESP32-C3 main control unit, lower-level machine, USB current limiting module, bidirectional current / power consumption monitor, debugging interface and USB-HUB control module; The USB current limiting module is used to provide current-limited power to the four USB downstream ports; The computer and the host computer are connected via USB. The host computer and the slave computer are isolated by capacitive coupling; The lower-level computer and the ESP32-C3 main control unit are connected via USB; The debugging interface connects the ESP32-C3 main control unit to external embedded devices; The lower-level machine and the USB-HUB control chip are connected via USB; The USB-HUB control chip and multiple USB downstream ports are connected via USB; The USB downstream port is connected to a bidirectional current / power consumption monitor via an analog-to-digital converter.

[0004] Furthermore, the voltage regulator circuit includes: chip U10, capacitor C30, and capacitor C31; chip U10 is an ME6210A33M3G chip; pin 3 of chip U10 is connected to the 5V power supply provided by the computer; one end of capacitor C31 is connected to pin 3 of chip U10, and the other end of capacitor C31 is grounded; one end of capacitor C30 is connected to pin 2 of chip U10, and the other end of capacitor C30 is grounded; pin 2 of chip U10 outputs a 3.3V VDD power supply. Further, the power isolation module circuit includes: chip U8, chip U9, low dropout regulator, Type-C interface USB1, capacitors C18, C19, C20, C24, C25, C26, C27, C28, diode D1, resistor R24, and resistor R27; chip U8 uses B0505S-3WR2, chip U9 uses CH213K, and the low dropout regulator uses AMS1117-3.3; pin 1 of chip U8 is connected to the 5V power supply provided by the computer, pin 2 of chip U8 is grounded, pin 4 of chip U8 is isolated and grounded, pin 6 of chip U8 is connected to pin 3 of chip U9, and pin 1 of chip U9 is isolated and grounded; one end of capacitor C18 is connected to pin 1 of chip U8, and the other end of capacitor C18 is grounded; one end of capacitor C19 is connected to pin 3 of chip U9, and the other end of capacitor C19 is isolated and grounded; capacitor C20... The two ends are connected to pins 1 and 2 of chip U9 respectively; pin 2 of chip U9 outputs a 5V isolated power supply; capacitors C26, C27, and C28 are connected in parallel and their two ends are connected to pins 1 and 2 of the low dropout regulator respectively; pin 1 of the low dropout regulator is isolated and grounded; capacitors C24 and C25 are connected in parallel, one end is connected to pin 3 of the low dropout regulator, and the other end is isolated and grounded; pin 3 of the low dropout regulator is also connected to a 5V isolated power supply; pins 2 and 4 of the low dropout regulator output a 3.3V isolated power supply; the VBUS signal of USB1 is connected to the 5V power supply provided by the computer through diode D1, the CC2 signal of USB1 is grounded through resistor R24, the DP1 and DP2 signals of USB1 are shorted, the DN1 and DN2 signals of USB1 are shorted, the CC1 signal of USB1 is grounded through resistor R27, the two VBUS signals of USB1 are shorted, and the GND signal of USB1 is grounded.

[0005] Furthermore, the ESP32-C3 main control unit circuit includes: chip U1, capacitors C1, C2, C3, C6, C7, resistors R1, R12, R19, reset button SW1, and reset button SW2; chip U1 uses chip ESP32-C3-MINI-1-N4. Capacitors C1 and C2 are connected in parallel, with one end connected to pin 3 of chip U1 and the other end grounded. An isolation power supply is connected to pin 3 of chip U1, one end of resistor R1, one end of resistor R12, and one end of resistor R19. The other end of resistor R1 is connected to pin 8 of chip U1, the other end of resistor R12 is connected to pin 22 of chip U1, and the other end of resistor R19 is connected to pin 23 of chip U1. One end of capacitor C3 is connected to pin 8 of chip U1, and the other end of capacitor C3 is grounded. Pins 1, 2, 11, and 36-53 of chip U1 are isolated and grounded; pin 1 of reset button SW1 is isolated and grounded, and pin 4 of reset button SW1 is connected to pin 8 of chip U1; one end of capacitor C6 is connected to pin 8 of chip U1, and the other end of capacitor C6 is isolated and grounded; pin 1 of reset button SW2 is isolated and grounded, and pin 4 of reset button SW2 is connected to pin 23 of chip U1; one end of capacitor C7 is connected to pin 23 of chip U1, and the other end of capacitor C7 is isolated and grounded.

[0006] Furthermore, the debugging interface circuit includes: SWD interface, JTAG interface, serial port interface, bidirectional TVS diodes D3, D5, D6, D7, D8, D9, D10, D11, and protection power supply circuit; the protection power supply circuit consists of PMOS transistor Q2, Schottky diode D4, and current limiting resistor R53. Connect the SWCLK signal line of the SWD interface to pin 20 of chip U1; connect the SWDIO signal line of the SWD interface to pin 21 of chip U1; connect the NTRST signal line of the JTAG interface to pin 18 of chip U1; connect the NRESET signal line of the JTAG interface to pin 19 of chip U1; connect the TCK signal line of the JTAG interface to pin 20 of chip U1; connect the TMS signal line of the JTAG interface to pin 21 of chip U1; connect the TDO signal line of the JTAG interface to pin 22 of chip U1; connect the TDI signal line of the JTAG interface to pin 23 of chip U1; connect the RX signal line of the serial port interface to pin 30 of chip U1; connect the TX signal line of the serial port interface to pin 31 of chip U1. The SWCLK and SWDIO signals of the SWD interface are isolated and grounded after passing through bidirectional TVS diodes D3 and D6, respectively. The TDI, TDO, NTRST, and NRESET signals of the JTAG interface are isolated and grounded after passing through bidirectional TVS diodes D8, D7, D6, and D9, respectively. The RX and TX signals of the serial port interface are isolated and grounded after passing through bidirectional TVS diodes D10 and D11, respectively. The GND signals of the SWD interface, serial port interface, and JTAG interface are isolated and grounded. The power signal is connected to a 3.3V protection power supply, which is generated by the protection power supply circuit. The source of PMOS transistor Q2 is connected to the 3.3V isolation power supply. One end of resistor R53 is connected to the gate of PMOS transistor Q2, and the other end of resistor R53 is isolated and grounded. One end of diode D4 is connected to the drain of PMOS transistor Q2, and the other end of diode D4 is isolated and grounded. The 3.3V protection power supply is output from the drain of PMOS transistor Q2.

[0007] Furthermore, the host computer circuit includes: chip U6, capacitors C12, C16, C17, C21, C29, crystal oscillator X1, and resistor R26; chip U6 uses chip CH318T; crystal oscillator X1 uses CMOS active crystal oscillator YSO110TR. One end of capacitor C12 is grounded, and the other end of capacitor C12 is connected to pin 5 of chip U6; capacitors C16 and C17 are connected in parallel, and their two ends are connected to pins 15 and 16 of chip U6, respectively; pin 15 of chip U6 is grounded, and pin 16 of chip U6 is connected to VDD power supply; one end of capacitor C21 is connected to pin 14 of chip U6, and the other end of capacitor C21 is grounded; the Tri-state signal of crystal oscillator X1 is connected to pin 3 of chip U6, the GND signal of crystal oscillator X1 is grounded, the output signal of crystal oscillator X1 is connected to pin 4 of chip U6, and the VDD signal of crystal oscillator X1 is grounded; the two ends of capacitor C29 are connected to the Tri-state signal and VDD signal of crystal oscillator X1, respectively; one end of resistor R26 is connected to pin 3 of crystal oscillator X1, and the other end of resistor R26 is grounded.

[0008] Furthermore, the lower-level circuit includes: chip U7, capacitors C10, C11, C13, C14, C15, C22, C32, resistors R25 and R28, and crystal oscillator X2; chip U7 uses chip CH318T; crystal oscillator X2 uses CMOS active crystal oscillator YSO110TR. One end of capacitor C10 is connected to pin 1 of chip U7, and the other end is connected to pin 1 of chip U6; one end of capacitor C15 is connected to pin 2 of chip U7, and the other end is connected to pin 2 of chip U6; one end of capacitor C13 is connected to pin 5 of chip U7, and the other end is grounded; capacitors C11 and C14 are connected in parallel, with their ends connected to pins 15 and 16 of chip U7 respectively; pin 15 of chip U7 is grounded, and pin 16 of chip U7 is connected to VDD power supply; one end of capacitor C22... One end of capacitor C22 is connected to pin 14 of chip U7, and the other end of capacitor C22 is isolated and grounded; one end of resistor R25 is connected to pin 13 of chip U7, and the other end of resistor R25 is isolated and grounded; pin 1 of crystal oscillator X2 is connected to pin 3 of U7, pin 2 of crystal oscillator X2 is isolated and grounded, pin 3 of crystal oscillator X2 is connected to pin 4 of U7, and pin 4 of crystal oscillator X2 is isolated and grounded; the two ends of capacitor C32 are connected to pin 1 and pin 4 of crystal oscillator X2 respectively; one end of resistor R28 is connected to pin 3 of crystal oscillator X2, and the other end of resistor R28 is isolated and grounded.

[0009] Furthermore, the four bidirectional current / power consumption monitors correspond to the four USB downstream ports respectively. The circuit principle of the four bidirectional current / power consumption monitors is the same. One of the bidirectional current / power consumption monitor circuits includes: chip U2, resistor R2, resistor R3, resistor R6, resistor R8, resistor R9, and capacitor C4; chip U2 uses chip INA226AIDGSR. One end of resistor R3 is connected to pin 1 of chip U2, and the other end of resistor R3 is connected to the isolated power supply or isolated ground; one end of resistor R2 is connected to pin 2 of chip U2, and the other end of resistor R2 is connected to the isolated power supply or isolated ground; the two ends of resistor R6 are connected to pins 9 and 10 of chip U2 respectively; pin 9 of chip U2 is connected to the GND pin of the USB downstream port, and pin 10 of chip U2 is connected to the VCC pin of the USB downstream port; one end of resistor R8 is connected to pin 4 of chip U2, and one end of resistor R9 is connected to pin 5 of chip U2. The other ends of resistors R8 and R9 are connected to the isolated power supply; pin 4 of chip U2 is connected to pin 6 of chip U1, and pin 5 of chip U2 is connected to pin 16 of chip U1.

[0010] Furthermore, the USB current limiting module and USB-HUB control module circuit includes: chip U13, chip U16, crystal oscillator X3, capacitors C35, C36, C37, C38, C39, C44, C45, C46, ​​and C47; resistors R35, R36, R42, R43, R45, and R47; and four downstream USB ports: USB6, USB7, USB8, and USB9. Chip U13 uses chip CH334U, and chip U16 uses chip CH217K. Pins 1, 12, and 28 of chip U13 are isolated and grounded; capacitors C44 and C45 are connected in parallel, with one end isolated and grounded, and the other end connected to pin 13 of chip U13; pin 13 of chip U13 is also connected to an isolated power supply; capacitors C37, C38, and C39 are connected in parallel, with one end isolated and grounded, and the other end connected to pins 20 and 21 of chip U13; pins 20 and 21 of chip U13 are also connected to an isolated power supply; pin 1 of crystal oscillator X3 is connected to pin 2 of chip U13. Pin 1 of crystal oscillator X3 is isolated to ground, and pin 2 and pin 4 of crystal oscillator X3 are connected to pin 3 of chip U13. The two ends of capacitor C46 are connected to pins 1 and 4 of crystal oscillator X3, and the two ends of capacitor C47 are connected to pins 2 and 3 of crystal oscillator X3. One end of resistors R42, R43, R45, and R47 is connected to pin 1 of chip U16, and the other end is connected to pin 10 of the corresponding chip INA226AIDGSR. Capacitor C35... One end of the capacitor C35 is connected to pin 1 of chip U16, and the other end of the capacitor C35 is grounded for isolation. Pin 2 of chip U16 is grounded for isolation. Pin 3 of chip U16 is connected to pin 26 of chip U13. One end of resistor R36 is connected to pin 3 of chip U16, and the other end of resistor R36 is connected to a 3.3V isolated power supply. Pin 4 of chip U16 is connected to pin 25 of chip U13. One end of resistor R35 is connected to pin 5 of chip U16, and the other end of resistor R35 is grounded for isolation. One end of capacitor C36 is connected to pin 6 of chip U16, and the other end of capacitor C36 is grounded for isolation. Pin 6 of chip U16 is also connected to a 5V isolated power supply. The VCC power lines of USB6~USB9 are connected to pin 9 of the corresponding chip INA226AIDGSR, and GND is grounded for isolation. The D+ and D- signal lines are connected to the four sets of positive and negative data signal lines of pins 4~11 of chip U13, respectively. A 5V power supply is output from pin 1 of chip U16.

[0011] Furthermore, the card reader module circuit includes: chip U15, SD card connector, capacitor C34, capacitor C40, capacitor C41, and capacitor C42; chip U15 uses GL823K-HCY04, and the SD card connector uses TF PUSH; pin 1 of chip U15 is grounded, and the signals of pins 2-8 and pin 11 of chip U15 are respectively connected to the corresponding pins of the SD card connector. The VSS signal of the SD card connector is grounded. One end of capacitor C34 is connected to pin 13 of chip U15, and the other end of capacitor C34 is grounded. Pin 13 of chip U15 is also connected to a 3.3V VDD power supply, and pin 10 of chip U15 is connected to a 5V power supply provided by the computer; one end of capacitor C40 is connected to pin 8 of chip U15, and the other end of capacitor C40 is grounded; capacitors C41 and C42 are connected in parallel, with one end connected to pin 9 of chip U15 and the other end grounded; pin 9 of chip U15 is also connected to a 3.3V VDD power supply.

[0012] The beneficial effects of the technical solution provided by this utility model are: This invention proposes a USB isolation extender based on the ESP32-C3 minimum system. This system not only supports USB interface expansion but also integrates multi-mode debugging capabilities for embedded devices, including JTAG debugging, SWD debugging, and serial port debugging. The overall system architecture consists of multiple functional modules. Under the unified scheduling of the ESP32-C3 main control unit, these modules collaboratively achieve core functions such as USB signal electrical isolation, intelligent power management, efficient data interaction, and peripheral function expansion. While ensuring system security and operational stability, it also possesses good scalability and practicality. Attached Figure Description

[0013] Figure 1 This is an overall structural block diagram of a USB isolation extender according to this utility model; Figure 2 This is the circuit diagram of the regulated power supply of this utility model; Figure 3 This is a circuit diagram of the power isolation module of this utility model; Figure 4 This is the circuit schematic diagram of the ESP32-C3 main control unit of this utility model; Figure 5 This is the circuit schematic diagram of the debugging interface of this utility model; Figure 6 This is the circuit diagram of the host computer of this utility model; Figure 7 This is the circuit schematic diagram of the lower-level machine of this utility model; Figure 8 This is the circuit schematic of the bidirectional current / power consumption monitor of this utility model; Figure 9 This invention relates to the circuit principles of the USB current limiting module and the USB-HUB control module. Figure 10 This is the circuit diagram of the card reader module of this utility model. Detailed Implementation

[0014] To make the objectives, technical solutions and advantages of this utility model clearer, the embodiments of this utility model will be further described below with reference to the accompanying drawings.

[0015] The overall structural block diagram of a USB isolation extender according to this utility model is as follows: Figure 1 Specifically, it includes: The system includes an ESP32-C3 main control unit, a regulated power supply, a computer, a power isolation module, a card reader module, a host computer, a slave computer, a USB current limiting module, a bidirectional current / power consumption monitor, a debug interface, a USB-HUB control module, and an analog-to-digital converter (ADC). The USB-HUB control module includes a USB-HUB control chip and four USB downstream ports; The computer is used to provide power to the regulated power supply and power isolation module; The voltage regulator is used to provide regulated power to the card reader module and the host computer; The power isolation module is used to provide isolated power to the ESP32-C3 main control unit, lower-level machine, USB current limiting module, bidirectional current / power consumption monitor, debugging interface and USB-HUB control module; The USB current limiting module is used to provide current-limited power to the four USB downstream ports; The computer and the host computer are connected via USB. The host computer and the slave computer are isolated by capacitive coupling; The lower-level computer and the ESP32-C3 main control unit are connected via USB; The debugging interface connects the ESP32-C3 main control unit to external embedded devices; The lower-level machine and the USB-HUB control chip are connected via USB; The USB-HUB control chip and multiple USB downstream ports are connected via USB; The USB downstream port is connected to a bidirectional current / power consumption monitor via an analog-to-digital converter.

[0016] The specific circuit diagrams for each part are as follows: (1) Regulated power supply Circuit diagram reference for regulated power supply Figure 2This circuit is primarily used to provide a 3.3V VDD power supply to the host computer and card reader. The voltage regulator circuit includes: chip U10, capacitor C30, and capacitor C31; chip U10 is an ME6210A33M3G chip, and capacitors C30 and C31 are 10uF.

[0017] Pin 3 of chip U10 is connected to the 5V power supply provided by the computer. One end of capacitor C31 is connected to pin 3 of chip U10, and the other end of capacitor C31 is grounded. One end of capacitor C30 is connected to pin 2 of chip U10, and the other end of capacitor C30 is grounded. Pin 2 of chip U10 outputs a 3.3V VDD power supply.

[0018] (2) Power isolation module Circuit schematic reference for power isolation module Figure 3 This power isolation module is primarily used to achieve electrical isolation between the computer power supply and the USB expansion power supply. The power isolation module circuit includes: chip U8, chip U9, a low-dropout regulator, a Type-C interface USB1, and multiple sets of decoupling and filtering capacitors: capacitors C18, C19, C20, C24, C25, C26, C27, and C28; diode D1; and resistors R24 and R27. Chip U8 uses the isolated DC-DC power module B0505S-3WR2. Chip U9 uses the USB power management and protection chip CH213K. This chip integrates overcurrent, short-circuit, over-temperature, and reverse polarity protection functions, effectively improving the system's safety and reliability. The low dropout voltage regulator uses AMS1117-3.3. Capacitors C18, C19, C24, and C27 are 10uF, capacitors C20 and C26 are 1uF, capacitors C25 and C28 are 100nF, and resistors R24 and R27 are 5.1kΩ.

[0019] Pin 1 of chip U8 is connected to the 5V power supply provided by the computer; pin 2 of chip U8 is grounded; pin 4 of chip U8 is isolated and grounded; pin 6 of chip U8 is connected to pin 3 of chip U9; pin 1 of chip U9 is isolated and grounded; one end of capacitor C18 is connected to pin 1 of chip U8, and the other end of capacitor C18 is grounded; one end of capacitor C19 is connected to pin 3 of chip U9, and the other end of capacitor C19 is isolated and grounded; the two ends of capacitor C20 are connected to pins 1 and 2 of chip U9 respectively; pin 2 of chip U9 outputs a 5V isolated power supply; capacitors C26, C27, and C28 are connected in parallel, and their two ends are connected to pins 1 and 2 of the low dropout voltage regulator respectively; the low dropout voltage regulator... Pin 1 of the voltage regulator is isolated and grounded; capacitors C24 and C25 are connected in parallel, with one end connected to pin 3 of the low dropout regulator and the other end isolated and grounded; pin 3 of the low dropout regulator is also connected to a 5V isolated power supply; pins 2 and 4 of the low dropout regulator output a 3.3V isolated power supply; the VBUS signal of USB1 is connected to the 5V power supply provided by the computer through diode D1, the CC2 signal of USB1 is grounded through resistor R24, the DP1 and DP2 signals of USB1 are shorted, the DN1 and DN2 signals of USB1 are shorted, the CC1 signal of USB1 is grounded through resistor R27, the two VBUS signals of USB1 are shorted, and the GND signal of USB1 is grounded.

[0020] (3) ESP32-C3 main control unit ESP32-C3 main control unit circuit schematic reference Figure 4 This includes: chip U1, capacitors C1, C2, C3, C6, and C7, resistors R1, R12, and R19, and reset buttons SW1 and SW2. Reset buttons SW1 and SW2 are used to set the boot mode of the ESP32C3. Reset button SW2 defaults to SPI BOOT mode. Chip U1 uses the ESP32-C3-MINI-1-N4 chip. Capacitor C1 is 10uF, capacitors C2, C6, and C7 are 100nF, capacitor C3 is 1uF, and resistors R1, R12, and R19 are 10kΩ.

[0021] Capacitors C1 and C2 are connected in parallel, with one end connected to pin 3 of chip U1 and the other end grounded. An isolation power supply is connected to pin 3 of chip U1, one end of resistor R1, one end of resistor R12, and one end of resistor R19. The other end of resistor R1 is connected to pin 8 of chip U1, the other end of resistor R12 is connected to pin 22 of chip U1, and the other end of resistor R19 is connected to pin 23 of chip U1. One end of capacitor C3 is connected to pin 8 of chip U1, and the other end of capacitor C3 is grounded. Pins 1, 2, 11, and 36-53 of chip U1 are isolated and grounded; pin 1 of reset button SW1 is isolated and grounded, and pin 4 of reset button SW1 is connected to pin 8 of chip U1; one end of capacitor C6 is connected to pin 8 of chip U1, and the other end of capacitor C6 is isolated and grounded; pin 1 of reset button SW2 is isolated and grounded, and pin 4 of reset button SW2 is connected to pin 23 of chip U1; one end of capacitor C7 is connected to pin 23 of chip U1, and the other end of capacitor C7 is isolated and grounded.

[0022] (4) Debugging interface The debugging interface provides program download and serial port debugging functions for external embedded devices. The circuit schematic for the debugging interface is available for reference. Figure 5 The debugging interface circuit includes: SWD interface, JTAG interface, serial port interface, bidirectional TVS diodes D3, D5, D6, D7, D8, D9, D10, and D11, and a protection power supply circuit. The protection power supply circuit prevents external abnormal high voltage or large current from accidentally entering the system, avoiding damage to the main control unit and internal circuits. The protection power supply circuit consists of a PMOS transistor Q2, a Schottky diode D4, and a current-limiting resistor R53. The Schottky diode D4 is a B5819WS, and the resistor R53 is 100kΩ. The SWD and serial port interfaces use a 6-port flexible circuit board, and the JTAG interface uses a connector XH-8PWB. The bidirectional TVS diodes D3, D5, D6, D7, D8, D9, D10, and D11 protect the electronic circuits from damage caused by transient overvoltages (such as electrostatic discharge ESD, surges caused by inductive load switching, lightning strikes, etc.).

[0023] Connect the SWCLK signal line of the SWD interface to pin 20 of chip U1; connect the SWDIO signal line of the SWD interface to pin 21 of chip U1; connect the NTRST signal line of the JTAG interface to pin 18 of chip U1; connect the NRESET signal line of the JTAG interface to pin 19 of chip U1; connect the TCK signal line of the JTAG interface to pin 20 of chip U1; connect the TMS signal line of the JTAG interface to pin 21 of chip U1; connect the TDO signal line of the JTAG interface to pin 22 of chip U1; connect the TDI signal line of the JTAG interface to pin 23 of chip U1; connect the RX signal line of the serial port interface to pin 30 of chip U1; connect the TX signal line of the serial port interface to pin 31 of chip U1.

[0024] The SWCLK and SWDIO signals of the SWD interface are isolated and grounded after passing through bidirectional TVS diodes D3 and D6, respectively. The TDI, TDO, NTRST, and NRESET signals of the JTAG interface are isolated and grounded after passing through bidirectional TVS diodes D8, D7, D6, and D9, respectively. The RX and TX signals of the serial port interface are isolated and grounded after passing through bidirectional TVS diodes D10 and D11, respectively.

[0025] The GND signals of the SWD interface, serial port interface, and JTAG interface are isolated and grounded. The power signal is connected to a 3.3V protection power supply, which is generated by the protection power supply circuit. The input power to the protection power supply circuit is a 3.3V isolated power supply. The source of PMOS transistor Q2 is connected to the 3.3V isolated power supply. One end of resistor R53 is connected to the gate of PMOS transistor Q2, and the other end of resistor R53 is isolated and grounded. One end of diode D4 is connected to the drain of PMOS transistor Q2, and the other end of diode D4 is isolated and grounded. The 3.3V protection power supply is output from the drain of PMOS transistor Q2.

[0026] (5) Host computer Reference circuit schematic of the host computer Figure 6 This includes: chip U6, capacitors C12, C16, C17, C21, and C29, crystal oscillator X1, and resistor R26; chip U6 uses CH318T, crystal oscillator X1 uses CMOS active crystal oscillator YSO110TR, product model: OT322520MJBA4SL, capacitors C12 and C16 are 1uF, capacitors C17 and C21 are 100nF, capacitor C29 is 20pF, and resistor R26 is 4.7MΩ.

[0027] One end of capacitor C12 is grounded, and the other end is connected to pin 5 of chip U6; capacitors C16 and C17 are connected in parallel, with their ends connected to pins 15 and 16 of chip U6, respectively; pin 15 of chip U6 is grounded, and pin 16 of chip U6 is connected to VDD power supply; one end of capacitor C21 is connected to pin 14 of chip U6, and the other end is grounded; pin 1 (Tri-state signal) of crystal oscillator X1 is connected to pin 3 of chip U6, pin 2 (GND signal) of crystal oscillator X1 is grounded, pin 3 (output signal) of crystal oscillator X1 is connected to pin 4 of chip U6, and pin 4 (VDD signal) of crystal oscillator X1 is grounded; the two ends of capacitor C29 are connected to pin 1 (Tri-state signal) and pin 4 (VDD signal) of crystal oscillator X1, respectively; one end of resistor R26 is connected to pin 3 of crystal oscillator X1, and the other end of resistor R26 is grounded.

[0028] This embodiment also provides an LED circuit, with a 3.3V VDD power supply connected in sequence to the LED, a 1kΩ resistor R30, and pin 13 of chip U6.

[0029] (6) Lower-level machine Reference to the circuit schematic of the lower-level machine Figure 7 The system includes: chip U7, capacitors C10, C11, C13, C14, C15, C22, and C32, resistors R25 and R28, and two crystal oscillators. Chip U7 uses a CH318T chip, and crystal oscillator X2 uses a CMOS active crystal oscillator YSO110TR (model number OT322520MJBA4SL). Capacitors C10, C11, C15, and C22 are 100nF, capacitors C13 and C14 are 1uF, capacitor C32 is 20pF, resistor R25 is 5.1kΩ, and resistor R28 is 4.7MΩ. Capacitors C10 and C15 are used to couple the USB differential signal between the host computer and the slave computer, and are key components for achieving signal isolation.

[0030] One end of capacitor C10 is connected to pin 1 of chip U7, and the other end is connected to pin 1 of chip U6; one end of capacitor C15 is connected to pin 2 of chip U7, and the other end is connected to pin 2 of chip U6; one end of capacitor C13 is connected to pin 5 of chip U7, and the other end is grounded; capacitors C11 and C14 are connected in parallel, with their ends connected to pins 15 and 16 of chip U7 respectively; pin 15 of chip U7 is grounded, and pin 16 of chip U7 is connected to VDD power supply; one end of capacitor C22... One end of capacitor C22 is connected to pin 14 of chip U7, and the other end of capacitor C22 is isolated and grounded; one end of resistor R25 is connected to pin 13 of chip U7, and the other end of resistor R25 is isolated and grounded; pin 1 of crystal oscillator X2 is connected to pin 3 of U7, pin 2 of crystal oscillator X2 is isolated and grounded, pin 3 of crystal oscillator X2 is connected to pin 4 of U7, and pin 4 of crystal oscillator X2 is isolated and grounded; the two ends of capacitor C32 are connected to pin 1 and pin 4 of crystal oscillator X2 respectively; one end of resistor R28 is connected to pin 3 of crystal oscillator X2, and the other end of resistor R28 is isolated and grounded.

[0031] (7) Bidirectional current / power consumption monitor A bidirectional current / power consumption monitor is used to monitor the electrical parameters of each USB port in real time, including operating voltage, output current, and instantaneous power consumption. A circuit schematic of the bidirectional current / power consumption monitor is provided for reference. Figure 8 It includes: chip U2, resistors R2, R3, R6, R8, R9, and capacitor C4. Chip U2 uses the INA226AIDGSR chip, resistors R2 and R3 are 10kΩ, resistor R6 is 100mΩ, resistors R8 and R9 are 4.7kΩ, and capacitor C4 is 100nF.

[0032] One end of resistor R3 is connected to pin 1 of chip U2, and the other end of resistor R3 is connected to an isolated power supply or isolated ground; one end of resistor R2 is connected to pin 2 of chip U2, and the other end of resistor R2 is connected to an isolated power supply or isolated ground; the two ends of resistor R6 are connected to pins 9 and 10 of chip U2 respectively; pin 9 of chip U2 is connected to the GND pin of the USB downstream port, and pin 10 of chip U2 is connected to the VCC pin of the USB downstream port; one end of resistor R8 is connected to pin 4 of chip U2, and one end of resistor R9 is connected to pin 5 of chip U2. The other ends of resistors R8 and R9 are connected to an isolated power supply; pin 4 of chip U2 is connected to pin 6 of chip U1, and pin 5 of chip U2 is connected to pin 16 of chip U1; one end of capacitor C4 is connected to pin 6 of chip U2, and the other end is connected to an isolated ground; pin 6 of chip U2 is also connected to a 3.3V isolated power supply.

[0033] This invention features four bidirectional current / power consumption monitors, each corresponding to one of the four USB downstream ports. Each monitor operates on the same circuit principle. The invention also includes three additional bidirectional current / power consumption monitor chips, U3, U4, and U5, all using the INA226AIDGSR chip. Specifically, pins 1 and 2 of chip U2 are grounded via resistor isolation; pins 1 and 2 of chip U3 are grounded and connected to a 3.3V isolated power supply via resistor isolation; pins 1 and 2 of chip U4 are connected to a 3.3V isolated power supply and isolated ground via resistor isolation; and pins 1 and 2 of chip U5 are connected to a 3.3V isolated power supply via resistor isolation.

[0034] (8) USB current limiting module and USB-HUB control module Circuit schematic reference for USB current limiting module and USB-HUB control module Figure 9 This includes: chip U13, chip U16, crystal oscillator X3, capacitors C35, C36, C37, C38, C39, C44, C45, C46, ​​and C47; resistors R35, R36, R42, R43, R45, and R47; and four downstream USB ports: USB6, USB7, USB8, and USB9. Chip U13 uses the CH334U chip, and chip U16 uses the CH217K chip. Capacitors C35 and C36 are 220uF electrolytic capacitors, capacitors C37, C38, and C44 are 10uF, capacitors C39 and C45 are 100nF, and capacitors C46 and C47 are 20pF. Resistor R35 is 25kΩ, resistor R36 is 47kΩ, and resistors R42, R43, R45, and R47 are 0Ω. The USB HUB control circuit provides four downstream USB ports (USB6–USB9). The USB current-limiting power distribution module, based on the CH217K, is responsible for centralized management of the power supply to the four USB ports, and features overcurrent protection, overtemperature protection, and undervoltage protection, effectively improving the system's power safety and operational reliability.

[0035] Pins 1, 12, and 28 of chip U13 are isolated and grounded; capacitors C44 and C45 are connected in parallel, with one end isolated and grounded, and the other end connected to pin 13 of chip U13; pin 13 of chip U13 is also connected to an isolated power supply; capacitors C37, C38, and C39 are connected in parallel, with one end isolated and grounded, and the other end connected to pins 20 and 21 of chip U13; pins 20 and 21 of chip U13 are also connected to an isolated power supply; pin 1 of crystal oscillator X3 is connected to chip U13. Pin 2 of chip U13 is isolated from pins 2 and 4 of crystal oscillator X3. Pin 3 of crystal oscillator X3 is connected to pin 3 of chip U13. The two ends of capacitor C46 are connected to pins 1 and 4 of crystal oscillator X3, and the two ends of capacitor C47 are connected to pins 2 and 3 of crystal oscillator X3. One end of resistors R42, R43, R45, and R47 is connected to pin 1 of chip U16, and the other end is connected to pin 10 of the corresponding chip INA226AIDGSR. Pin configuration: The positive terminal of capacitor C35 is connected to pin 1 of chip U16, and the other end of capacitor C35 is isolated and grounded; pin 2 of chip U16 is isolated and grounded; pin 3 of chip U16 is connected to pin 26 of chip U13; one end of resistor R36 is connected to pin 3 of chip U16, and the other end of resistor R36 is connected to a 3.3V isolated power supply; pin 4 of chip U16 is connected to pin 25 of chip U13; one end of resistor R35 is connected to pin 5 of chip U16, and the other end of resistor R35 is isolated and grounded; the positive terminal of capacitor C36 is connected to pin 6 of chip U16, and the other end of capacitor C36 is isolated and grounded; pin 6 of chip U16 is also connected to a 5V isolated power supply; the VCC power lines of USB6~USB9 are connected to pin 9 of the corresponding chip INA226AIDGSR, and GND is isolated and grounded; the D+ and D- signal lines are connected to the four sets of positive and negative data signal lines of pins 4~11 of chip U13, respectively. A 5V power supply is output from pin 1 of chip U16 to power the four USB downstream ports.

[0036] The circuit principle of this embodiment also includes an overcurrent indicator light. The 3.3V isolated power supply passes through the LED, the 2kΩ resistor R41, and pin 26 of the chip U13 in sequence.

[0037] (9) Card reader module Reference circuit schematic for card reader module Figure 10 This module is primarily used to read data from SD memory cards. It mainly consists of a USB-to-SD card bridge controller GL823K-HCY04 (U15), an SD card connector TF PUSH (CARD1), and decoupling and filtering capacitors (C34, C40, C41, C42). Capacitors C34, C40, and C42 are 100nF, and capacitor C41 is 10uF.

[0038] Pin 1 of chip U15 is grounded. The signals of pins 2-8 and pin 11 of chip U15 are connected to the corresponding pins of the SD card connector. The VSS signal of the SD card connector is grounded. One end of capacitor C34 is connected to pin 13 of chip U15, and the other end of capacitor C34 is grounded. Pin 13 of chip U15 is also connected to the 3.3V VDD power supply. Pin 10 of chip U15 is connected to the 5V power supply provided by the computer. One end of capacitor C40 is connected to pin 8 of chip U15, and the other end of capacitor C40 is grounded. After capacitors C41 and C42 are connected in parallel, one end is connected to pin 9 of chip U15, and the other end is grounded. Pin 9 of chip U15 is also connected to the 3.3V VDD power supply.

[0039] This embodiment also includes an LED circuit, where the 3.3V VDD power supply passes sequentially through a 1kΩ current-limiting resistor R39, a status indicator LED (LED2), and pin 12 of chip U15.

[0040] The workflow of the USB isolation extender in this embodiment is as follows: (1) Initialize external devices and create thread tasks: BLE, WiFi, USB (2) BLE thread: BLE (Bluetooth Low Energy) initialization; Check the BLE connection status. If not connected, enable Bluetooth broadcasting and continuously monitor the connection status; if connected, parse the JSON data and execute ① parameter configuration command → configure serial port parameter settings → configure WiFi parameters; ② serial port pass-through command → send serial port data. Check if the BLE connection is lost. If yes, return a Bluetooth broadcast data packet; otherwise, return to perform JSON data parsing.

[0041] (3) WiFi thread: WiFi initialization; Check if the WiFi connection is successful. If not, the serial port output connection fails. If yes, parse the JSON data and execute the following commands simultaneously: ① SWD download command → download the program to the device; ② JTAG download command → download the program to the device; ③ OTA upgrade command → software upgrade; ④ serial port pass-through command → send serial port data. Check if the WiFi connection is lost. If so, return to check if the WiFi connection is successful. If not, return to parse the JSON data.

[0042] (4) USB thread: USB initialization; Simultaneously execute the following commands while parsing JSON data: ① SWD download command → download program to device; ② JTAG download command → download program to device; ③ Serial port pass-through command → send serial port data. The serial port outputs log information, and then the JSON data is parsed.

[0043] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A USB isolation extender, characterized in that, include: ESP32-C3 main control unit, regulated power supply, computer, power isolation module, card reader module, host computer, slave computer, USB current limiting module, bidirectional current / power consumption monitor, debugging interface, USB-HUB control module, analog-to-digital converter; The USB-HUB control module includes a USB-HUB control chip and four USB downstream ports; The computer is used to provide power to the regulated power supply and power isolation module; The voltage regulator is used to provide regulated power to the card reader module and the host computer; The power isolation module is used to provide isolated power to the ESP32-C3 main control unit, lower-level machine, USB current limiting module, bidirectional current / power consumption monitor, debugging interface and USB-HUB control module; The USB current limiting module is used to provide current-limited power to the four USB downstream ports; The computer and the host computer are connected via USB. The host computer and the slave computer are isolated by capacitive coupling; The lower-level computer and the ESP32-C3 main control unit are connected via USB; The debugging interface connects the ESP32-C3 main control unit to external embedded devices; The lower-level machine and the USB-HUB control chip are connected via USB; The USB-HUB control chip and multiple USB downstream ports are connected via USB; The USB downstream port is connected to a bidirectional current / power consumption monitor via an analog-to-digital converter.

2. A USB isolation extender according to claim 1, characterized in that, The regulated power supply circuit includes: chip U10, capacitor C30, and capacitor C31; chip U10 is a ME6210A33M3G chip; pin 3 of chip U10 is connected to the 5V power supply provided by the computer; one end of capacitor C31 is connected to pin 3 of chip U10, and the other end of capacitor C31 is grounded; one end of capacitor C30 is connected to pin 2 of chip U10, and the other end of capacitor C30 is grounded; pin 2 of chip U10 outputs a 3.3V VDD power supply.

3. A USB isolation extender according to claim 2, characterized in that, The power isolation module circuit includes: chip U8, chip U9, low dropout regulator, Type-C interface USB1, capacitors C18, C19, C20, C24, C25, C26, C27, C28, diode D1, resistor R24, and resistor R27. Chip U8 is a B0505S-3WR2, chip U9 is a CH213K, and the low dropout regulator is an AMS1117-3.

3. Pin 1 of chip U8 is connected to the 5V power supply provided by the computer; pin 2 of chip U8 is grounded; pin 4 of chip U8 is isolated and grounded; pin 6 of chip U8 is connected to pin 3 of chip U9; pin 1 of chip U9 is isolated and grounded. One end of capacitor C18 is connected to pin 1 of chip U8, and the other end of capacitor C18 is grounded. One end of capacitor C19 is connected to pin 3 of chip U9, and the other end of capacitor C19 is isolated and grounded. The two ends of capacitor C20... Connect pins 1 and 2 of chip U9 respectively; pin 2 of chip U9 outputs a 5V isolated power supply; capacitors C26, C27, and C28 are connected in parallel, and their two ends are connected to pins 1 and 2 of the low dropout regulator respectively; pin 1 of the low dropout regulator is isolated and grounded; capacitors C24 and C25 are connected in parallel, one end is connected to pin 3 of the low dropout regulator, and the other end is isolated and grounded; pin 3 of the low dropout regulator is also connected to a 5V isolated power supply; pins 2 and 4 of the low dropout regulator output a 3.3V isolated power supply; the VBUS signal of USB1 is connected to the 5V power supply provided by the computer through diode D1, the CC2 signal of USB1 is grounded through resistor R24, the DP1 and DP2 signals of USB1 are shorted, the DN1 and DN2 signals of USB1 are shorted, the CC1 signal of USB1 is grounded through resistor R27, the two VBUS signals of USB1 are shorted, and the GND signal of USB1 is grounded.

4. A USB isolation extender according to claim 3, characterized in that, The ESP32-C3 main control unit circuit includes: chip U1, capacitors C1, C2, C3, C6, C7, resistors R1, R12, and R19, reset button SW1, and reset button SW2; chip U1 uses chip ESP32-C3-MINI-1-N4. Capacitors C1 and C2 are connected in parallel, with one end connected to pin 3 of chip U1 and the other end grounded. An isolation power supply is connected to pin 3 of chip U1, one end of resistor R1, one end of resistor R12, and one end of resistor R19. The other end of resistor R1 is connected to pin 8 of chip U1, the other end of resistor R12 is connected to pin 22 of chip U1, and the other end of resistor R19 is connected to pin 23 of chip U1. One end of capacitor C3 is connected to pin 8 of chip U1, and the other end of capacitor C3 is grounded. Pins 1, 2, 11, and 36-53 of chip U1 are isolated and grounded; pin 1 of reset button SW1 is isolated and grounded, and pin 4 of reset button SW1 is connected to pin 8 of chip U1; one end of capacitor C6 is connected to pin 8 of chip U1, and the other end of capacitor C6 is isolated and grounded; pin 1 of reset button SW2 is isolated and grounded, and pin 4 of reset button SW2 is connected to pin 23 of chip U1; one end of capacitor C7 is connected to pin 23 of chip U1, and the other end of capacitor C7 is isolated and grounded.

5. A USB isolation extender according to claim 4, characterized in that, The debugging interface circuit includes: SWD interface, JTAG interface, serial port interface, bidirectional TVS diodes D3, D5, D6, D7, D8, D9, D10, D11, and protection power supply circuit; the protection power supply circuit consists of PMOS transistor Q2, Schottky diode D4, and current limiting resistor R53. Connect the SWCLK signal line of the SWD interface to pin 20 of chip U1; connect the SWDIO signal line of the SWD interface to pin 21 of chip U1; connect the NTRST signal line of the JTAG interface to pin 18 of chip U1; connect the NRESET signal line of the JTAG interface to pin 19 of chip U1; connect the TCK signal line of the JTAG interface to pin 20 of chip U1; connect the TMS signal line of the JTAG interface to pin 21 of chip U1; connect the TDO signal line of the JTAG interface to pin 22 of chip U1; connect the TDI signal line of the JTAG interface to pin 23 of chip U1; connect the RX signal line of the serial port interface to pin 30 of chip U1; connect the TX signal line of the serial port interface to pin 31 of chip U1. The SWCLK and SWDIO signals of the SWD interface are isolated and grounded after passing through bidirectional TVS diodes D3 and D6, respectively. The TDI, TDO, NTRST, and NRESET signals of the JTAG interface are isolated and grounded after passing through bidirectional TVS diodes D8, D7, D6, and D9, respectively. The RX and TX signals of the serial port interface are isolated and grounded after passing through bidirectional TVS diodes D10 and D11, respectively. The GND signals of the SWD interface, serial port interface, and JTAG interface are isolated and grounded. The power signal is connected to a 3.3V protection power supply, which is generated by the protection power supply circuit. The source of PMOS transistor Q2 is connected to the 3.3V isolation power supply. One end of resistor R53 is connected to the gate of PMOS transistor Q2, and the other end of resistor R53 is isolated and grounded. One end of diode D4 is connected to the drain of PMOS transistor Q2, and the other end of diode D4 is isolated and grounded. The 3.3V protection power supply is output from the drain of PMOS transistor Q2.

6. A USB isolation extender according to claim 5, characterized in that, The host computer circuit includes: chip U6, capacitors C12, C16, C17, C21, C29, crystal oscillator X1, and resistor R26; chip U6 uses chip CH318T; crystal oscillator X1 uses CMOS active crystal oscillator YSO110TR. One end of capacitor C12 is grounded, and the other end of capacitor C12 is connected to pin 5 of chip U6; capacitors C16 and C17 are connected in parallel, and their two ends are connected to pins 15 and 16 of chip U6, respectively; pin 15 of chip U6 is grounded, and pin 16 of chip U6 is connected to VDD power supply; one end of capacitor C21 is connected to pin 14 of chip U6, and the other end of capacitor C21 is grounded; the Tri-state signal of crystal oscillator X1 is connected to pin 3 of chip U6, the GND signal of crystal oscillator X1 is grounded, the output signal of crystal oscillator X1 is connected to pin 4 of chip U6, and the VDD signal of crystal oscillator X1 is grounded; the two ends of capacitor C29 are connected to the Tri-state signal and VDD signal of crystal oscillator X1, respectively; one end of resistor R26 is connected to pin 3 of crystal oscillator X1, and the other end of resistor R26 is grounded.

7. A USB isolation extender according to claim 6, characterized in that, The lower-level circuit includes: chip U7, capacitors C10, C11, C13, C14, C15, C22, C32, resistors R25 and R28, and crystal oscillator X2; chip U7 uses chip CH318T; crystal oscillator X2 uses CMOS active crystal oscillator YSO110TR. One end of capacitor C10 is connected to pin 1 of chip U7, and the other end is connected to pin 1 of chip U6; one end of capacitor C15 is connected to pin 2 of chip U7, and the other end is connected to pin 2 of chip U6; one end of capacitor C13 is connected to pin 5 of chip U7, and the other end is grounded; capacitors C11 and C14 are connected in parallel, with their ends connected to pins 15 and 16 of chip U7 respectively; pin 15 of chip U7 is grounded, and pin 16 of chip U7 is connected to VDD power supply; one end of capacitor C22... One end of capacitor C22 is connected to pin 14 of chip U7, and the other end of capacitor C22 is isolated and grounded; one end of resistor R25 is connected to pin 13 of chip U7, and the other end of resistor R25 is isolated and grounded; pin 1 of crystal oscillator X2 is connected to pin 3 of U7, pin 2 of crystal oscillator X2 is isolated and grounded, pin 3 of crystal oscillator X2 is connected to pin 4 of U7, and pin 4 of crystal oscillator X2 is isolated and grounded; the two ends of capacitor C32 are connected to pin 1 and pin 4 of crystal oscillator X2 respectively; one end of resistor R28 is connected to pin 3 of crystal oscillator X2, and the other end of resistor R28 is isolated and grounded.

8. A USB isolation extender according to claim 7, characterized in that, The four bidirectional current / power consumption monitors correspond to the four USB downstream ports respectively. The circuit principle of the four bidirectional current / power consumption monitors is the same. One of the bidirectional current / power consumption monitor circuits includes: chip U2, resistor R2, resistor R3, resistor R6, resistor R8, resistor R9, and capacitor C4; chip U2 uses chip INA226AIDGSR. One end of resistor R3 is connected to pin 1 of chip U2, and the other end of resistor R3 is connected to the isolated power supply or isolated ground; one end of resistor R2 is connected to pin 2 of chip U2, and the other end of resistor R2 is connected to the isolated power supply or isolated ground; the two ends of resistor R6 are connected to pins 9 and 10 of chip U2 respectively; pin 9 of chip U2 is connected to the GND pin of the USB downstream port, and pin 10 of chip U2 is connected to the VCC pin of the USB downstream port; one end of resistor R8 is connected to pin 4 of chip U2, and one end of resistor R9 is connected to pin 5 of chip U2. The other ends of resistors R8 and R9 are connected to the isolated power supply; pin 4 of chip U2 is connected to pin 6 of chip U1, and pin 5 of chip U2 is connected to pin 16 of chip U1.

9. A USB isolation extender according to claim 8, characterized in that, The USB current limiting module and USB-HUB control module circuit includes: chip U13, chip U16, crystal oscillator X3, capacitors C35, C36, C37, C38, C39, C44, C45, C46, ​​and C47; resistors R35, R36, R42, R43, R45, and R47; and four downstream USB ports: USB6, USB7, USB8, and USB9. Chip U13 uses the CH334U chip, and chip U16 uses the CH217K chip. Pins 1, 12, and 28 of chip U13 are isolated and grounded; capacitors C44 and C45 are connected in parallel, with one end isolated and grounded, and the other end connected to pin 13 of chip U13; pin 13 of chip U13 is also connected to an isolated power supply; capacitors C37, C38, and C39 are connected in parallel, with one end isolated and grounded, and the other end connected to pins 20 and 21 of chip U13; pins 20 and 21 of chip U13 are also connected to an isolated power supply; pin 1 of crystal oscillator X3 is connected to pin 2 of chip U13. Pin 1 of crystal oscillator X3 is isolated to ground, and pin 2 and pin 4 of crystal oscillator X3 are connected to pin 3 of chip U13. The two ends of capacitor C46 are connected to pins 1 and 4 of crystal oscillator X3, and the two ends of capacitor C47 are connected to pins 2 and 3 of crystal oscillator X3. One end of resistors R42, R43, R45, and R47 is connected to pin 1 of chip U16, and the other end is connected to pin 10 of the corresponding chip INA226AIDGSR. Capacitor C35... One end of the capacitor C35 is connected to pin 1 of chip U16, and the other end of the capacitor C35 is grounded for isolation. Pin 2 of chip U16 is grounded for isolation. Pin 3 of chip U16 is connected to pin 26 of chip U13. One end of resistor R36 is connected to pin 3 of chip U16, and the other end of resistor R36 is connected to a 3.3V isolated power supply. Pin 4 of chip U16 is connected to pin 25 of chip U13. One end of resistor R35 is connected to pin 5 of chip U16, and the other end of resistor R35 is grounded for isolation. One end of capacitor C36 is connected to pin 6 of chip U16, and the other end of capacitor C36 is grounded for isolation. Pin 6 of chip U16 is also connected to a 5V isolated power supply. The VCC power lines of USB6~USB9 are connected to pin 9 of the corresponding chip INA226AIDGSR, and GND is grounded for isolation. The D+ and D- signal lines are connected to the four sets of positive and negative data signal lines of pins 4~11 of chip U13, respectively. A 5V power supply is output from pin 1 of chip U16.

10. A USB isolation extender according to claim 9, characterized in that, The card reader module circuit includes: chip U15, SD card connector, capacitors C34, C40, C41, and C42; chip U15 uses GL823K-HCY04, and the SD card connector uses TF PUSH; pin 1 of chip U15 is grounded, and the signals of pins 2-8 and pin 11 of chip U15 are connected to the corresponding pins of the SD card connector, respectively. The VSS signal of the SD card connector is grounded. One end of capacitor C34 is connected to pin 13 of chip U15, and the other end of capacitor C34 is grounded. Pin 13 of chip U15 is also connected to a 3.3V VDD power supply, and pin 10 of chip U15 is connected to a 5V power supply provided by the computer; one end of capacitor C40 is connected to pin 8 of chip U15, and the other end of capacitor C40 is grounded; capacitors C41 and C42 are connected in parallel, with one end connected to pin 9 of chip U15 and the other end grounded; pin 9 of chip U15 is also connected to a 3.3V VDD power supply.

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