Display device

Abstract

A display device, the display device includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a control module, a first pull-down module, a capacitor, a signal end, an output end and a first low level end, the gate of the first thin film transistor is connected with one end of the capacitor, the control module and the drain of the third thin film transistor, the source of the first thin film transistor is connected with the other end of the capacitor, the drain of the second thin film transistor and the output end, the gate of the second thin film transistor is connected with the first pull-down module and the gate of the third thin film transistor, the output end is connected with a pixel electrode, the control module controls the switch of the first thin film transistor, the signal end transmits a first signal to the drain of the first thin film transistor, the first signal includes a high potential signal and a low potential signal, and the first pull-down module reduces the voltage of the low potential signal to the voltage of the first low level end when the output end transmits the low potential signal, thereby reducing the charging time difference of the display device.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] Currently, in the display technology field, manufacturers often use the DRD architecture in monitors to reduce data cables and simplify the monitor's structure. However, in existing technologies, monitors using the DRD architecture exhibit significant variations in panel charging time, which can easily lead to issues such as screen tearing, flickering, and poor image quality. Utility Model Content

[0003] The purpose of this invention is to provide a display device that improves the problem of large differences in charging time among display devices.

[0004] To achieve the objectives of this utility model, the following technical solution is provided:

[0005] In a first aspect, this utility model provides a display device, the display device comprising a first thin-film transistor (TFT), a second TFT, a third TFT, a control module, a first pull-down module, a capacitor, a signal terminal, an output terminal, and a first low-level terminal. The gate of the first TFT is connected to one end of the capacitor, the control module, and the drain of the third TFT. The source of the first TFT is connected to the other end of the capacitor, the drain of the second TFT, and the output terminal. The gate of the second TFT is connected to the first pull-down module and the gate of the third TFT. The output terminal is used to connect to a pixel electrode. The first low-level terminal is used to receive a first low-level signal. The control module is used to control the on / off state of the first TFT. The signal terminal is used to transmit a first signal to the drain of the first TFT, the first signal including a high-potential signal and a low-potential signal. The first pull-down module is used to reduce the voltage of the low-potential signal to the voltage of the first low-level terminal when the low-potential signal is transmitted at the output terminal.

[0006] The control module controls the on and off of the first thin-film transistor, and the signal terminal transmits a first signal to the drain of the first thin-film transistor. The first signal includes a high-potential signal and a low-potential signal. The first pull-down module is used to reduce the voltage of the low-potential signal to the voltage of the first low-level terminal when the low-potential signal is transmitted at the output terminal. This reduces the voltage of the low-potential signal, increases the voltage difference between the high-potential signal and the low-potential signal, speeds up the fall time of the first signal, and reduces the difference in the charging time of the display device.

[0007] In one embodiment, the control module includes a fourth thin-film transistor, the source of which is connected to the gate of the first thin-film transistor, one end of the capacitor, and the drain of the third thin-film transistor, and the drain of the fourth thin-film transistor is connected to the gate of the fourth thin-film transistor.

[0008] By configuring the control module to include a fourth thin-film transistor (TFT), the source of which is connected to the gate of the first TFT, one end of a capacitor, and the drain of the third TFT, and the drain of the fourth TFT is connected to its gate, the fourth TFT can control the conduction and disconnection of the first TFT. When a low-level signal is applied to the gate of the fourth TFT, the fourth TFT is disconnected; when a high-level signal is applied to the gate of the fourth TFT, the fourth TFT is turned on. A high-level signal is then applied to the first TFT to turn it on, thus improving the accuracy and efficiency of the control over the first TFT.

[0009] In one embodiment, the display device further includes a plurality of driving modules, which are arranged in one or more columns along the length or width of the display device. The gate and drain of the fourth thin-film transistor are both connected to at least one of the driving modules, and the first pull-down module is connected to at least one of the driving modules.

[0010] The display device also includes multiple driving modules, which are arranged in one or more columns along the length or width of the display device. The gate and drain of the fourth thin-film transistor are both connected to at least one driving module, which improves the efficiency and accuracy of the driving module in controlling the fourth thin-film transistor. The first pull-down module is connected to at least one driving module, which improves the efficiency and accuracy of the driving module in controlling the first pull-down module.

[0011] In one embodiment, the display device further includes a fifth thin-film transistor, the drain of which is connected to the source of the second thin-film transistor, the first low-level terminal, and the source of the third thin-film transistor.

[0012] The display device also includes a fifth thin-film transistor. The drain of the fifth thin-film transistor is connected to the source of the second thin-film transistor, the first low-level terminal, and the source of the third thin-film transistor. This makes the drain of the fifth thin-film transistor, the source of the second thin-film transistor, and the source of the third thin-film transistor at the same voltage as the first low-level terminal, thereby pulling down the voltage of the drain of the fifth thin-film transistor, the source of the second thin-film transistor, and the source of the third thin-film transistor.

[0013] In one embodiment, the display device further includes a second low-level terminal, which is connected to the source of the fifth thin-film transistor, and is used to receive a second low-level signal.

[0014] The display device also includes a second low-level terminal, which is connected to the source of the fifth thin-film transistor. The second low-level terminal is used to receive a second low-level signal, which pulls down the voltage of the source of the fifth thin-film transistor.

[0015] In one embodiment, the display device further includes a second pull-down module, which is connected to the gate of the fifth thin-film transistor and to at least one of the driving modules. The second pull-down module is used to reduce the voltage of the first low-level terminal to the voltage of the second low-level terminal when the fifth thin-film transistor is turned on.

[0016] The display device also includes a second pull-down module, which is connected to the gate of the fifth thin-film transistor and to at least one driving module. The second pull-down module is used to reduce the voltage of the first low-level terminal to the voltage of the second low-level terminal when the fifth thin-film transistor is turned on, and to reduce the voltage of the output terminal to the voltage of the second low-level terminal when the second thin-film transistor is turned on, thereby increasing the voltage difference between the gate high voltage and the gate low voltage.

[0017] In one embodiment, the voltage of the first low-level terminal is A volts and the voltage of the second low-level terminal is B volts, satisfying: -7≤A≤-5, -14≤B≤-10.

[0018] By setting the voltage of the first low-level terminal to be greater than or equal to -7 volts and less than or equal to -5 volts, and the voltage of the second low-level terminal to be greater than or equal to -14 volts and less than or equal to -10 volts, the voltage of the second low-level terminal is lower than the voltage of the first low-level terminal, thereby reducing the gate low voltage.

[0019] In one embodiment, the duty cycle of the high-potential signal duration of the first signal is C, satisfying: 40% ≤ C ≤ 50%.

[0020] By setting the duty cycle of the high-potential signal duration of the first signal to between 40% and 50%, the ratio of the high-potential signal duration to the low-potential signal duration can be controlled to be appropriate.

[0021] In one embodiment, the display device further includes a first resistor, one end of which is connected to the source of the first thin-film transistor, the other end of the capacitor, and the drain of the second thin-film transistor, and the other end of the first resistor is connected to the output terminal.

[0022] It is understood that one end of the first resistor is connected to the source of the first thin-film transistor, the other end of the capacitor, and the drain of the second thin-film transistor, while the other end of the first resistor is connected to the output terminal, thereby limiting the magnitude of the current transmitted to the output terminal and preventing excessive current surges.

[0023] In one embodiment, the display device further includes a second resistor, one end of which is connected to the drain of the third thin-film transistor, and the other end of which is connected to the control module, one end of the capacitor, and the gate of the first thin-film transistor.

[0024] It is understandable that one end of the second resistor is connected to the drain of the third thin-film transistor, and the other end of the second resistor is connected to the control module, one end of the capacitor, and the gate of the first thin-film transistor to prevent excessive current surges. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is an application scenario diagram of a display device;

[0027] Figure 2 This is a schematic diagram of the structure of a display device;

[0028] Figure 3 This is a schematic diagram of the circuit structure of a display device;

[0029] Figure 4 This is a potential diagram of a display device according to one embodiment.

[0030] Explanation of reference numerals in the attached figures:

[0031] 10-Display device, 101-User, 102-Electronic device, 103-Server, 11-First thin-film transistor, 12-Second thin-film transistor, 13-Third thin-film transistor, 14-Control module, 15-First pull-down module, 16-Capacitor, 17-Signal terminal, 18-Output terminal, 19-First low-level terminal, 20-Fourth thin-film transistor, 21-Fifth thin-film transistor, 22-Second low-level terminal, 23-Second pull-down module, 24-First node, 25-First resistor, 26-Second resistor, 30-Housing, V1-First low-potential signal, V2-First high-potential signal, V3-First low-level signal, V4-Second low-level signal. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present application, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the examples described are only a part of the examples of the present application, and not all of them. Based on the examples in the present application, all other examples obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0033] The terms “1” and “2”, etc., in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0034] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one example of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0035] Please see Figure 1 , Figure 1 An application scenario diagram of a display device provided in this application. For example... Figure 1 As shown in the diagram, this application scenario includes user 101, electronic device 102, and server 103. It should be noted that electronic device 102 includes a display, which can display video data or image data. Furthermore, Figure 1 The number of devices, the form of each device, and the number of users in the system shown are for illustrative purposes only and do not constitute a limitation of this application. A user 101 can use multiple electronic devices 102, and a server 103 can be connected to multiple electronic devices 102. The server 103 transmits data to the electronic devices 102, and the electronic devices 102 can display the data on the display.

[0036] User 101 is the user who actually operates electronic device 102 to control it to perform corresponding operations. Electronic device 102 can be... Figure 1The laptop shown can also be a personal computer (PC), all-in-one computer, handheld computer, tablet computer, desktop computer, smartphone, smart TV playback terminal, and portable device. PC-based electronic devices, such as all-in-one computers, can have operating systems including, but not limited to, Linux, Unix, and Windows series systems (such as Windows XP and Windows 7). Mobile electronic devices, such as smartphones, can have operating systems including, but not limited to, Android, iOS (Apple's operating system), and Windows.

[0037] Please refer to Figure 2 This application provides a schematic diagram of a display device, including a housing 30 and a display device 10 as described in this embodiment of the invention, wherein the display device 10 is installed within the housing 30. The display device 10 may be an e-reader, e-book, monitor, or mobile phone, etc., and this application does not impose any limitations thereon.

[0038] Optionally, the display device 10 is a liquid crystal panel (TFT-LCD panel). The display device 10 includes an upper substrate, liquid crystal, and an array substrate. In this embodiment, the driving circuits of the display device 10 are all disposed on the array substrate. The driving circuits change the pixel voltage between the upper substrate and the array substrate by changing the output voltage to control the alignment direction or physical state of the liquid crystal. Light output from an external light source or the backlight of the display device 10 is polarized by the polarization function of the liquid crystal and then projected onto the panel to generate an image. Optionally, there are multiple pixel electrodes arranged in an array. Optionally, the array substrate includes a substrate, a driving circuit layer, a passivation layer, and a pixel electrode layer stacked sequentially. The driving circuit of the display device 10 is disposed within the driving circuit layer, and the pixel electrodes are disposed within the pixel electrode layer.

[0039] The display device provided by this utility model, by employing a housing 30 and a display device 10 in the embodiment of this utility model, reduces the voltage of the low-potential signal to the voltage of the first low-level terminal when transmitting a low-potential signal at the output terminal of the display device 10. This reduces the voltage of the low-potential signal, increases the voltage difference between the high-potential signal and the low-potential signal, accelerates the fall time of the first signal, reduces the charging difference between positive and negative polarities, reduces the difference in charging time of the display device, improves the uniformity of the display device, improves the display effect, and increases the yield.

[0040] For example, in an LCD panel, T is the time constant, R is the resistance, and C is the capacitance, satisfying: T = RC. When RC is a constant value, the time T for charging (discharging) to the next voltage level is also a constant value. The panel loses power the fastest in the first RC time. Therefore, in the same time, the greater the voltage difference, the faster the voltage discharge is from 0 to RC. The discharge starts to slow down from RC to 2RC. Therefore, when the charging time is controlled to be near or within a time T = RC, the difference in charging time of the entire panel will be minimized.

[0041] Please see Figure 3 , Figure 3 This is a schematic diagram of the circuit structure of a display device provided in this application. Figure 3 As shown in the schematic diagram, the structure includes a display device 10, a first thin-film transistor 11, a second thin-film transistor 12, a third thin-film transistor 13, a control module 14, a first pull-down module 15, a capacitor 16, a signal terminal 17, an output terminal 18, a first low-level terminal 19, a fourth thin-film transistor 20, a fifth thin-film transistor 21, a second low-level terminal 22, a second pull-down module 23, and a first node 24. Specifically, the gate of the first thin-film transistor 11 is connected to one end of the capacitor 16, the control module 14, and the drain of the third thin-film transistor 13; the source of the first thin-film transistor 11 is connected to the other end of the capacitor, the drain of the second thin-film transistor 12, and the output terminal; the drain of the first thin-film transistor 11 is connected to the signal terminal 17; the gate of the second thin-film transistor 12 is connected to the first pull-down module 15 and the gate of the third thin-film transistor 13; and the source of the fourth thin-film transistor 20 is connected to the gate of the first thin-film transistor 11, one end of the capacitor 16, and the third thin-film transistor 13. The drains of the second thin-film transistor 21 and the third thin-film transistor 12 are all connected. The drain of the fifth thin-film transistor 21 is connected to the source of the second thin-film transistor 12, the first low-level terminal 19, and the source of the third thin-film transistor 13. The second low-level terminal 22 is connected to the source of the fifth thin-film transistor 21 and is used to receive a second low-level signal. The second pull-down module 23 is connected to the gate of the fifth thin-film transistor 21. The output terminal 18 is used to connect to the pixel electrode, and the first low-level terminal 19 is used to receive a first low-level signal. For example, the first low-level signal is the VSS signal, and the second low-level signal is the VSST signal.

[0042] For example, a clock signal is transmitted to the drain of the first thin-film transistor 11 via the signal terminal 17. The clock signal includes a high-potential signal and a low-potential signal.

[0043] For example, when both the drain and gate of the fourth thin-film transistor 20 are connected to a high-potential signal, the fourth thin-film transistor 20 is turned on, transmits a high-potential signal to the gate of the first thin-film transistor 11, and charges the capacitor 16, causing the first thin-film transistor 11 to be in a conducting state; when both the drain and gate of the fourth thin-film transistor 20 are connected to a low-potential signal, the fourth thin-film transistor 20 is turned off.

[0044] For example, when the first pull-down module 15 receives a high-potential signal, the first pull-down module 15 transmits a high-potential signal to the gate of the second thin-film transistor 12, and the second thin-film transistor 12 is turned on; when the first pull-down module 15 receives a low-potential signal, the first pull-down module 15 transmits a low-potential signal to the gate of the second thin-film transistor 12, and the second thin-film transistor 12 is turned off.

[0045] For example, when the second pull-down module 23 receives a high-potential signal, the second pull-down module 23 transmits a high-potential signal to the gate of the fifth thin-film transistor 21, and the fifth thin-film transistor 21 is turned on; when the second pull-down module 23 receives a low-potential signal, the second pull-down module 23 transmits a low-potential signal to the gate of the fifth thin-film transistor 21, and the fifth thin-film transistor 21 is turned off.

[0046] For example, when the first pull-down module 15 receives a high-potential signal, the first pull-down module 15 transmits a high-potential signal to the gate of the third thin-film transistor 13, and the third thin-film transistor 13 is turned on; when the first pull-down module 15 receives a low-potential signal, the first pull-down module 15 transmits a low-potential signal to the gate of the third thin-film transistor 13, and the third thin-film transistor 13 is turned off.

[0047] In one implementation, please refer to Figure 3 The control module includes a fourth thin-film transistor. The source of the fourth thin-film transistor is connected to the gate of the first thin-film transistor, one end of the capacitor, and the drain of the third thin-film transistor. The drain of the fourth thin-film transistor is connected to the gate of the fourth thin-film transistor.

[0048] For example, when a high-potential signal is applied to the source of the fourth thin-film transistor 20, the fourth thin-film transistor 20 transmits a high-potential signal to the gate of the first thin-film transistor 11, and the first thin-film transistor 11 is turned on.

[0049] By configuring the control module to include a fourth thin-film transistor 20, the source of the fourth thin-film transistor 20 is connected to the gate of the first thin-film transistor 11, one end of the capacitor 16, and the drain of the third thin-film transistor 13. The drain of the fourth thin-film transistor 20 is connected to its gate, enabling the fourth thin-film transistor 20 to control the conduction and disconnection of the first thin-film transistor 11. When a low-level signal is applied to the gate of the fourth thin-film transistor 20, the fourth thin-film transistor 20 is disconnected; when a high-level signal is applied to the gate of the fourth thin-film transistor 20, the fourth thin-film transistor 20 is turned on, thus inputting a high level to the first thin-film transistor 11 to turn it on, thereby improving the accuracy and efficiency of controlling the first thin-film transistor 11.

[0050] In one implementation, please refer to Figure 3 The display device 10 also includes multiple driving modules, which are arranged in one or more columns along the length or width of the display device 10. The gate and drain of the fourth thin film transistor 20 are both connected to at least one driving module, and the first pull-down module 15 is connected to at least one driving module.

[0051] For example, the gate and drain of the fourth thin-film transistor 20 are both connected to the (N-4)th driving module.

[0052] For example, the first drop-down module 15 is connected to the N+4th driver module.

[0053] The display device 10 also includes multiple driving modules, which are arranged in one or more columns along the length or width of the display device 10. The gate and drain of the fourth thin-film transistor 20 are both connected to at least one driving module, which improves the efficiency and accuracy of the driving module in controlling the fourth thin-film transistor 20. The first pull-down module 15 is connected to at least one driving module, which improves the efficiency and accuracy of the driving module in controlling the first pull-down module 15.

[0054] In one implementation, please refer to Figure 3 The display device 10 also includes a fifth thin-film transistor 21, the drain of which is connected to the source of the second thin-film transistor 12, the first low-level terminal 19, and the source of the third thin-film transistor 13.

[0055] The display device 10 also includes a fifth thin-film transistor 21. The drain of the fifth thin-film transistor 21 is connected to the source of the second thin-film transistor 12, the first low-level terminal 19, and the source of the third thin-film transistor 13. This makes the drain of the fifth thin-film transistor 21, the source of the second thin-film transistor 12, and the source of the third thin-film transistor 13 at the same voltage as the first low-level terminal 19, thereby lowering the voltage of the drain of the fifth thin-film transistor 21, the source of the second thin-film transistor 12, and the source of the third thin-film transistor 13.

[0056] In one implementation, please refer to Figure 3 The display device 10 also includes a second low-level terminal 22, which is connected to the source of the fifth thin-film transistor 21 and is used to receive a second low-level signal.

[0057] The display device 10 also includes a second low-level terminal 22, which is connected to the source of the fifth thin-film transistor 21. The second low-level terminal 22 is used to receive a second low-level signal, which pulls down the voltage of the source of the fifth thin-film transistor 21.

[0058] In one implementation, please refer to Figure 3 The display device 10 further includes a second pull-down module 23, which is connected to the gate of the fifth thin-film transistor 21 and is connected to at least one driving module. The second pull-down module 23 is used to reduce the voltage of the first low-level terminal 19 to the voltage of the second low-level terminal 22 when the fifth thin-film transistor 21 is turned on.

[0059] For example, the second drop-down module 23 is connected to the N+3rd driver module.

[0060] For example, when the second pull-down module 23 receives a high-potential signal, it transmits a high-potential signal to the gate of the fifth thin-film transistor 21, causing the fifth thin-film transistor 21 to conduct; when the second pull-down module 23 receives a low-potential signal, it transmits a low-potential signal to the gate of the fifth thin-film transistor 21, causing the fifth thin-film transistor 21 to turn off.

[0061] The display device 10 also includes a second pull-down module 23, which is connected to the gate of the fifth thin-film transistor 21 and to at least one driving module. The second pull-down module 23 is used to reduce the voltage of the first low-level terminal 19 to the voltage of the second low-level terminal 22 when the fifth thin-film transistor 21 is turned on, and to reduce the voltage of the output terminal 18 to the voltage of the second low-level terminal 22 when the second thin-film transistor 12 is turned on, thereby increasing the voltage difference between the gate high voltage and the gate low voltage.

[0062] In one embodiment, the voltage of the first low-level terminal 19 is A volts and the voltage of the second low-level terminal 22 is B volts, satisfying: -7≤A≤-5, -14≤B≤-10.

[0063] By setting the voltage of the first low-level terminal 19 to be greater than or equal to -7 volts and less than or equal to -5 volts, and the voltage of the second low-level terminal 22 to be greater than or equal to -14 volts and less than or equal to -10 volts, the voltage of the second low-level terminal 22 is lower than the voltage of the first low-level terminal 19, thereby reducing the gate low voltage.

[0064] In one embodiment, the duty cycle of the high-potential signal duration of the first signal is C, which satisfies: 40% ≤ C ≤ 50%.

[0065] Optionally, the first signal includes a clock signal, which includes a high-level signal and a low-level signal.

[0066] By setting the duty cycle of the high-potential signal duration of the first signal to between 40% and 50%, the ratio of the high-potential signal duration to the low-potential signal duration can be controlled to be appropriate.

[0067] In one embodiment, the display device 10 further includes a first resistor 25, one end of which is connected to the source of the first thin film transistor 11, the other end of the capacitor 16, and the drain of the second thin film transistor 12, and the other end of the first resistor 25 is connected to the output terminal 18.

[0068] It is understood that one end of the first resistor 25 is connected to the source of the first thin-film transistor 11, the other end of the capacitor 16, and the drain of the second thin-film transistor 12, and the other end of the first resistor 25 is connected to the output terminal 18, limiting the magnitude of the current transmitted to the output terminal 18 and preventing excessive current surges.

[0069] In one embodiment, the display device 10 further includes a second resistor 26, one end of which is connected to the drain of the third thin-film transistor 13, and the other end of which is connected to the control module 14, one end of the capacitor 16, and the gate of the first thin-film transistor 11.

[0070] It is understood that one end of the second resistor 26 is connected to the drain of the third thin-film transistor 13, and the other end of the second resistor 26 is connected to the control module, one end of the capacitor 16, and the gate of the first thin-film transistor 11 to prevent excessive current surges.

[0071] Please refer to Figure 4 , Figure 4This is a potential diagram of a display device according to an embodiment of this application. As shown, at time t1, the gate of the fourth thin-film transistor is connected to a first low-potential signal V1. At this time, the fourth thin-film transistor is off, the capacitor discharges, and the first thin-film transistor is turned on. At this time, the signal terminal is connected to a first high-potential signal V2, and the output terminal outputs the first high-potential signal V2. At time t2, the gate of the fourth thin-film transistor is connected to the first low-potential signal V1. At this time, the fourth thin-film transistor is off, the capacitor discharges, and the first thin-film transistor is turned on. At this time, the signal terminal is connected to the first high-potential signal V2, and the output terminal outputs the first high-potential signal V2. At time t3, the gate of the fourth thin-film transistor is connected to a first low-level signal V3. At this time, the fourth thin-film transistor is off, the first thin-film transistor is off, the first pull-down module outputs the first high-potential signal V2, and the second thin-film transistor is turned on. The voltage at the output terminal is the same as the voltage at the first low-level terminal. The second pull-down module outputs the first high-potential signal V2, and the fifth thin-film transistor is turned on. The voltage at the first low-level terminal is the same as the voltage at the second low-level terminal. Since the voltage at the second low-level terminal is the second low-level signal V4, the output terminal outputs the second low-level signal V4. For example, V1 is the gate low voltage, V2 is the gate high voltage, V3 is the VSS voltage, and V4 is the VSST voltage.

[0072] In the description of the embodiments of this utility model, it should be noted that the orientation or positional relationship of the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and other indicators are based on the orientation or positional relationship of the drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0073] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Those skilled in the art can understand that implementing all or part of the above-described embodiments and making equivalent changes in accordance with the claims of the present utility model are still within the scope of the present utility model.

Claims

1. A display device, characterized in that, The display device includes a first thin-film transistor (TFT), a second TFT, a third TFT, a control module, a first pull-down module, a capacitor, a signal terminal, an output terminal, and a first low-level terminal. The gate of the first TFT is connected to one end of the capacitor, the control module, and the drain of the third TFT. The source of the first TFT is connected to the other end of the capacitor, the drain of the second TFT, and the output terminal. The gate of the second TFT is connected to the gate of the first pull-down module and the gate of the third TFT. The output terminal is used to connect to a pixel electrode. The first low-level terminal is used to receive a first low-level signal. The control module is used to control the on and off states of the first thin-film transistor; The signal terminal is used to transmit a first signal to the drain of the first thin-film transistor, the first signal including a high-potential signal and a low-potential signal; The first pull-down module is used to reduce the voltage of the low-potential signal to the voltage of the first low-level terminal when the low-potential signal is transmitted at the output terminal.

2. The display device according to claim 1, characterized in that, The control module includes a fourth thin-film transistor, the source of which is connected to the gate of the first thin-film transistor, one end of the capacitor, and the drain of the third thin-film transistor, and the drain of the fourth thin-film transistor is connected to the gate of the fourth thin-film transistor.

3. The display device according to claim 2, characterized in that, The display device further includes multiple driving modules, which are arranged in one or more columns along the length or width of the display device. The gate and drain of the fourth thin-film transistor are both connected to at least one of the driving modules, and the first pull-down module is connected to at least one of the driving modules.

4. The display device according to claim 1, characterized in that, The display device further includes a fifth thin-film transistor, the drain of which is connected to the source of the second thin-film transistor, the first low-level terminal, and the source of the third thin-film transistor.

5. The display device according to claim 4, characterized in that, The display device further includes a second low-level terminal, which is connected to the source of the fifth thin-film transistor and is used to receive a second low-level signal.

6. The display device according to claim 5, characterized in that, The display device further includes a second pull-down module, which is connected to the gate of the fifth thin-film transistor and to at least one of the driving modules. The second pull-down module is used to reduce the voltage of the first low-level terminal to the voltage of the second low-level terminal when the fifth thin-film transistor is turned on.

7. The display device according to claim 6, characterized in that, The voltage at the first low-level terminal is A volts, and the voltage at the second low-level terminal is B volts, satisfying: -7≤A≤-5, -14≤B≤-10.

8. The display device according to claim 1, characterized in that, The duty cycle of the high-potential signal duration of the first signal is C, which satisfies: 40% ≤ C ≤ 50%.

9. The display device according to claim 1, characterized in that, The display device further includes a first resistor, one end of which is connected to the source of the first thin-film transistor, the other end of the capacitor, and the drain of the second thin-film transistor, and the other end of the first resistor is connected to the output terminal.

10. The display device according to claim 1, characterized in that, The display device further includes a second resistor, one end of which is connected to the drain of the third thin-film transistor, and the other end of which is connected to the control module, one end of the capacitor, and the gate of the first thin-film transistor.

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