Static random access memory and electronic device

Abstract

The utility model provides a kind of static random access memory, comprising: storage circuit, address gate, electrically connected in storage circuit;Sense amplifier, when memory is in read process, sense amplifier is electrically connected in address gate;Write amplifier, when memory is in write process, write amplifier is electrically connected in address gate, and the input end of write amplifier is electrically connected with sense amplifier by two-stage detection switch;Output flip-flop, input end is electrically connected in sense amplifier, and the output end of output flip-flop is electrically connected with the input end of write amplifier by one-stage detection switch;Logic circuit, electrically connected in the output end of output flip-flop and the input end of write amplifier;And input-output circuit, electrically connected in logic circuit and external device;Wherein, when memory read-write error, one-stage detection switch and two-stage detection switch are closed in turn.This application can quickly locate error area when read-write error.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a static random access memory and electronic device. Background Technology

[0002] Static Random Access Memory (SRAM) is a type of random access memory that retains its stored data as long as it is powered on. When reading or writing data, the signal passes through multiple circuit regions. When a read / write failure occurs, it is difficult to directly pinpoint the defective area and the number of defects. Therefore, when analyzing the cause of the failure, it is necessary to first determine the location of the fault to provide direction for subsequent chip failure analysis.

[0003] When a memory device encounters a read / write error, the chip cannot perform a self-test to analyze the underlying cause. Instead, it relies on disassembling the chip structure and measuring the electrical characteristics of the integrated circuit. Since a chip contains hundreds of millions of transistors, blindly performing fault analysis is not only extremely difficult, but disassembling the chip structure may also incorrectly remove the actual faulty area, leading to inadequate chip failure analysis and reduced accuracy. Utility Model Content

[0004] The purpose of this invention is to provide a static random access memory and electronic device that can locate the error area when a semiconductor device reads or writes an error, and then use physical or chemical means to find the cause in a targeted manner.

[0005] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution: This utility model provides a static random access memory, comprising: Storage circuit; An address selector is electrically connected to the storage circuit; A read amplifier is electrically connected to the address selector when the memory is in a read process. A write amplifier is electrically connected to the address selector when the memory is in the write process, and the input terminal of the write amplifier is electrically connected to the read amplifier through a two-stage detection switch. An output trigger is electrically connected to the input terminal of the sense amplifier, and the output terminal of the output trigger is electrically connected to the input terminal of the write amplifier through a first-stage detection switch. A logic circuit, electrically connected to the output terminal of the output flip-flop and the input terminal of the write amplifier; and Input / output circuitry, electrically connected to the logic circuitry and external devices; When a read / write error occurs in the memory, the first-level detection switch and the second-level detection switch are closed in sequence to locate the fault location of the memory based on the output signal of the input / output circuit.

[0006] In one embodiment of this utility model, at most one of the primary detection switch and the secondary detection switch is closed at the same time.

[0007] In one embodiment of this utility model, the input / output circuit includes an input terminal and an output terminal. The output terminal and the input terminal are electrically connected to the logic circuit and the external device. When the input value of the input terminal and the output value of the output terminal are equal, there is no fault in the activated signal detection path in the memory. When the input value of the input terminal and the output value of the output terminal are not equal, there is a fault area in the activated signal detection path in the memory.

[0008] In one embodiment of the present invention, the signal detection path through which the memory can be activated includes a first detection circuit and a second detection circuit. The first detection circuit includes the input terminal, the logic circuit, the first-level detection switch, and the output terminal. The second detection circuit includes the input terminal, the logic circuit, the write amplifier, the second-level detection switch, the read amplifier, the output trigger, and the output terminal.

[0009] In one embodiment of the present invention, the memory includes peripheral circuitry, the storage circuitry and the logic circuitry are disposed on the same chip substrate, wherein the output trigger, the read amplifier, the write amplifier, the address selector, the first-level detection switch and the second-level detection switch are disposed in the peripheral circuitry.

[0010] In one embodiment of this utility model, the peripheral circuit includes a process switching switch. The first terminal of the process switching switch is electrically connected to the address selector, the second terminal of the process switching switch is electrically connected to the read amplifier, and the third terminal of the process switching switch is electrically connected to the write amplifier. When the memory is working, the first terminal is electrically connected to the second terminal, or the first terminal is electrically connected to the third terminal.

[0011] In one embodiment of this utility model, the peripheral circuit includes: A first process switching switch, one end of which is electrically connected to the address selector, and the other end of which is electrically connected to the sense amplifier; and The second process switching switch is electrically connected at one end to the address selector and at the other end to the write amplifier. When the memory is in operation, either the first process switching switch or the second process switching switch is closed.

[0012] In one embodiment of this utility model, the peripheral circuit includes a pre-charge module, which is electrically connected to the storage circuit and the address selector.

[0013] In one embodiment of this utility model, the primary detection switch and the secondary detection switch each include at least one MOS transistor.

[0014] This invention provides an electronic device, including any of the static random access memories described above.

[0015] As described above, this utility model provides a static random access memory and electronic device that can perform fault self-checks and determine the specific area where the fault occurs when read / write errors occur. This not only helps to identify the fault type or location in a timely manner, but also facilitates accurate and efficient chip failure analysis in the future.

[0016] Of course, any product implementing this utility model does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a storage device in one embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the structure of the storage device in another embodiment of the present invention.

[0020] In the diagram: 100, Input / output circuit; 110, Input terminal; 120, Output terminal; 200, Logic circuit; 300, Peripheral circuit; 310, Output trigger; 320, Read amplifier; 330, Write amplifier; 340, Address selector; 350, Precharge module; 360, First-level detection switch; 370, Second-level detection switch; 380, Process switching switch; 381, First process switching switch; 382, ​​Second process switching switch; 400, Storage circuit. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0022] Please see Figure 1 As shown, this utility model discloses a memory, which can be a Static Random Access Memory (SRAM). In this utility model, the memory includes an input / output circuit 100, a logic circuit 200, a peripheral circuit 300, and a storage circuit 400. The logic circuit 200, the peripheral circuit 300, and the storage circuit 400 are disposed on the same chip substrate. Furthermore, the input / output circuit 100 is electrically connected to the logic circuit 200, the logic circuit 200 is electrically connected to the peripheral circuit 300, and the peripheral circuit 300 is electrically connected to the storage circuit 400. The substrate is, for example, a silicon substrate forming the semiconductor structure of the memory. The substrate may include a substrate and a silicon layer disposed on top of the substrate. The substrate is, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), or lithium aluminate (LiAlO2), and the silicon layer is formed on top of the substrate. The memory is a semiconductor device disposed on the substrate, and the interconnection of internal devices within the memory can be achieved through a metal interconnect structure. The input / output circuit 100, logic circuit 200, peripheral circuit 300, and storage circuit 400 are disposed on the same chip substrate. The input terminals 110 and 120 of the input / output circuit 100 can be formed using metal layers and / or contact plugs (CTs). In this embodiment, the input / output circuit 100 is electrically connected to an external device to complete data transmission to the memory. The external device can read and write data from the memory through the input / output circuit 100. The external device can be an external host, a test machine, or other device responsible for providing or receiving signals. In this embodiment, the logic circuit 200 is used to implement various preset functions of the memory. This invention does not limit the structure of the logic circuit 200. For example, the logic circuit 200 may include an inverter or data buffer for data transmission, as well as a multiplexer, etc. In this embodiment, the peripheral circuit 300 is a non-standard logic circuit 200. In this embodiment, the storage circuit 400 can be an integration of multiple storage cells. The storage cell can be a 6T SRAM. On the chip, the storage circuit 400 and the peripheral circuit 300 are located in different areas, and the peripheral circuit 300 can be electrically connected to the storage circuit 400 and the logic circuit 200 through a metal interconnect structure.

[0023] Please see Figure 1 As shown, in one embodiment of this utility model, the peripheral circuit 300 includes an address selector 340, a read amplifier 320, a write amplifier 330, an output trigger 310, a first-level detection switch 360, and a second-level detection switch 370. When the memory is in a read process, the read amplifier 320 is electrically connected to the address selector 340. When the memory is in a write process, the write amplifier 330 is electrically connected to the address selector 340, and its input terminal 110 is electrically connected to the read amplifier 320 via the second-level detection switch 370. The input terminal 110 of the output trigger 310 is electrically connected to the read amplifier 320, and its output terminal 120 is electrically connected to the input terminal 110 of the write amplifier 330 via the first-level detection switch 360. In this embodiment, the logic circuit 200 is electrically connected to the output terminal 120 of the output trigger 310 and the input terminal 110 of the write amplifier 330. When a memory read / write error occurs, the primary detection switch 360 and the secondary detection switch 370 close sequentially to locate the fault location of the memory based on the output signal of the input / output circuit 100. In this embodiment, at most one of the primary detection switch 360 and the secondary detection switch 370 may be closed at the same time.

[0024] Please see Figure 1 As shown, in one embodiment of this utility model, the signal detection path that can be activated in the memory includes a first detection loop and a second detection loop. The first detection loop includes an input terminal 110, a logic circuit 200, a first-level detection switch 360, and an output terminal 120. The second detection loop includes an input terminal 110, a logic circuit 200, a write amplifier 330, a second-level detection switch 370, a read amplifier 320, an output trigger 310, and an output terminal 120. When a read / write error occurs in the memory, the first-level detection switch 360 is closed first, thereby forming the first detection loop inside the memory. At this time, an external device writes data to the memory from the input terminal 110. The storage signal reaches the logic circuit 200 from the input terminal 110, then returns to the logic circuit 200 through the first-level detection switch 360, and then reaches the output terminal 120. The input terminal 110 has an input value, and the output terminal 120 has an output value. When the input value of the input terminal 110 and the output value of the output terminal 120 are not equal, there is a fault area in the activated signal detection path in the memory, and the fault area can be directly located as the logic circuit 200.

[0025] Please see Figure 1As shown, in one embodiment of this utility model, when the input value of input terminal 110 and the output value of output terminal 120 are equal, there is no fault in the activated signal detection path in the memory. The first-level detection switch 360 is disconnected, the second-level detection switch 370 is closed again, and the input and output values ​​are reacquired. At this time, the path of the stored signal in the memory is the second detection loop. Specifically, the stored signal reaches the logic circuit 200 from input terminal 110, then reaches the write amplifier 330, then directly reaches the read amplifier 320 through the second-level detection switch 370, then the output signal reaches the output trigger 310, then the output signal returns to the logic circuit 200, and then the output signal is output from output terminal 120. If there is no fault in the first detection loop, and the input value of input terminal 110 and the output value of output terminal 120 are not equal, the fault area can be directly located as the peripheral circuit 300. The fault area can be any one of the write amplifier, read amplifier 320, and output trigger 310, or the connecting wires between the devices. If the first detection circuit checks out no faults, and the input value of input terminal 110 and the output value of output terminal 120 are equal, then the fault area can be directly located in address selector 340 or storage circuit 400.

[0026] Please see Figure 1 and Figure 2As shown, in one embodiment of this utility model, the peripheral circuit 300 includes a process switching switch 380. The first terminal of the process switching switch 380 is electrically connected to the address selector 340, the second terminal of the process switching switch 380 is electrically connected to the read amplifier 320, and the third terminal of the process switching switch 380 is electrically connected to the write amplifier 330. When the memory is working, the first terminal is electrically connected to the second terminal, or the first terminal is electrically connected to the third terminal. When an external device writes data to the memory, the input data and storage signal are input from the input terminal 110, processed by the logic circuit 200, and reach the write amplifier 330. At this time, the first terminal and the third terminal of the process switching switch 380 are electrically connected, thereby completing the selection of the data write address and completing the data write. When an external device wants to read data from the memory, the output trigger 310 is activated, the first terminal and the second terminal of the process switching switch 380 are electrically connected, and then the amount of data to be read is amplified many times, and after being processed by the output trigger 310 and the logic circuit 200, it is output from the output terminal 120. In this embodiment, the process switching switch 380 can be a dual-control switch. In another embodiment of this invention, a first process switching switch 381 and a second process switching switch 382 are provided. One end of the first process switching switch 381 is electrically connected to the address selector 340, and the other end is electrically connected to the read amplifier 320. One end of the second process switching switch 382 is electrically connected to the address selector 340, and the other end is electrically connected to the write amplifier 330. When the memory is working, either the first process switching switch 381 or the second process switching switch 382 is closed.

[0027] Please see Figure 1 As shown, in one embodiment of this utility model, the peripheral circuit 300 includes a pre-charge module 350, which is electrically connected to the storage circuit 400 and the address selector 340. The pre-charge module 350 may be a capacitor.

[0028] Please see Figure 1 As shown, in one embodiment of this invention, the primary detection switch 360 and the secondary detection switch 370 each include at least one MOSFET. In this invention, the switching function can be implemented not only by a single MOSFET, but also by connecting multiple MOSFETs in series and parallel, combined with logic gate control, thereby improving the stability of the test.

[0029] The embodiments of this utility model disclosed above are merely illustrative of the present utility model. The embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Obviously, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A static random access memory, characterized in that, include: Storage circuit; An address selector is electrically connected to the storage circuit; A read amplifier is electrically connected to the address selector when the memory is in a read process. A write amplifier is electrically connected to the address selector when the memory is in the write process, and the input terminal of the write amplifier is electrically connected to the read amplifier through a two-stage detection switch. An output trigger is electrically connected to the input terminal of the sense amplifier, and the output terminal of the output trigger is electrically connected to the input terminal of the write amplifier through a first-stage detection switch. A logic circuit is electrically connected to the output terminal of the output flip-flop and the input terminal of the write amplifier; as well as Input / output circuitry, electrically connected to the logic circuitry and external devices; When a read / write error occurs in the memory, the first-level detection switch and the second-level detection switch are closed in sequence to locate the fault location of the memory based on the output signal of the input / output circuit.

2. A static random access memory according to claim 1, characterized in that, At most one of the primary detection switch and the secondary detection switch may be closed at the same time.

3. A static random access memory according to claim 1, characterized in that, The input / output circuit includes an input terminal and an output terminal. The output terminal and the input terminal are electrically connected to the logic circuit and the external device. When the input value of the input terminal and the output value of the output terminal are equal, there is no fault in the activated signal detection path in the memory. When the input value of the input terminal and the output value of the output terminal are not equal, the activated signal detection path in the memory is faulty.

4. A static random access memory according to claim 3, characterized in that, The signal detection path that can activate the memory includes a first detection loop and a second detection loop. The first detection loop includes the input terminal, the logic circuit, the first-level detection switch, and the output terminal. The second detection loop includes the input terminal, the logic circuit, the write amplifier, the second-level detection switch, the read amplifier, the output trigger, and the output terminal.

5. A static random access memory according to claim 1, characterized in that, The memory includes peripheral circuitry, and the peripheral circuitry, the storage circuitry, and the logic circuitry are disposed on the same chip substrate. The output trigger, the read amplifier, the write amplifier, the address selector, the first-level detection switch, and the second-level detection switch are disposed in the peripheral circuitry.

6. A static random access memory according to claim 5, characterized in that, The peripheral circuit includes a process switching switch. The first terminal of the process switching switch is electrically connected to the address selector, the second terminal of the process switching switch is electrically connected to the read amplifier, and the third terminal of the process switching switch is electrically connected to the write amplifier. When the memory is working, the first terminal is electrically connected to the second terminal, or the first terminal is electrically connected to the third terminal.

7. A static random access memory according to claim 5, characterized in that, The peripheral circuit includes: A first process switching switch, one end of which is electrically connected to the address selector, and the other end of which is electrically connected to the sense amplifier; and The second process switching switch is electrically connected at one end to the address selector and at the other end to the write amplifier. When the memory is in operation, either the first process switching switch or the second process switching switch is closed.

8. A static random access memory according to claim 5, characterized in that, The peripheral circuit includes a pre-charge module, which is electrically connected to the storage circuit and the address selector.

9. A static random access memory according to claim 1, characterized in that, The primary detection switch and the secondary detection switch each include at least one MOSFET.

10. An electronic device, characterized in that, Includes the static random access memory as described in any one of claims 1 to 9.

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