High-speed CMOS sensor power supply circuit and electronic device

Abstract

The utility model provides a kind of high-speed CMOS sensor power supply circuit and electronic equipment, by adopting the hybrid power supply framework of DC-DC and LDO cooperation of on-chip integrated inductance, and using the bias power generation scheme based on voltage reference source and analog switch, the contradiction that power supply ripple and conversion efficiency is difficult to take into account in traditional design is fundamentally solved, the power dissipation and system temperature rise of LDO are reduced, and simultaneously, since rejecting external discrete inductance and a large number of LDO, circuit board occupied area is reduced, and support is provided for the miniaturization and light and thin design of terminal equipment.In addition, by adopting voltage reference source and thin film resistance, it is ensured that the bias power supply has excellent voltage precision and temperature stability, and the imaging quality and consistency of CMOS sensor under different working environments are guaranteed.The utility model realizes the effective control of system cost and the improvement of production yield with fewer component quantity and more simplified circuit structure.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit power supply technology, and in particular to a high-speed CMOS sensor power supply circuit and electronic equipment. Background Technology

[0002] With the rapid development of smartphones, autonomous driving, security monitoring, and machine vision, high-speed CMOS image sensors, as core sensing components, directly affect the imaging quality and reliability of the final system. Modern high-speed CMOS sensors have evolved into highly complex system-on-a-chip (SoCs), integrating millions or even hundreds of millions of pixel units, analog front-ends, analog-to-digital converters, digital signal processors, and high-speed interfaces. This high degree of integration results in the existence of multiple power rails with different voltage, current, and noise characteristics within the sensor, posing unprecedented challenges to the design of its power supply circuits.

[0003] Specifically, in the power supply architecture of high-speed CMOS sensors, the power rails can be broadly divided into two categories: one is the main power rail that powers the analog and digital circuits, requiring a large current and being extremely sensitive to power supply ripple; the other is the bias power rail that provides precise bias to the pixel units, requiring high voltage accuracy and low temperature drift characteristics, and needing to meet specific power-on sequences to ensure stable sensor initialization. Traditional power supply solutions, such as those using switching power supplies or low-dropout linear regulators, often fall short when faced with these conflicting requirements, struggling to achieve a good balance between power efficiency, output ripple, chip area, and thermal management.

[0004] However, existing power supply solutions have significant limitations. First, for the main power rail, while a switching power supply offers high conversion efficiency, its inherent switching noise and large ripple can severely interfere with sensitive analog circuits, leading to fixed-pattern noise or artifacts in the image. If an LDO is used alone, although it provides clean power, its power dissipation increases dramatically when the input-output voltage difference is large, causing severe overheating and affecting sensor performance and lifespan. Second, for the bias power rail, existing designs typically use multiple LDOs combined with a thick-film resistor divider network to generate multiple biases. This approach not only fails to meet high image quality requirements due to the limited accuracy and temperature drift of the LDOs and resistors themselves, but also requires a large number of LDOs to achieve complex power-on sequences, resulting in a large number of components, complex circuit layout, high cost, and hindering device miniaturization. Therefore, a new power supply circuit solution that can comprehensively solve the above problems is urgently needed. Utility Model Content

[0005] In view of the above problems, a high-speed CMOS sensor power supply circuit and electronic device are proposed to overcome or at least partially solve the above problems, specifically: A high-speed CMOS sensor power supply circuit includes: The power conversion module includes at least one on-chip integrated inductor DC-DC power supply and at least one LDO regulator. The input terminal of the on-chip integrated inductor DC-DC power supply is connected to an external input voltage, the output terminal of the on-chip integrated inductor DC-DC power supply is connected to the input terminal of the LDO regulator, and the output terminal of the LDO regulator is connected to a CMOS sensor. The bias power generation module includes a voltage reference source, a multi-channel analog switch, a resistor divider, and a buffer. The output of the voltage reference source is connected to the input of the multi-channel analog switch. The output of each channel of the multi-channel analog switch is connected to at least one resistor divider composed of thin-film resistors. The output of each resistor divider is connected to the input of the buffer, and the output of the buffer is connected to a CMOS sensor. There are two thin-film resistors connected in series. The main control unit's control signal output terminals are connected to the enable terminal of the LDO regulator and the channel selection control terminal of the multi-channel analog switch, respectively.

[0006] Optionally, an RC low-pass filter is connected between the output of the voltage reference source and the input of the multi-channel analog switch.

[0007] Optionally, a buffer can be connected in series between the RC low-pass filter and the input of the multi-channel analog switch.

[0008] Optionally, the number of channels of the multi-channel analog switch can be configured according to the power-on sequence of the bias power supply.

[0009] Optionally, when the power conversion module has multiple LDO regulators, the input of at least one LDO regulator is directly connected to an external input voltage.

[0010] An electronic device includes: a high-speed CMOS sensor power supply circuit as described above; and a high-speed CMOS sensor electrically connected to the power supply circuit.

[0011] This invention fundamentally solves the contradiction between power supply ripple and conversion efficiency in traditional designs by employing a hybrid power supply architecture that combines on-chip integrated inductors with a coordinated LDO (Limited-Dual-Action Logic Controller) and a bias power generation scheme based on a voltage reference source and analog switches. This significantly reduces LDO power dissipation and system temperature rise. Furthermore, by eliminating external discrete inductors and a large number of LDOs, the circuit board area is greatly reduced, providing crucial support for the miniaturization and thinning of terminal devices. In addition, the use of a voltage reference source and thin-film resistors ensures excellent voltage accuracy and temperature stability of the bias power supply, effectively guaranteeing the imaging quality and consistency of CMOS sensors under different operating environments. With fewer components and a more streamlined circuit structure, this invention achieves effective control of system costs and improved production yield, demonstrating high practical value and market competitiveness. Attached Figure Description

[0012] To more clearly illustrate the technical solution of this utility model, the drawings used in the description of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a block diagram of a high-speed CMOS sensor power supply circuit system provided in an embodiment of this utility model. Detailed Implementation

[0014] To make the above-mentioned objectives, features, and advantages of this utility model more apparent and understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0015] High-speed CMOS sensors often integrate modules such as pixel sensors, ADCs, memory cells, and high-speed interfaces. This results in multiple power rails, including power supplies for analog and digital circuits, as well as bias power supplies for the pixel sensors, making the power supply circuit design very complex.

[0016] Analog and digital circuits typically draw large currents, placing high demands on the ripple of the power supply. This is especially true for compact designs, which must balance meeting ripple requirements with minimizing board size and heat dissipation, making power supply circuit design quite challenging.

[0017] Existing designs often use DC-DC power supplies, but these have significant ripple and switching noise. Furthermore, conventional DC-DC power supplies typically require externally soldered inductors, which severely reduces PCB board size. On the other hand, designs using LDO power supplies generate substantial power dissipation in the LDO, causing the LDO and the board temperature to rise and affecting the quality of CMOS output.

[0018] The bias power supply powers the pixel sensor. A pixel sensor is a processing unit that converts light signals into electrical signals, typically consisting of three or four MOSFETs and photodiodes. Its unique structure necessitates multiple bias power supplies, which often require both source and sink currents, usually powered by operational amplifiers. However, typical operational amplifiers lack an enable pin, necessitating additional circuitry for power-on timing control. Since the bias power supply voltage is directly related to the image quality and stability of the CMOS sensor, its accuracy and temperature stability must also be guaranteed.

[0019] In existing designs, the bias power supply circuit typically consists of an LDO, a resistor divider, and a buffer. Bias power supplies operating in the same power-on sequence are supplied with a reference voltage by the same LDO. This reference voltage is then divided by resistors and buffered by an operational amplifier to power the CMOS bias power supply. The main control unit controls the timing of the bias power supply by controlling the LDO enable pin.

[0020] However, existing designs have the following drawbacks: First, LDOs have low accuracy and high temperature coefficients, making them unable to meet the requirements of high-precision, low-temperature-drift bias power supplies. Second, when there are many power rails with different power-on sequences, multiple LDOs are required, which limits low-cost and miniaturized designs.

[0021] Therefore, it can be seen that the power supply circuit of the existing high-speed CMOS sensor has the following shortcomings: its analog and digital power supply circuits cannot simultaneously address power ripple, power efficiency, and board size. Low ripple design leads to low power efficiency, resulting in increased power consumption and severe heat generation. On the other hand, high efficiency design results in excessively large power ripple. Furthermore, its bias power supply circuit suffers from drawbacks such as complex design, numerous required components, low precision, and large temperature drift, which in turn increases cost and limits the realization of miniaturization design.

[0022] This utility model embodiment provides a high-speed CMOS sensor power supply circuit, which may specifically include: The power conversion module includes at least one on-chip integrated inductor DC-DC power supply and at least one LDO regulator. The input terminal of the on-chip integrated inductor DC-DC power supply is connected to an external input voltage, the output terminal of the on-chip integrated inductor DC-DC power supply is connected to the input terminal of the LDO regulator, and the output terminal of the LDO regulator is connected to a CMOS sensor. The bias power generation module includes a voltage reference source, a multi-channel analog switch, a resistor divider, and a buffer. The output of the voltage reference source is connected to the input of the multi-channel analog switch. The output of each channel of the multi-channel analog switch is connected to at least one resistor divider composed of thin-film resistors. The output of each resistor divider is connected to the input of the buffer, and the output of the buffer is connected to a CMOS sensor. There are two thin-film resistors connected in series. The main control unit's control signal output terminals are connected to the enable terminal of the LDO regulator and the channel selection control terminal of the multi-channel analog switch, respectively.

[0023] In this embodiment of the invention, the power conversion module is responsible for powering the analog and digital circuitry of the CMOS sensor. This module employs a hybrid architecture of "pre-stage buck converter + post-stage regulator." Specifically, at least one on-chip integrated inductor DC-DC power supply is deployed at the front end of the circuit, receiving an external input voltage (e.g., 5V) and stepping it down to a lower intermediate voltage (e.g., 1.8V). This intermediate voltage is then fed to the input of at least one LDO regulator. Through this cascading method, the power loss due to the high voltage drop is primarily borne by the high-efficiency DC-DC power supply, allowing the LDO regulator to handle only a very low voltage drop, thereby significantly reducing the LDO's own power dissipation and heat generation. Finally, the clean power supply with extremely low ripple provided by the LDO regulator output is directly connected to the corresponding power pin of the CMOS sensor, meeting its power quality requirements.

[0024] The bias power generation module is responsible for providing the bias voltage to the CMOS sensor. The signal chain of this module begins with a voltage reference source, which generates a stable reference voltage. This reference voltage is directly fed to the common input of a multi-channel analog switch. The output of each individual channel of the analog switch is connected to a resistor divider consisting of two thin-film resistors in series. By configuring the resistance ratio of these two thin-film resistors, various desired bias voltage values ​​can be obtained from the reference voltage. The output of each resistor divider is then connected to the input of a buffer (typically a voltage follower composed of operational amplifiers). The buffer provides sufficient current sourcing and sinking capabilities and isolates the voltage divider network from the influence of subsequent loads, ensuring voltage accuracy. The output of the buffer is finally connected to the power-time-controlled bias power supply pins of the CMOS sensor.

[0025] The control signal output terminals of the main control unit are connected to the enable terminal of the LDO regulator in the power conversion module and the channel selection control terminal of the multi-channel analog switch in the bias power generation module. By executing a preset program, the main control unit controls the timing of these enable signals and channel selection signals, thereby strictly following the power-on sequence required by the CMOS sensor and sequentially turning on each power rail, ensuring that the sensor can be reliably initialized and operate stably.

[0026] In a preferred embodiment of this invention, an RC low-pass filter is connected between the output terminal of the voltage reference source and the input terminal of the multi-channel analog switch.

[0027] Furthermore, a buffer is connected in series between the RC low-pass filter and the input of the multi-channel analog switch.

[0028] To provide a stable voltage reference to the bias power supply generation module, a signal conditioning circuit is installed between the output of the voltage reference source and the input of the multi-channel analog switch. This circuit specifically consists of an RC low-pass filter and a buffer. The initial reference voltage generated by the voltage reference source is first fed into this RC low-pass filter. The function of this filter is to attenuate broadband noise, especially high-frequency noise components, from the voltage reference source itself and the preceding power supply to the maximum extent possible, thereby significantly improving the signal-to-noise ratio of the reference signal.

[0029] However, in practical applications, RC filters may suffer from high output impedance. If directly driving multiple loads in subsequent stages, the filtered reference voltage will fluctuate due to load changes, compromising its accuracy. Therefore, a unity-gain operational amplifier is connected in series at the output of the RC low-pass filter as a buffer. This buffer serves to isolate and enhance the driving capability: its high input impedance ensures no load effect on the preceding RC filter network, guaranteeing unaffected filtering performance; while its low output impedance easily drives each channel of the subsequent multi-channel analog switch and its connected resistor divider network, forming a stable, low-impedance buffered reference voltage. This fundamentally ensures that the reference voltage applied to the source terminals of the multi-channel analog switch possesses both high stability and strong driving capability.

[0030] In practical applications, the number of channels of a multi-channel analog switch can be configured according to the power-on sequence of the bias power supply.

[0031] Specifically, the main control unit stores a preset power-on timing program, which is connected to the channel selection control terminal of the multi-channel analog switch via general-purpose input / output pins. When the system starts, the main control unit does not enable all channels simultaneously, but instead sends different channel selection signals to the analog switch sequentially according to the preset timing logic. For example, in an application with four independent bias power-on sequences, a single-pole four-throw analog switch can be selected; if the sequence increases to six, a single-pole six-throw or higher channel-count switch is required. This allows the same high-precision reference voltage to be time-division multiplexed onto multiple different resistor divider networks, thus replacing the multi-channel timing control function that traditional solutions require multiple LDOs with only one voltage reference source and one multi-channel analog switch. This not only greatly reduces the number of required components, lowering material costs and board space, but also ensures the consistency of initial accuracy and temperature drift characteristics among the bias voltages since all bias voltages originate from the same reference, which is beneficial to improving the overall performance of the sensor. Therefore, by replacing analog switches with different numbers of channels and adjusting the timing control logic of the main control unit, the power supply circuit of this invention can be adapted to high-speed CMOS sensors of different models with different power-on timing requirements, and has excellent scalability and versatility.

[0032] In an embodiment of this utility model, when the power conversion module has multiple LDO regulators, the input terminal of at least one LDO regulator is directly connected to an external input voltage.

[0033] Specifically, when there are multiple LDO regulators in the power conversion module, not all LDOs adopt the cascaded architecture of DC-DC pre-step + LDO. Instead, they are designed differently according to the specific electrical characteristics of each power rail and the overall optimization goal of the system. That is, the input terminal of at least one LDO regulator is directly connected to the external input voltage.

[0034] It is understandable that for power rails with relatively low operating current or small input-output voltage differences within the sensor, using DC-DC pre-stepping would offer limited efficiency gains and instead increase system complexity and cost. In this embodiment, for example, the 1.8V power rail supplying the sensor's input / output interface requires only a few milliamps of current. Using a separate LDO to directly step down the 5V external voltage to 1.8V, although there is a voltage drop across the LDO (3.2V), the power dissipation is extremely low due to the minimal load current, well within acceptable heat dissipation limits. This direct connection eliminates the need for a DC-DC power chip and its peripheral circuitry, simplifying the design and saving PCB area and material costs.

[0035] This invention also provides an electronic device, comprising: a high-speed CMOS sensor power supply circuit as described above; and a high-speed CMOS sensor electrically connected to the power supply circuit.

[0036] This invention fundamentally solves the contradiction between power supply ripple and conversion efficiency in traditional designs by employing a hybrid power supply architecture that combines on-chip integrated inductors with a coordinated LDO (Limited-Dual-Action Logic Controller) and a bias power generation scheme based on a voltage reference source and analog switches. This significantly reduces LDO power dissipation and system temperature rise. Furthermore, by eliminating external discrete inductors and a large number of LDOs, the circuit board area is greatly reduced, providing crucial support for the miniaturization and thinning of terminal devices. In addition, the use of a voltage reference source and thin-film resistors ensures excellent voltage accuracy and temperature stability of the bias power supply, effectively guaranteeing the imaging quality and consistency of CMOS sensors under different operating environments. With fewer components and a more streamlined circuit structure, this invention achieves effective control of system costs and improved production yield, demonstrating high practical value and market competitiveness.

[0037] It is understood that this utility model is only an example of this high-speed CMOS image sensor. Any other high-speed CMOS sensor, as long as it is designed with a CMOS power supply circuit, can be implemented using this utility model. The number of DC-DC inductors and the number of channels of analog switches used can be flexibly selected to meet the actual use conditions.

[0038] For example, when a power rail current in an analog or digital circuit is large and using an LDO results in a high voltage drop, a DC-DC power supply with an integrated inductor can be added to step down the voltage as an intermediate power supply. Similarly, when the bias power supply has more power-on timing stages, analog switches with more channels can be selected for timing control. Both of these can improve efficiency, reduce heat generation, lower costs, and reduce the number of components used, ultimately facilitating the design and implementation of miniaturized, highly reliable, and highly stable products.

[0039] The above is the overall concept of this utility model. For ease of understanding, the following embodiments are also provided.

[0040] Reference Figure 1 High-speed CMOS sensors require 4 analog or digital power rails and 5 bias power rails, with a total of 6 power-on stages controlled by the main control unit. The entire circuit is powered by a unified 5V power supply, and its power-on process is as follows: First, the main control unit controls the first-stage timing power-on: VDDIO (1.8V, <5mA) is directly generated from 5V via LDO regulation. Simultaneously, the crucial pre-buck channel is activated: a DC-DC power supply with integrated inductors on a single chip converts 5V to 1.8V, serving as the intermediate power supply for the subsequent high-current LDO; another LDO steps down the 5V to 4.5V to power the analog circuitry. After receiving a 4.5V supply, the voltage reference source generates a precision reference voltage REF of 4.096V. This voltage is filtered by an RC low-pass filter and buffered by an operational amplifier to generate a low-noise voltage REF_BUF, which is then fed into the three source terminals (S1, S2, S3) of the three-channel analog switch.

[0041] Subsequently, the main control unit executes the second and third level timing: simultaneously powering on VDDAD and VDDD (both 1.5V, 400mA). Given the large current, both are generated from the aforementioned 1.8V intermediate power supply produced by the DC-DC converter via an LDO, significantly reducing the LDO's voltage drop and power consumption. Next, VDDAD (3.3V, 80mA) is powered on, directly generated from 5V via an LDO.

[0042] Subsequently, the main control unit controls the analog switch channel to power on the bias power supply in three steps: With channel 1 activated, REF_BUF is output to node REF1, and then through a thin-film resistor voltage divider network (3.6kΩ and 11.3kΩ; 2kΩ and 14.7kΩ) and buffered by an operational amplifier, two bias power supplies, 3.1V (VDDPIX) and 3.6V (VRH), are generated simultaneously.

[0043] With channel 2 activated, REF_BUF is output to node REF2. After voltage division (5.9kΩ and 820Ω) and buffering, a 0.5V (VTX2L) bias power supply is generated.

[0044] With channel 3 activated, REF_BUF is output to node REF3. After voltage division (3.9kΩ and 4.99kΩ; 6.8kΩ and 5.1kΩ) and buffering, two bias power supplies, 2.3V (VRF) and 1.75V (VREF), are generated simultaneously.

[0045] The above provides a detailed description of the high-speed CMOS sensor power supply circuit and electronic device. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A high-speed CMOS sensor power supply circuit, characterized in that, The circuit includes: A power conversion module includes at least one on-chip integrated inductor DC-DC power supply and at least one LDO regulator. The input terminal of the on-chip integrated inductor DC-DC power supply is connected to an external input voltage, the output terminal of the on-chip integrated inductor DC-DC power supply is connected to the input terminal of the LDO regulator, and the output terminal of the LDO regulator is connected to a CMOS sensor. A bias power generation module includes a voltage reference source, a multi-channel analog switch, a resistor divider, and a buffer. The output of the voltage reference source is connected to the input of the multi-channel analog switch. The output of each channel of the multi-channel analog switch is connected to at least one resistor divider composed of thin-film resistors. The output of each resistor divider is connected to the input of the buffer, and the output of the buffer is connected to a CMOS sensor. There are two thin-film resistors connected in series. The main control unit has its control signal output terminal connected to the enable terminal of the LDO regulator and the channel selection control terminal of the multi-channel analog switch, respectively.

2. The circuit according to claim 1, characterized in that, An RC low-pass filter is connected between the output of the voltage reference source and the input of the multi-channel analog switch.

3. The circuit according to claim 2, characterized in that, A buffer is connected in series between the RC low-pass filter and the input terminal of the multi-channel analog switch.

4. The circuit according to claim 3, characterized in that, The number of channels of the multi-channel analog switch is configured according to the power-on sequence of the bias power supply.

5. The circuit according to claim 1, characterized in that, When the power conversion module has multiple LDO regulators, the input terminal of at least one of the LDO regulators is directly connected to the external input voltage.

6. An electronic device, characterized in that, The electronic device includes: a high-speed CMOS sensor power supply circuit as claimed in any one of claims 1 to 5; and a high-speed CMOS sensor electrically connected to the power supply circuit.

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