A signal design circuit capable of resisting pulse group

Abstract

The utility model relates to electronic circuit technical field discloses a signal design circuit of anti impulse group, including digital isolator U27, power filter module, RS485 signal drive module, impedance matching module, overvoltage protection module and connector YX3, the first filter unit is by electric capacity C104, electric capacity C191 and resistance R192 are composed, is used for to VDD_3V3_MAIN power filter, is the non -isolated side power supply of digital isolator U27. In the utility model, for the signal port of external connection, adopt the combination mode of common mode filter and bidirectional TVS pipe, form the common mode and difference mode double -restrained of impulse group interference, ensure that the RS485 difference signal stable of signal port transmission of external connection, restrain impulse group interference, can realize the restraint common mode interference through common mode filter, and bidirectional TVS pipe can realize the restraint difference mode interference.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, and in particular to a signal design circuit that is resistant to pulse bursts. Background Technology

[0002] Burst interference is a short-duration, high-frequency, high-amplitude transient electromagnetic pulse that mainly intrudes into circuits in two forms: common-mode interference (between signal lines and ground) and differential-mode interference (between signal lines). Therefore, it is necessary to develop a signal design circuit that is resistant to burst interference.

[0003] A signal design circuit capable of withstanding pulse bursts can address the shortcomings of traditional circuits in protecting against complex electromagnetic environments, ensuring long-term stable operation of equipment under pulse burst interference scenarios. However, in previous technologies, traditional signal circuits mostly relied on a single bidirectional TVS diode for overvoltage protection, which is insufficient to cope with the complex characteristics of pulse burst interference. Utility Model Content

[0004] To overcome the above shortcomings, this utility model provides a signal design circuit that is resistant to pulse bursts, aiming to improve the problem that traditional signal circuits in the prior art rely on a single bidirectional TVS diode for overvoltage protection, which is difficult to cope with the complex characteristics of pulse burst interference.

[0005] To achieve the above objectives, this utility model provides the following technical solution: a signal design circuit resistant to pulse bursts, including a digital isolator U27, a power supply filtering module, an RS485 signal driving module, an impedance matching module, an overvoltage protection module, and a connector YX3. The power supply filtering module includes a first filtering unit and a second filtering unit. The first filtering unit consists of capacitor C104, capacitor C191, and resistor R192, used to filter the VDD_3V3_MAIN power supply to power the non-isolated side of the digital isolator U27. The second filtering unit consists of capacitors C214 and C220 connected in parallel. One end of each capacitor C214 and capacitor C220 is connected to the VDD_5V0_ISO1 power supply, and the other end is connected to GND. I1 is used to filter the VDD_5V0_ISO1 power supply and supply power to the isolation side of the digital isolator U27. The RS485 signal driving module includes an inverter U24. The impedance matching module includes resistors R136 and R137 and a common-mode filter L7. The overvoltage protection module includes a bidirectional TVS protection array chip U30 and a bidirectional TVS diode D32 to suppress transient overvoltages and protect the circuit. The connector YX3 is used to connect to external devices. The power filtering module is electrically connected to the digital isolator U27. The digital isolator U27 is signal-connected to the RS485 signal driving module and the impedance matching module. The impedance matching module is electrically connected to the overvoltage protection module. The overvoltage protection module is signal-connected to the connector YX3.

[0006] Through the above technical solution: Preferably, pin 1 of the digital isolator U27 is connected to one end of resistor R192, resistor R192 is connected to VDD_3V3_MAIN power supply, VDD_3V3_MAIN power supply is connected to one end of capacitor C194 and capacitor C191, capacitor C194 and capacitor C191 are connected in parallel, and the other end of capacitor C194 and capacitor C191 are both connected to GNDI1.

[0007] Preferably, pins 2, 7, and 8 of the digital isolator U27 are all connected to GNDI1. Pin 2 of the digital isolator U27 is connected to one end of resistor R191, and the other end of resistor R191 is connected to the receive signal line of UART1. The other end of resistor R192 is connected to pin 3 of the digital isolator U27. Pins 4 and 5 of the digital isolator U27 are both connected to one end of resistor R190. The other end of resistor R190 is connected to pin 4 of inverter U24. Pin 5 of inverter U24 is connected to the VDD_3V3_MAIN power supply, and pin 3 is connected to GNDI1. Pin 2 of inverter U24 is connected to one end of resistor R179, and the other end of resistor R179 is connected to an external control signal line. Pin 6 of the digital isolator U27 is connected to one end of resistor R189, and the other end of resistor R189 is connected to the transmit signal line of UART1.

[0008] Preferably, pin 16 of the digital isolator U27 is connected to the VDD_5V0_ISO1 power supply; pins 9, 10, and 15 of the digital isolator U27 are all connected to GNDI1; pin 12 of the digital isolator U27 is connected to one end of resistor R215, and the other end of resistor R215 is connected to the VDD_5V0_ISO1 power supply; pin 13 of the digital isolator U27 is connected to one end of resistor R216, and the other end of resistor R216 is connected to GNDI1; resistor R215 is connected to the UART_485_A1 differential signal line; and resistor R215 is connected to the UART_485_B1 differential signal line.

[0009] Preferably, one end of capacitor C218 is connected to the UART_485_A1 differential signal line, one end of capacitor C219 is connected to R216 on the UART_485_B1 differential signal line, the other ends of capacitors C218 and C219 are both connected to GNDI1, one end of resistor R200 is connected to the UART_485_A1 differential signal line, and the other end of resistor R200 is connected to the UART_485_B1 differential signal line.

[0010] Preferably, a resistor R136 is connected in series on the UART_485_A1 differential signal line, pin 1 of the common-mode filter L7 is connected to the UART_485_A1 differential signal line, a resistor R137 is connected in series on the UART_485_B1 differential signal line, and pin 2 of the common-mode filter L7 is connected to the UART_485_B1 differential signal line.

[0011] Preferably, the bidirectional TVS protection array chip U30 integrates a bidirectional TVS diode. The UART_485_A1 differential signal line is connected to pin 2 of the bidirectional TVS protection array chip U30, the UART_485_B1 differential signal line is connected to pin 1 of the bidirectional TVS protection array chip U30, pin 3 of the bidirectional TVS protection array chip U30 is connected to GNDI1, pin 2 of the bidirectional TVS protection array chip U30 is connected to a 485A2 signal line, and pin 1 of the bidirectional TVS protection array chip U30 is connected to a 485B2 signal line. The 485A2 and 485B2 signal lines are used to connect to an external interface.

[0012] Preferably, pin 7 of connector YX3 is connected to the UART_485_A1 differential signal line, pin 8 of connector YX3 is connected to the UART_485_B1 differential signal line, a bidirectional TVS diode D32 is connected in parallel between the UART_485_A1 and UART_485_B1 differential signal lines, pin 9 of connector YX3 is connected to GNDI1, and pin 11 of connector YX3 is connected to EGND9.

[0013] This utility model has the following beneficial effects: 1. In this utility model, for the external signal port, a combination of a common-mode filter and a bidirectional TVS diode is adopted to form a dual suppression of common-mode and differential-mode interference of pulse group interference, ensuring the stability of the RS485 differential signal input from the external signal port and suppressing pulse group interference. The common-mode filter can suppress common-mode interference, and the bidirectional TVS diode can suppress differential-mode interference. Through the cooperation of multiple modules, comprehensive suppression of differential-mode and common-mode interference in pulse group is achieved, avoiding interference from intruding into the core circuit and causing communication errors or device damage.

[0014] 2. In this utility model, the power supply filtering module can provide a clean power supply for the digital isolator U27. The isolator realizes electrical isolation between the front and back circuits, cuts off the interference conduction path, and the inverter U24 adapts to the control signal requirements through logic inversion, while enhancing the signal driving capability and ensuring accurate transmission of control commands. The reasonable grounding and signal pin allocation of connector YX3 not only provide a reliable discharge path for interference current, but also realizes the standardized docking with external devices. This circuit ensures the stable operation of RS485 communication and circuit safety. Attached Figure Description

[0015] Figure 1 This is a circuit connection diagram of a signal design circuit that is resistant to pulse bursts, as proposed in this utility model. Detailed Implementation

[0016] The technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0017] Reference Figure 1 This utility model provides an embodiment of a signal design circuit resistant to pulse bursts, including a digital isolator U27, a power supply filtering module, an RS485 signal driving module, an impedance matching module, an overvoltage protection module, and a connector YX3. The power supply filtering module includes a first filtering unit and a second filtering unit. The first filtering unit consists of capacitors C104 and C191 and resistor R192, used to filter the VDD_3V3_MAIN power supply to power the non-isolated side of the digital isolator U27. The second filtering unit consists of capacitors C214 and C220 connected in parallel. One end of each capacitor C214 and C220 is connected to the VDD_5V0_ISO1 power supply, and the other end is connected to GND. I1 is used to filter the VDD_5V0_ISO1 power supply and power the isolation side of the digital isolator U27. The RS485 signal drive module includes an inverter U24. The impedance matching module includes resistors R136 and R137 and a common-mode filter L7. The overvoltage protection module includes a bidirectional TVS protection array chip U30 and a bidirectional TVS transistor D32 to suppress transient overvoltages and protect the circuit. Connector YX3 is used to connect to external devices. The power filtering module is electrically connected to the digital isolator U27. The digital isolator U27 is signal connected to the RS485 signal drive module and the impedance matching module. The impedance matching module is electrically connected to the overvoltage protection module. The overvoltage protection module is signal connected to connector YX3. Specifically, capacitor C214 filters high-frequency noise, and capacitor C220 filters low-frequency ripple. The parallel connection of these two filter capacitors removes wideband noise from the VDD_5V0_ISO1 power supply, preventing power supply noise from coupling to the RS485 signal link through the isolator. This provides a stable operating voltage for the digital isolator U27, ensuring its isolation performance meets standards and preventing isolation failure due to power fluctuations, thus preserving its core function of common-mode interference suppression. The digital isolator U27 isolates the front-end control signals from the RS485 driver circuit, and the inverter U24 performs logic inversion and drives the RS485 communication control signals, adapting them to the back-end circuit's signal... To prevent front-end noise from intruding into the external communication link through control signals, the differential signal output pins A and B of the digital isolator U27 are connected to one end of resistors R136 and R137 in the impedance matching module, respectively. The RS485 differential signal output from the isolator first passes through resistors R136 and R137 to match the characteristic impedance of the RS485 bus, reducing signal reflection during transmission, especially in long-distance transmission, and preventing pulse group interference amplification caused by the superposition of reflected signals. At the same time, resistors R136 and R137 act as current limiters, protecting the digital isolator U27 in case of external overcurrent. The common-mode filter L7 further filters the signal after impedance matching. The process utilizes its high impedance characteristics for common-mode signals to suppress common-mode interference from external sources and prevent interference from propagating to the digital isolator. The bidirectional TVS protection array chip U30 clamps differential-mode overvoltage between lines A and B before common-mode filtering, and the bidirectional TVS diode D32 further clamps residual differential-mode interference after filtering. This dual protection ensures that the downstream circuitry is protected from differential-mode overvoltage damage. The RS485 signal, after impedance matching, common-mode filtering, and dual differential-mode protection, is connected to external devices via connector YX3, ensuring that the signal entering the external device is free from significant interference. Simultaneously, external interference is suppressed at multiple stages before entering the internal circuitry, and the power supply filtering module further enhances its effectiveness. To ensure the stable operation of the digital isolator U27 and prevent power supply noise from becoming a source of interference, the digital isolator U27 can disconnect the electrical connection between internal and external circuits, blocking the transmission of common-mode interference at the source. Through impedance matching and the synergy of the common-mode filter L7, signal reflection can be reduced and common-mode interference can be suppressed. The dual TVS diodes D32 can protect against differential-mode overvoltage with precise clamping. Finally, the connector YX3 enables anti-interference communication with external devices. Through the above connections, a complete link is formed from power supply filtering, signal driving, isolation, impedance matching to overvoltage protection. The common-mode filter L7 suppresses common-mode interference, and the bidirectional TVS diodes suppress differential-mode interference, together achieving the function of resisting pulse group interference.

[0018] Reference Figure 1Pin 1 of digital isolator U27 is connected to one end of resistor R192. Resistor R192 is connected to the VDD_3V3_MAIN power supply. The VDD_3V3_MAIN power supply is connected to one end of capacitors C194 and C191. Capacitors C194 and C191 are connected in parallel. The other ends of capacitors C194 and C191 are both connected to GNDI1. Pins 2, 7, and 8 of digital isolator U27 are all connected to GNDI1. Pin 2 of digital isolator U27 is connected to one end of resistor R191. The other end of resistor R191 is connected to the receive signal line of UART1. The other end of pin 2 is connected to pin 3 of digital isolator U27. Pins 4 and 5 of digital isolator U27 are both connected to one end of resistor R190. The other end of resistor R190 is connected to pin 4 of inverter U24. Pin 5 of inverter U24 is connected to VDD_3V3_MAIN power supply. Pin 3 is connected to GNDI1. Pin 2 of inverter U24 is connected to one end of resistor R179. The other end of resistor R179 is connected to an external control signal line. Pin 6 of digital isolator U27 is connected to one end of resistor R189. The other end of resistor R189 is connected to the transmit signal line of UART1. Specifically, resistor R192 limits the maximum current flowing into the isolator's power supply terminal and suppresses high-frequency spike noise in the VDD_3V3_MAIN power supply, preventing noise from entering the isolator through the power supply pins. Capacitor C194 filters out high-frequency noise, and C191 filters out low-frequency ripple, thus forming a wideband power supply filter network to provide a stable operating voltage for the isolator and reduce the impact of power supply noise on isolation performance. By defining the isolator's ground reference, the internal signal reference potential of the isolator can be ensured to be uniform, avoiding signal distortion caused by ground potential deviation. Multi-pin grounding can reduce grounding impedance and improve common-mode interference immunity. Resistor R191 limits the input signal current, protects the isolator's input pins, and stabilizes the level of the UART received signal, avoiding noise interference caused by floating. This path allows external UART received signals to be input to the isolator, then isolated and transmitted to the back-end circuitry. Resistor R189 stabilizes the level of the UART transmit signal, enabling the input of external UART transmit signals to the isolator. Resistor R190 acts as a current-limiting resistor for the isolator's output signal, protecting the input pins of inverter U24. Digital isolator U27 outputs isolated control signals through pins 4 and 5, which are transmitted to inverter U24 for logic inversion, adapting to the control logic of the back-end circuit. Connecting pin 5 of inverter U24 to VDD_3V3_MAIN power and pin 3 to GNDI1 provides operating power and ground reference for inverter U24, ensuring stable logic inversion. Resistor R179 acts as a current-limiting resistor for external control signals, preventing overcurrent damage to inverter U24. External control signals can also assist in adjusting the output logic of inverter U24. These connections achieve interference-resistant transmission of UART and control signals, providing isolation protection for the back-end RS485 circuit.

[0019] Reference Figure 1Pin 16 of digital isolator U27 is connected to the VDD_5V0_ISO1 power supply. Pins 9, 10, and 15 of digital isolator U27 are all connected to GNDI1. Pin 12 of digital isolator U27 is connected to one end of resistor R215, and the other end of resistor R215 is also connected to the VDD_5V0_ISO1 power supply. Pin 13 of digital isolator U27 is connected to one end of resistor R216, and the other end of resistor R216 is connected to GNDI1. Resistor R215 is connected to the UART_485_A1 differential signal line and the UART_485_B1 differential signal line. Capacitor C21 is connected to the UART_485_A1 differential signal line. On one end of line 8, R216 is connected to one end of capacitor C219 on the UART_485_B1 differential signal line. The other ends of capacitors C218 and C219 are both connected to GNDI1. On one end of line 8, resistor R200 is connected to the UART_485_A1 differential signal line. The other end of resistor R200 is connected to the UART_485_B1 differential signal line. Resistor R136 is connected in series on the UART_485_A1 differential signal line. Pin 1 of common-mode filter L7 is connected on the UART_485_A1 differential signal line. Resistor R137 is connected in series on the UART_485_B1 differential signal line. Pin 2 of common-mode filter L7 is connected on the UART_485_B1 differential signal line. Specifically, by directly connecting the isolation-side power supply pin 16 of the digital isolator U27 to the VDD_5V0_ISO1 power supply, an independent power supply can be provided for the isolation-side circuit of the digital isolator U27, forming electrical isolation from the non-isolated side VDD_3V3_MAIN. This prevents main power supply noise from coupling to the RS485 signal link through the isolator. By unifying the ground reference potential of the isolation-side circuit, the level reference of the RS485 differential signal can be ensured to be stable. Multi-pin grounding can reduce grounding impedance and enhance the discharge capability against common-mode interference. By using resistor R215 as a pull-up resistor, the idle level of the UART_485_A1 differential signal line can be pulled to VDD_5V0_ISO1. V0_ISO1 is used to avoid noise interference caused by floating signals and to provide a reference level for differential signals, ensuring accurate logic judgment. Resistor R216 acts as a pull-down resistor, pulling the idle level of the UART_485_B1 differential signal line to GNDI1. This, in conjunction with R215, stabilizes the idle state of the differential signal, ensuring that the voltage on line A is always higher than that on line B by a certain value, preventing misjudgments. Resistor R215 is connected in series with the UART_485_A1 line, and then one end of capacitor C218 is connected. Resistor R216 is connected in series with the UART_485_B1 line, and then one end of capacitor C219 is connected. The other ends of capacitors C218 and C219 are both connected to G. The NDI1 uses capacitors C218 and C219 to filter out high-frequency differential-mode noise in the differential signal, preventing noise amplification by the common-mode filter while not affecting the transmission of low-frequency differential signals. Resistors R200 are connected to the UART_485_A1 and UART_485_B1 differential signal lines respectively. Resistor R200 is a termination matching resistor with the characteristic impedance of the RS485 bus, reducing signal reflection during long-distance transmission and preventing reflections from superimposing on the original signal to form pulse group interference, thus ensuring signal integrity. After passing through R200, the UART_485_A1 differential signal line is connected in series with resistor R136, while the UART_485_B1 differential signal... After passing through R200, the line is connected in series with resistor R137. R136 and R137 are series matching resistors, which can work with the terminating resistor R200 to further optimize the impedance matching effect. At the same time, it limits the current flowing into the common-mode filter L7 and protects the subsequent circuit. Pin 1 of the common-mode filter L7 is connected to the end of R136 away from line A, pin 2 is connected to the end of R137 away from line B, pin 3 is led out to line A on the connector side, and pin 4 is led out to line B on the connector side. The common-mode filter L7 uses the high impedance characteristics of the common-mode inductor to the common-mode signal to suppress common-mode interference from external sources or generated internally, and prevents interference from being conducted to the digital isolator. It is the core component for suppressing pulse group interference.

[0020] Reference Figure 1The bidirectional TVS protection array chip U30 integrates a bidirectional TVS diode. Pin 2 of the bidirectional TVS protection array chip U30 is connected to the UART_485_A1 differential signal line, pin 1 of the bidirectional TVS protection array chip U30 is connected to the UART_485_B1 differential signal line, pin 3 of the bidirectional TVS protection array chip U30 is connected to GNDI1, and pin 2 of the bidirectional TVS protection array chip U30 is connected to the 485A2 signal line. Pin 1 is connected to the 485B2 signal line, the 485A2 signal line, and the 485B2 signal line for connecting to external interfaces; pin 7 of connector YX3 is connected to the UART_485_A1 differential signal line, pin 8 of connector YX3 is connected to the UART_485_B1 differential signal line, a bidirectional TVS diode D32 is connected in parallel between the UART_485_A1 and UART_485_B1 differential signal lines, pin 9 of connector YX3 is connected to GNDI1, and pin 11 of connector YX3 is connected to EGND9; Specifically, the bidirectional TVS protection array chip U30 can serve as a primary differential-mode overvoltage protection. When burst interference is received from external interfaces 485A2 and 485B2, its internal bidirectional TVS transistor quickly conducts, clamping the overvoltage between the differential signal lines of UART_485_A1 and UART_485_B1 within a safe range, preventing interference from directly entering the internal circuitry. It also provides a ground reference for the bidirectional TVS protection array chip U30, allowing the current generated by transient overvoltage to be discharged through GNDI1, preventing interference energy from accumulating on the signal lines. The connection between the ground pin of connector YX3 and GNDI1 provides a discharge path for common-mode interference. To prevent interference from accumulating at the interface, the bidirectional TVS diode D32 serves as a secondary differential mode overvoltage protection. It performs secondary clamping on the differential mode interference that remains after the initial suppression by the bidirectional TVS protection array chip U30, further reducing the impact of interference on the digital isolator U27 and inverter U24. Together with the bidirectional TVS protection array chip U30, it forms dual differential mode protection. Connector YX3 connects to the UART_485_A1 and UART_485_B1 differential signal lines through pins 7 and 8, enabling differential signal interaction with external RS485 devices. The signal after multiple protections at the front end can effectively resist pulse group interference, ensuring communication accuracy.

[0021] Working Principle: In use, capacitors C214 and C220 connected in parallel in the power filter module filter the VDD_5V0_ISO1 power supply, removing high-frequency and low-frequency noise and providing stable power to the downstream circuits. Digital isolator U27, connected to resistor R192 via pin 1, filters the VDD_3V3_MAIN power supply (filtered by capacitors C194 and C191). Pin 16 directly connects to the VDD_5V0_ISO1 power supply, achieving electrical isolation between the isolated and non-isolated sides, preventing interference from being conducted between the two circuits. Pin #1 isolates the input signal for transmission to the output, preventing external interference from entering the internal circuitry through the signal path. The inverter U24 in the RS485 signal driver module can logically invert the control signal output from the digital isolator U27, thus adapting it to the enable logic of the RS485 transceiver. In the impedance matching module, resistors R136 and R137 work in conjunction with the common-mode filter L7. First, resistors R136 and R137 match the characteristic impedance of the RS485 bus, reducing signal reflection. Then, the common-mode filter L7 utilizes the common-mode impedance... The high impedance characteristic of the signal can suppress common-mode interference from external sources or generated internally. In the overvoltage protection module, the bidirectional TVS protection array chip U30 integrates a bidirectional TVS diode. Its pins 1 and 2 are connected to the differential signal lines of UART_485_B1 and UART_485_A1, respectively, and pin 3 is grounded. Thus, when a transient overvoltage is introduced from the external interface, it can quickly conduct to clamp the differential overvoltage and discharge the interference current through the ground pin. The bidirectional TVS diode D32 is connected in parallel with UART_485_A1 and UART_485_B1. Between the _B1 differential signal lines, secondary clamping can be performed on the differential mode interference that remains after the initial suppression by the bidirectional TVS protection array chip U30. By connecting pins 7 and 8 of connector YX3 to the protected UART_485_A1 and UART_485_B1 differential signal lines respectively, communication with external RS485 devices can be realized. By connecting pin 9 to GNDI1 and pin 11 to EGND9, a reliable grounding path can be established to ensure stable signal transmission and introduce interference current to the ground to ensure circuit safety. This circuit employs a combination of a common-mode filter L7 and a bidirectional TVS diode for protection. On the external signal path, the differential signal lines at the external port are first connected to the differential signal lines B and A via pins 1 and 2 of the bidirectional TVS protection array chip U30, respectively, with pin 3 grounded. The integrated bidirectional TVS diode quickly clamps differential-mode transient overvoltages between the signal lines, limiting differential-mode interference to a safe range. Subsequently, the signal enters the common-mode filter L7. Its high impedance to common-mode signals effectively suppresses common-mode interference between lines A and B relative to ground. To prevent common-mode bursts from propagating along the signal lines into the internal circuitry, a secondary differential-mode protection is formed by connecting a bidirectional TVS diode D32 in parallel between the differential signal lines of UART_485_A1 and UART_485_B1. This further attenuates the differential-mode interference remaining after common-mode filtering. Through the combined design of the differential-mode clamping bidirectional TVS protection array chip U30, the common-mode filter L7, and the secondary differential-mode clamping bidirectional TVS diode D32, targeted suppression of differential-mode and common-mode components in burst interference is achieved, thereby ensuring the communication stability of the external signal port.

[0022] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A signal design circuit resistant to pulse bursts, comprising a digital isolator U27, a power supply filtering module, an RS485 signal driving module, an impedance matching module, an overvoltage protection module, and a connector YX3, characterized in that: The power filtering module includes a first filtering unit and a second filtering unit. The first filtering unit consists of capacitor C104, capacitor C191, and resistor R192, used to filter the VDD_3V3_MAIN power supply to power the non-isolated side of the digital isolator U27. The second filtering unit consists of capacitors C214 and C220 connected in parallel. One end of each capacitor C214 and C220 is connected to the VDD_5V0_ISO1 power supply, and the other end is connected to GNDI1, used to filter the VDD_5V0_ISO1 power supply to power the isolated side of the digital isolator U27. The RS48... The signal driving module includes an inverter U24; the impedance matching module includes resistors R136 and R137 and a common-mode filter L7; the overvoltage protection module includes a bidirectional TVS protection array chip U30 and a bidirectional TVS diode D32 for suppressing transient overvoltages and protecting the circuit; the connector YX3 is used to connect to external devices; the power filtering module is electrically connected to a digital isolator U27; the digital isolator U27 is signal-connected to the RS485 signal driving module and the impedance matching module; the impedance matching module is electrically connected to the overvoltage protection module; and the overvoltage protection module is signal-connected to the connector YX3.

2. The signal design circuit resistant to pulse bursts according to claim 1, characterized in that: Pin 1 of the digital isolator U27 is connected to one end of resistor R192. Resistor R192 is connected to the VDD_3V3_MAIN power supply. The VDD_3V3_MAIN power supply is connected to one end of capacitor C194 and capacitor C191. Capacitor C194 and capacitor C191 are connected in parallel. The other ends of capacitor C194 and capacitor C191 are both connected to GNDI1.

3. The signal design circuit resistant to pulse bursts according to claim 2, characterized in that: Pins 2, 7, and 8 of the digital isolator U27 are all connected to GNDI1. Pin 2 of the digital isolator U27 is connected to one end of resistor R191, and the other end of resistor R191 is connected to the receive signal line of UART1. The other end of resistor R192 is connected to pin 3 of the digital isolator U27. Pins 4 and 5 of the digital isolator U27 are both connected to one end of resistor R190, and the other end of resistor R190 is connected to pin 4 of inverter U24. Pin 5 of inverter U24 is connected to the VDD_3V3_MAIN power supply, and pin 3 is connected to GNDI1. Pin 2 of inverter U24 is connected to one end of resistor R179, and the other end of resistor R179 is connected to an external control signal line. Pin 6 of the digital isolator U27 is connected to one end of resistor R189, and the other end of resistor R189 is connected to the transmit signal line of UART1.

4. The signal design circuit resistant to pulse bursts according to claim 2, characterized in that: Pin 16 of the digital isolator U27 is connected to the VDD_5V0_ISO1 power supply. Pins 9, 10, and 15 of the digital isolator U27 are all connected to GNDI1. Pin 12 of the digital isolator U27 is connected to one end of resistor R215, and the other end of resistor R215 is connected to the VDD_5V0_ISO1 power supply. Pin 13 of the digital isolator U27 is connected to one end of resistor R216, and the other end of resistor R216 is connected to GNDI1. Resistor R215 is connected to the UART_485_A1 differential signal line and the UART_485_B1 differential signal line.

5. A signal design circuit resistant to pulse bursts according to claim 4, characterized in that: One end of capacitor C218 is connected to the UART_485_A1 differential signal line, and one end of capacitor C219 is connected to R216 on the UART_485_B1 differential signal line. The other ends of capacitors C218 and C219 are both connected to GNDI1. One end of resistor R200 is connected to the UART_485_A1 differential signal line, and the other end of resistor R200 is connected to the UART_485_B1 differential signal line.

6. The signal design circuit resistant to pulse bursts according to claim 4, characterized in that: A resistor R136 is connected in series on the UART_485_A1 differential signal line, and pin 1 of the common-mode filter L7 is connected to the UART_485_A1 differential signal line. A resistor R137 is connected in series on the UART_485_B1 differential signal line, and pin 2 of the common-mode filter L7 is connected to the UART_485_B1 differential signal line.

7. The signal design circuit resistant to pulse bursts according to claim 1, characterized in that: The bidirectional TVS protection array chip U30 integrates a bidirectional TVS diode. The UART_485_A1 differential signal line is connected to pin 2 of the bidirectional TVS protection array chip U30, the UART_485_B1 differential signal line is connected to pin 1 of the bidirectional TVS protection array chip U30, pin 3 of the bidirectional TVS protection array chip U30 is connected to GNDI1, pin 2 of the bidirectional TVS protection array chip U30 is connected to a 485A2 signal line, and pin 1 of the bidirectional TVS protection array chip U30 is connected to a 485B2 signal line. The 485A2 and 485B2 signal lines are used to connect to external interfaces.

8. A signal design circuit resistant to pulse bursts according to claim 1, characterized in that: Pin 7 of connector YX3 is connected to the UART_485_A1 differential signal line, pin 8 of connector YX3 is connected to the UART_485_B1 differential signal line, a bidirectional TVS diode D32 is connected in parallel between the UART_485_A1 and UART_485_B1 differential signal lines, pin 9 of connector YX3 is connected to GNDI1, and pin 11 of connector YX3 is connected to EGND9.

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