Channel module and electric vehicle controller interface chip

Abstract

The utility model discloses a kind of passageway module and electric vehicle controller interface chip, it is related to the field of integrated circuit technology, in the passageway module, driving circuit is driven NMOS switch to open or shut off according to input control signal, and when NMOS switch opens, the gate voltage of NMOS switch can be changed with its source voltage, so it can control the gate-source voltage difference Vgs of NMOS switch in a fixed value or fixed interval, can guarantee NMOS switch low impedance. The utility model uses NMOS switch as high-voltage switch, that is, only using single type high-voltage tube as switch, saves area and cost.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, specifically to a channel module and an electric vehicle controller interface chip. Background Technology

[0002] A port is a terminal in a circuit that allows it to connect to an external circuit. In some high-voltage applications, a high-voltage switch is typically installed between the port and the low-voltage circuit. When the port voltage is high, the high-voltage switch opens, cutting off the path between the port and the low-voltage circuit and preventing damage to the low-voltage circuit from the high voltage at the port. When the port voltage is low, the high-voltage switch can close normally, allowing the port to connect to the low-voltage circuit and enabling the relevant functions of the low-voltage circuit.

[0003] Ensuring low impedance of the high-voltage switch when the port is connected to a low-voltage circuit is a challenge. Existing high-voltage switches generally use a transmission gate structure, which requires the simultaneous use of high-voltage PMOS and high-voltage NMOS transistors, resulting in high cost and large footprint. Utility Model Content

[0004] This invention provides a channel module and an electric vehicle controller interface chip, which can overcome the above-mentioned technical problems.

[0005] To address the aforementioned problems, from a first aspect, this utility model discloses a channel module, comprising: a first port, a low-voltage circuit, an NMOS switch, and a driving circuit;

[0006] Among them, the NMOS switch is a high-voltage transistor, and the NMOS switch is connected between the first port and the low-voltage circuit through its drain and source.

[0007] The driving circuit is connected to the source and gate of the NMOS switch respectively. The driving circuit drives the NMOS switch to turn on or off according to the input control signal, and when the NMOS switch is turned on, the gate voltage of the NMOS switch changes with its source voltage.

[0008] In some embodiments of this utility model, the driving circuit includes a current output module and a clamping circuit; the current output module is used to output a first current under the power supply voltage of the first power supply voltage; the clamping circuit is connected between the first voltage and the output terminal of the current output module; wherein, the clamping circuit is used to clamp the gate voltage of the NMOS switch to a second voltage, so as to drive the NMOS switch to turn on when the control signal indicates to turn on the NMOS switch; the second voltage is greater than the first voltage, and the first voltage is generated based on the source voltage of the NMOS switch.

[0009] In some embodiments of this utility model, the driving circuit further includes a first NMOS transistor and a first switch; the first switch is controlled by a control signal, and the first switch is turned on when the control signal indicates that the NMOS switch is turned on; the gate of the first NMOS transistor is connected to the source of the NMOS switch, the drain of the first NMOS transistor is connected to a second power supply voltage through the first switch, and the source of the first NMOS transistor is used to output a first voltage; the clamping circuit includes a clamping module, the first end of the clamping module is used to connect to the first voltage, and the second end is used to connect to the output end of the current output module, wherein the second voltage is the second terminal voltage of the clamping module.

[0010] In some embodiments of this utility model, the driving circuit further includes a first switch and a first NMOS transistor; the first switch is controlled by a control signal, and the first switch is turned on when the control signal indicates that the NMOS switch is turned on; the gate of the first NMOS transistor is used to connect to the source voltage of the NMOS switch, the drain of the first NMOS transistor is connected to the second power supply voltage through the first switch, and the source of the first NMOS transistor is used to output the first voltage; the clamping circuit includes a clamping module and a voltage divider module, the clamping module and the voltage divider module are connected in parallel and connected between the output terminals of the first voltage and current output module, wherein the second voltage is the voltage divider node voltage of the voltage divider circuit.

[0011] In some embodiments of this utility model, the clamping circuit includes a clamping module. The first end of the clamping module is used to connect to a first voltage, and the second end is used to connect to the output end of the current output module. The first voltage is the source voltage of the NMOS switch, and the second voltage is the voltage at the second end of the clamping module.

[0012] In some embodiments of this utility model, the clamping circuit includes a clamping module and a voltage divider module. The clamping module and the voltage divider module are connected in parallel and then connected between the output terminals of the first voltage and current output module. The first voltage is the source voltage of the NMOS switch, and the second voltage is the voltage divider node voltage of the voltage divider circuit.

[0013] In some embodiments of this utility model, the clamping module is a Zener diode, the cathode of the Zener diode is connected to the output terminal of the current output module, and the anode of the Zener diode is used to connect to the first voltage.

[0014] In some embodiments of this utility model, the driving circuit further includes a current limiting module, which is connected between the first voltage and ground.

[0015] In some embodiments of this invention, the second power supply voltage is lower than the first power supply voltage.

[0016] In some embodiments of this utility model, the driving circuit further includes: a first switch and a second switch controlled by a control signal; the first switch is connected to the driving circuit, and the second switch is connected between the gate of the NMOS switch and ground; when the control signal indicates that the NMOS switch is turned on, the first switch is turned on and the second switch is turned off; when the control signal indicates that the NMOS switch is turned off, the first switch is turned off and the second switch is turned on.

[0017] In some embodiments of this utility model, the current output module includes a first current mirror, a second current mirror, and a withstand voltage unit; the input branch of the first current mirror is used to receive a second current, the output branch of the first current mirror is connected to the input branch of the second current mirror via the withstand voltage unit, and the output branch of the second current mirror is used to output a first current; wherein, the second current mirror is connected to a first power supply voltage, and the first current mirror is grounded.

[0018] In some embodiments of this utility model, the withstand voltage unit includes a second NMOS transistor; wherein, the source of the second NMOS transistor is connected to the output branch of the first current mirror, the drain of the second NMOS transistor is connected to the input branch of the second current mirror, and the gate of the second NMOS transistor is controlled by the inverted signal of the control signal; both the MOS transistor in the second current mirror and the second NMOS transistor are high-voltage transistors.

[0019] In some embodiments of this utility model, the channel module further includes: multiple functional ports and a high-voltage detection circuit; the multiple functional ports are divided into high-voltage detection ports and multiple low-voltage ports, and the port types of the different low-voltage ports are different; the low-voltage circuit is connected between the NMOS switch and the multiple low-voltage ports; the input terminal of the high-voltage detection circuit is connected between the first port and the NMOS switch, and is used to detect the voltage of the first port; the output terminal of the high-voltage detection circuit outputs a detection signal through the high-voltage detection port; wherein, the control signal is generated based on the detection signal.

[0020] Secondly, this utility model also discloses an electric vehicle controller interface chip, comprising:

[0021] Multiple general-purpose pins are provided to provide input and / or output ports for functional signals connected to the electric vehicle controller;

[0022] A channel module is provided for each general-purpose pin. The channel module is the channel module described in the first aspect of this utility model. The first port of the channel module is connected to its corresponding general-purpose pin.

[0023] In some embodiments of this utility model, the channel module also has multiple functional ports, and the port types of the different functional ports are different; the interface chip also includes:

[0024] Communication pins and multiple function pins are used to connect to components in the electric vehicle controller;

[0025] The control module controls the general-purpose pin to connect to the target function pin via the target function port in its corresponding channel module, based on the configuration logic determined by one or more functional signals transmitted through the communication pin; wherein the signal types of the functional signals connecting the target function port and the general-purpose pin are matched, and the functional signals connecting the target function pin and the general-purpose pin are matched.

[0026] This utility model has the following advantages:

[0027] In the channel module disclosed in this utility model, the NMOS switch is a high-voltage transistor connected between the first port and the low-voltage circuit through its drain and source. The driving circuit is connected to the source and gate of the NMOS switch respectively, which can ensure that the NMOS switch has low impedance and can operate in a safe operating voltage region. This utility model uses an NMOS switch as a high-voltage switch, that is, it only uses a single type of high-voltage transistor as a switch, saving area and cost. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application.

[0029] Figure 1 This is a structural schematic diagram of a channel module according to the present invention;

[0030] Figure 2 This is a schematic diagram of the drive circuit of an embodiment of the present invention;

[0031] Figure 3 This is a circuit diagram of the driving circuit of an embodiment of the present invention. Figure 1 ;

[0032] Figure 4 This is a circuit diagram of the driving circuit of an embodiment of the present invention. Figure 2 ;

[0033] Figure 5 This is a circuit diagram of the driving circuit of an embodiment of the present invention. Figure 3 ;

[0034] Figure 6 This is a circuit diagram of the driving circuit of an embodiment of the present invention. Figure 4 ;

[0035] Figure 7 This is a circuit diagram of the driving circuit of an embodiment of the present invention. Figure 5 ;

[0036] Figure 8 This is a schematic diagram of the structure of an electric vehicle controller interface chip according to this utility model.

[0037] Explanation of reference numerals in the attached figures:

[0038] 01-Channel module, 101-First port, 102-Low voltage circuit, 103-NMOS switch, 104-Drive circuit, 105-High voltage detection circuit; 1041-Current output module, 1042-Clamping circuit, 1043-Current source, 1044-Current limiting module; VDD_HV-First power supply voltage, V1-First voltage, V2-Second voltage, CTR1-Control signal, CTR2-Inverted control signal, VDD-Second power supply voltage. Detailed Implementation

[0039] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0040] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0041] In the embodiments of this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly, and can refer to direct connection or indirect connection through an intermediate medium.

[0042] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0043] Ensuring low impedance of the high-voltage switch when the port is connected to a low-voltage circuit is a challenge. Existing high-voltage switches generally use a transmission gate structure, which requires the simultaneous use of high-voltage PMOS and high-voltage NMOS transistors, resulting in high cost and large footprint.

[0044] To solve the above problems, this utility model discloses a channel module 01, such as... Figure 1As shown, the circuit includes a first port 101, a low-voltage circuit 102, an NMOS switch 103, and a driving circuit 104. The NMOS switch 103 is a high-voltage transistor, connected between the first port 101 and the low-voltage circuit 102 via its drain and source. The driving circuit 104 is connected to the source and gate of the NMOS switch 103, respectively. The driving circuit 104 drives the NMOS switch 103 to turn on or off according to an input control signal. When the NMOS switch 103 is on, the gate voltage of the NMOS switch 103 changes with its source voltage.

[0045] This invention uses an NMOS switch 103 as a high-voltage switch, that is, it uses only a single type of high-voltage transistor as a switch, saving area and cost. Optionally, the drain of the NMOS switch 103 is connected to the first port 101, and the source of the NMOS switch 103 is connected to the low-voltage circuit 102.

[0046] The control signal CTR1 is used to indicate whether the NMOS switch 103 is turned on or off. The control signal CTR1 can be generated by relevant control circuitry. For example, in an electric vehicle controller interface chip application, refer to... Figure 8 The channel module 01 within the interface chip also includes multiple functional ports and a high-voltage detection circuit 105. The multiple functional ports are divided into high-voltage detection ports and multiple low-voltage ports, with different port types for each low-voltage port. A low-voltage circuit 102 is connected between an NMOS switch 103 and the multiple low-voltage ports. The input terminal of the high-voltage detection circuit 105 is connected between a first port 101 and the NMOS switch, used to detect the voltage at the first port 101. The output terminal outputs a detection signal through the high-voltage detection port. The control signal CTR1 is generated based on this detection signal. When a high voltage is detected at the first port 101, the control signal CTR1 instructs the NMOS switch 103 to turn off (i.e., the switch is open), cutting off the path between the first port 101 and the low-voltage circuit 102, preventing the high voltage at the first port 101 from damaging the low-voltage circuit 102. When a low voltage is detected at the first port 101, the control signal CTR1 instructs the NMOS switch 103 to turn on (i.e., the switch is closed), allowing the first port 101 to connect to the low-voltage circuit 102.

[0047] The driving circuit 104 outputs the gate voltage of the NMOS switch 103 according to the control signal CTR1, driving the NMOS switch 103 to turn on or off. During the period when the NMOS switch 103 is turned on, the driving circuit 104 of this invention can make the gate voltage of the NMOS switch 103 change with its source voltage. That is, the driving circuit 104 can adaptively adjust the gate voltage of the NMOS switch 103 according to the source voltage of the NMOS switch 103, thus controlling the gate-source voltage difference Vgs of the NMOS switch 103 within a fixed value or a fixed range. Under this fixed value or fixed range, the gate-source voltage difference Vgs of the NMOS switch 103 will not be too small, so that the impedance of the NMOS switch 103 is too large, which may cause some problems (such as affecting the current flow between the first port 101 and the low-voltage circuit 102 and causing excessive power consumption; for example, in the application of electric vehicle interface chips, too large an impedance may prevent the power supply target from being achieved). Furthermore, under this fixed value or fixed range, the gate-source voltage difference Vgs of the NMOS switch 103 will not be too large, so as not to exceed the safe operating voltage of the NMOS switch 103 and damage the NMOS switch 103.

[0048] In this utility model, reference Figure 2 The driving circuit 104 may include a current output module 1041 and a clamping circuit 1042. The current output module 1041 is used to output a first current under the power supply voltage VDD_HV. The clamping circuit 1042 is connected between the first voltage V1 and the output terminal of the current output module 1041. The clamping circuit 1042 is used to clamp the gate voltage of the NMOS switch 103 to a second voltage V2, so as to drive the NMOS switch 103 to turn on when the control signal CTR1 indicates that the NMOS switch 103 is turned on. The second voltage V2 is greater than the first voltage V1, and the first voltage V1 is generated based on the source voltage of the NMOS switch 103.

[0049] In this utility model, such as Figure 3-5 As shown, the current output module 1041 may include a first current mirror, a second current mirror, and a withstand voltage unit; the input branch of the first current mirror is used to receive a second current, the output branch of the first current mirror is connected to the input branch of the second current mirror via the withstand voltage unit, and the output branch of the second current mirror is used to output a first current; wherein, the second current mirror is connected to the first power supply voltage VDD_HV, and the first current mirror is grounded.

[0050] The second current is generated by a current source 1043. The first and second current mirrors can be a cascaded transistor current mirror structure (such as a Cascode current mirror) or a standard single-stage current mirror structure. Figure 3As shown, the first and second current mirrors are both cascaded transistor current mirror structures. The first current mirror includes NMOS transistors NM1, NM2, NM6, and NM7. NM1 and NM2 share a common gate and their sources are grounded together. NM6 and NM7 share a common gate. The drain of NM1 is connected to the source of NM6, and the source of NM6 serves as the input branch of the first current mirror for receiving the second current. The drain of NM2 is connected to the source of NM7, and the drain of NM7 serves as the output branch of the first current mirror. The second current mirror includes PMOS transistors PM0, PM1, PM3, and PM4. PM0 and PM1 share a common gate, and their sources are both connected to the first power supply voltage VDD_HV. PM3 and PM4 share a common gate. The drain of PM0 is connected to the source of PM3, and the drain of PM3 serves as the input branch of the second current mirror. The drain of PM1 is connected to the source of PM4, and the drain of PM4 serves as the output branch of the second current mirror for outputting the first current.

[0051] By using a first current mirror and a second current mirror, the second current provided by current source 1043 is replicated, ultimately outputting the first current. The design of NM6 and NM7 increases the output impedance and reduces the impact of the current mirror drain load on the current output. Figure 3 As shown, it may also include NMOS transistors NM9 and NM10. NM9 is connected between the drain and gate of NM6 through its source and drain, and NM10 is connected between the drain and gate of NM1 through its source and drain. The gates of NM9 and NM10 are both controlled by the inverted signal CTR2 of control signal CTR1. When control signal CTR1 instructs NMOS switch 103 to be turned on, NM9 and NM10 are also turned on based on CTR2.

[0052] It is important to emphasize that the accompanying drawings are merely schematic diagrams illustrating parts relevant to the concept of this utility model. In practical applications, the circuits may have minor modifications or some anti-power consumption or security designs, which will not be listed here. For example, such as... Figure 3 As shown, the current output module 1041 also includes NMOS transistors NM11 and NM12. The gates of NM11 and NM12 are both connected to the control signal CTR1, and their sources are both grounded. When the control signal CTR1 indicates that the NMOS switch 103 is on, CTR1 is low, and NM11 and NM12 are not on. When the control signal CTR1 indicates that the NMOS switch 103 is off, both NM11 and NM12 are on. The drain of NM11 is used for the output voltage VBN, and the drain of NM12 is used for the output voltage VBNC. Voltage VBN is connected to the gate of NM2, and voltage VBNC is connected to the gate of NM7. Voltages VBN and VBNC can completely shut off the replicated current when the drive circuit is not working, avoiding additional power consumption.

[0053] like Figure 4-5 As shown, the first and second current mirrors can also be ordinary single-stage current mirror structures. The first current mirror consists of NMOS transistors NM1 and NM2, and the second current mirror consists of PM0 and PM1. NM1 and NM2 share a common gate and their sources are both grounded. The drain of NM1 serves as the input branch of the first current mirror to receive the second current output from the current source 1043, and the drain of NM2 serves as the output branch of the first current mirror. PM0 and PM1 share a common gate and their sources are connected to the first power supply voltage VDD_HV. The drain of PM0 serves as the input branch of the second current mirror, and the drain of PM1 serves as the output branch of the second current mirror to output the first current. Wherein, as... Figure 4 As shown, it may also include an NMOS transistor NM0, which is controlled by a control signal CTR1. When the control signal CTR1 indicates that the NMOS switch 103 is turned on, NM0 is turned off; when the control signal CTR1 indicates that the NMOS switch 103 is turned off, NM0 is turned off to stop the first current mirror from working and save energy.

[0054] In a feasible circuit, the first current mirror is always a low-voltage transistor, and the second current mirror is always a high-voltage transistor. For example... Figure 3 In the series, NM1, NM2, NM6, and NM7 are all low-pressure pipes, while PM0, PM1, PM3, and PM4 are all high-pressure pipes.

[0055] The output branch of the first current mirror is connected to the input branch of the second current mirror via a withstand voltage unit. The withstand voltage unit isolates the high-voltage from the low-voltage components, protecting the low-voltage transistor. For example... Figure 3 As shown, the withstand voltage unit may include a second NMOS transistor NM14; wherein the source of the second NMOS transistor NM14 is connected to the output branch of the first current mirror, the drain of the second NMOS transistor is connected to the input branch of the second current mirror, and the gate of the second NMOS transistor is controlled by the inverted signal CTR2 of the control signal CTR1. The second NMOS transistor NM14 may also be a high-voltage transistor. Further optional, such as... Figure 3 As shown, the withstand voltage unit can also include a resistor R0 to further isolate high and low voltage. Of course, theoretically, the withstand voltage unit can also be implemented with only a resistor R0. Figure 3-5 The current mirror and voltage withstand unit shown are merely illustrative. In some embodiments, a voltage withstand unit may also be provided between the output branch of the second current mirror and the clamping circuit 1042, such as... Figure 3 The resistor R3 in the middle.

[0056] In this invention, the driving circuit 104 is used to receive the source voltage of the NMOS switch 103 and output the gate voltage of the NMOS switch 103. The clamping circuit 1042 is used to clamp the gate voltage of the NMOS switch 103 to a second voltage V2, meaning the gate voltage of the NMOS switch 103 is the second voltage V2. Furthermore, since the clamping circuit 1042 is connected to the first voltage V1 and the output terminal of the current output module 1041, and the first voltage V1 is generated based on the source voltage of the NMOS switch 103, based on this connection, the gate voltage of the NMOS switch 103 can vary with its source voltage when it is turned on, allowing for multiple implementation methods.

[0057] In some implementations, reference Figures 2-4 The driving circuit 104 may further include a first NMOS transistor and a first switch; the first switch is controlled by a control signal CTR1, and the first switch is turned on when the control signal CTR1 indicates that the NMOS switch 103 is turned on; the gate of the first NMOS transistor is connected to the source of the NMOS switch 103, the drain of the first NMOS transistor is connected to the second power supply voltage VDD through the first switch, and the source of the first NMOS transistor is used to output the first voltage V1. The clamping circuit 1042 may include a clamping module and a voltage divider module, which are connected in parallel between the first voltage V1 and the output terminal of the current output module 1041, wherein the second voltage V2 is the voltage divider node voltage of the voltage divider circuit.

[0058] In this embodiment, the gate voltage of the NMOS switch 103 is the voltage divider node voltage of the voltage divider circuit, and the source voltage of the NMOS switch 103 is connected to the gate of the first NMOS transistor. For example... Figure 3 and Figure 4 As shown, the first NMOS transistor is NMOS transistor NM5, and the first switch can be implemented using PMOS transistor PM2. The gate of PM2 is used to connect to the control signal CTR1, the drain of PM2 is connected to the drain of NM5, and the source of PM2 is used to connect to the second power supply voltage VDD. When the control signal CTR1 indicates that NMOS switch 103 is turned on, PM2 is turned on; when the control signal CTR1 indicates that NMOS switch 103 is turned off, PM2 is turned off. The gate of NM5 is used to connect to the source voltage of NMOS switch 103.

[0059] A voltage divider module can be implemented using a resistor voltage divider circuit, such as... Figure 3 and Figure 4As shown, the voltage divider module includes resistors R1 and R2, used to divide the voltage on the clamping circuit 1042. The voltage at the voltage divider node is the node voltage between resistors R1 and R2. Therefore, V2 = Vz * R2 / (R1 + R2) + V1, where Vz is the breakdown voltage of the clamping module, and * indicates multiplication. That is, the gate voltage Vg of the NMOS switch 103 = V2 = Vz * R2 / (R1 + R2) + V1.

[0060] After PM2 is turned on, the voltage at the first port 101 may fluctuate. When the source voltage Vs of NMOS switch 103 is less than the turn-on threshold voltage Vth of NM5, NM5 cannot be turned on, and V1 equals 0. Since the source voltage of NMOS switch 103 can be considered close to 0 at this time, the gate-source voltage difference Vgs of NMOS switch 103 is basically equal to VZ*R2 / (R1+R2). When the source voltage Vs of NMOS switch 103 is greater than or equal to the turn-on threshold voltage Vth of NM5, NM5 is turned on, V1=Vs-Vth, and the gate-source voltage difference Vgs of NMOS switch 103=Vg-Vs=VZ*R2 / (R1+R2)-Vth.

[0061] In this embodiment, by setting an appropriate clamping module and resistors R1 and R2, the Vgs of the NMOS switch 103 can be controlled within a fixed value or a fixed range. This fixed value or fixed range will not be too small, so that the impedance of the NMOS switch 103 is too large; nor will this fixed value or fixed range be too large, so that it exceeds the safe operating voltage of the NMOS switch 103 and damages the NMOS switch 103.

[0062] In other embodiments, reference is made to Figure 5 The driving circuit 104 may further include a first NMOS transistor and a first switch; the first switch is controlled by a control signal CTR1, and the first switch is turned on when the control signal CTR1 indicates that the NMOS switch 103 is turned on; the gate of the first NMOS transistor is connected to the source of the NMOS switch 103, the drain of the first NMOS transistor is connected to the second power supply voltage VDD through the first switch, and the source of the first NMOS transistor is used to output the first voltage V1. The clamping circuit 1042 may include a clamping module, the first terminal of the clamping module is used to connect to the first voltage V1, and the second terminal is used to connect to the output terminal of the current output module 1041, wherein the second voltage V2 is the second terminal voltage of the clamping module.

[0063] In this embodiment, the gate voltage Vg of the NMOS switch 103 is the second terminal voltage of the clamping module, and the source voltage Vs of the NMOS switch 103 is connected to the gate of the first NMOS transistor. Vg = V2 = Vz + V1, where Vz is the breakdown voltage of the clamping module. Figure 5As shown, the first NMOS transistor is NM5, and the first switch can be implemented using the PMOS transistor PM2. The connection relationship between NM5 and PM2 can be referenced as follows: Figure 3 and Figure 4 The implementation methods shown will not be described in detail here.

[0064] After PM2 is turned on, with the fluctuation of the voltage at the first port 101, when the source voltage Vs of NMOS switch 103 is less than the turn-on threshold voltage Vth of NM5, NM5 cannot be turned on, and the first voltage V1 is equal to 0. At this time, the source voltage Vs of NMOS switch 103 can be considered close to 0. Therefore, the gate-source voltage difference Vgs of NMOS switch 103 is basically equal to Vz. When the source voltage Vs of NMOS switch 103 is greater than or equal to the turn-on threshold voltage Vth of NM5, NM5 is turned on, V1 = Vs - Vth, and the gate-source voltage difference Vgs of NMOS switch 103 = Vg - Vs = Vz - Vth.

[0065] In this embodiment, by setting an appropriate clamping module, the Vgs of the NMOS switch 103 can be controlled within a fixed value or a fixed range. Figure 3 and Figure 4 Compared to the embodiments shown Figure 5 This implementation provides more control space and more effectively controls the low impedance of NMOS switches while operating in a safe operating voltage range.

[0066] In this invention, the second power supply voltage VDD is less than the first power supply voltage VDD_HV. When the NMOS switch is turned on and the first port 101 is mistakenly connected to a high voltage, the drain voltage of the NMOS switch 103 connected to the first port 101 may exceed the second power supply voltage VDD. Correspondingly, the source voltage of the NMOS switch 103 will also be very large, causing NM5 to be fully turned on. The first voltage V1 is pulled to the second power supply voltage VDD, making the maximum first voltage V1 VDD. In this case, if... Figure 3 and Figure 4 In the NMOS switch 103, the gate voltage Vg reaches a maximum of VZ*R2 / (R1+R2)+VDD. The source voltage Vs of the NMOS switch 103 continues to increase until Vs=VZ*R2 / (R1+R2)+VDD-VTH, where VTH is the turn-on threshold voltage of the NMOS switch 103. At this point, even if the drain voltage Vd of the NMOS switch 103 continues to increase, the source voltage Vs of the NMOS switch 103 will no longer increase.

[0067] Furthermore, in such Figures 3-5In the illustrated embodiment, the driving circuit 104 may further include a current limiting module 1044, which is connected between the first voltage V1 and ground. Optionally, the current limiting module 1044 can be implemented using a resistor or a MOSFET. Figure 3 and Figure 4 As shown, the current limiting module 1044 includes an NMOS transistor NM3. NM3 and NM1 in the current output module 1041 form a current mirror to realize current replication. The source of NM3 is grounded. Figure 3 In this structure, NM8, NM6, NM1, and NM3 also form a Cascode current mirror structure. The drain of NM3 is connected to the source of NM8, and the drain of NM8 is connected to the source of NM5. NM8 and NM6 share a common gate, which can increase the output impedance of the current mirror, reduce the influence of the load voltage on the current magnitude, and make the current replication more accurate.

[0068] In other embodiments, reference is made to Figure 6 The clamping circuit 1042 may include a clamping module. A first terminal of the clamping module is used to connect to a first voltage V1, and a second terminal is used to connect to the output terminal of the current output module 1041. The first voltage V1 is the source voltage of the NMOS switch 103, and the second voltage V2 is the voltage at the second terminal of the clamping module. In this embodiment, the following is omitted: Figure 3-5 The first NMOS transistor and current limiting module 1044 are shown. The source and gate of the NMOS switch 103 are directly connected to the two ends of the clamping circuit 1042, where Vs=V1 and Vg=V2=Vz+V1. After the control signal CTR1 indicates that the NMOS switch 103 is turned on, the gate-source voltage difference of the NMOS switch 103 is Vgs=Vg-Vs=Vz, where Vz is the breakdown voltage of the clamping module. In this embodiment, by setting an appropriate clamping module, the Vgs of the NMOS switch 103 can be controlled within a fixed value or a fixed range.

[0069] In other embodiments, reference is made to Figure 7 The clamping circuit 1042 may include a clamping module and a voltage divider module. The clamping module and the voltage divider module are connected in parallel between the first voltage V1 and the output terminal of the current output module 1041. The first voltage V1 is the source voltage of the NMOS switch 103, and the second voltage V2 is the voltage divider node voltage of the voltage divider circuit. In this embodiment, the following is omitted: Figure 3-5The first NMOS transistor and current limiting module 1044 are shown. The source of NMOS switch 103 is connected to the first terminal of the clamping module. The gate voltage of NMOS switch 103 is the voltage divider node voltage of the voltage divider circuit, i.e., Vg = V2 = Vz * R2 / (R1 + R2) + V1, Vs = V1, and Vz is the breakdown voltage of the clamping module. After the control signal CTR1 indicates that NMOS switch 103 is turned on, the gate-source voltage difference of NMOS switch 103 is Vgs = Vg - Vs = Vz * R2 / (R1 + R2). In this embodiment, by setting an appropriate clamping module and resistors R1 and R2, the Vgs of NMOS switch 103 can be controlled within a fixed value or a fixed range.

[0070] It is worth noting that, Figure 6 and Figure 7 Only the clamping circuit 1042 is shown as a difference; other modules in the drive circuit 104, such as the first switch controlled by the control signal CTR1 and the specific circuitry of the current output module 1041, are not shown.

[0071] In the above embodiments, such as Figure 3-7 As shown, the clamping module preferably uses a Zener diode, wherein the cathode of the Zener diode is connected to the output terminal of the current output module 1041, and the anode of the Zener diode is used to connect to the first voltage V1. Of course, in some other embodiments, the clamping module can also be implemented by a resistor or a common diode, etc., and this utility model does not impose any limitations. It is worth noting that the voltage stability after the Zener diode breaks down is higher, which can maintain the stability of the gate voltage of the NMOS switch 103.

[0072] In this invention, the driving circuit 104 further includes: a first switch and a second switch controlled by a control signal CTR1; the first switch is connected to the driving circuit 104, and the second switch is connected between the gate of the NMOS switch 103 and ground; when the control signal CTR1 indicates that the NMOS switch 103 is turned on, the first switch is turned on and the second switch is turned off; when the control signal CTR1 indicates that the NMOS switch 103 is turned off, the first switch is turned off and the second switch is turned on. Optionally, such as Figure 2-5 As shown, the first switch is implemented by PMOS transistor PM2, and the second switch is implemented by NMOS transistor NM4. When the control signal CTR1 is high, PM2 is turned off, NM4 is turned on, the gate voltage of NMOS switch 103 is pulled down to ground by NM4, and NMOS switch 103 is turned off. When the control signal CTR1 is low, PM2 is turned on, NM4 is turned off, NMOS switch 103 is turned on, and the gate voltage of NMOS switch 103 changes with its source voltage.

[0073] Based on the same inventive concept, this utility model also discloses an electric vehicle controller interface chip, see reference. Figure 8 It includes multiple general-purpose pins and a channel module 01 configured for each general-purpose pin. The general-purpose pins are used to provide input ports and / or output ports for functional signals connected to the electric vehicle controller. The first port 101 of each channel module 01 is connected to the corresponding general-purpose pin of the channel module 01.

[0074] Channel module 01 also has multiple functional ports, each with a different port type. The interface chip also includes: a communication pin (not shown), multiple functional pins (not shown), and a control module (not shown). The communication pin and multiple functional pins are used to connect to components in the electric vehicle controller. The control module controls the general-purpose pin to connect to the target functional pin via its corresponding target functional port in channel module 01, based on the configuration logic determined by one or more functional signals transmitted through the communication pin. The signal types of the functional signals connected between the target functional port and the general-purpose pin are matched, and the functional signals connected between the target functional pin and the general-purpose pin are matched.

[0075] The components in the aforementioned electric vehicle controller include an MCU. Explanations of the communication pins, multiple functional pins, and control module of this interface chip, as well as other circuit structures unrelated to this invention, can be found in the invention patent "An Interface Chip, Electric Vehicle Controller and Its Control System" (publication number CN120491521A). It is worth noting that in this invention, the control signal received by the drive circuit can directly or indirectly originate from the control module. The input terminal of the high-voltage detection circuit 105 is connected between the first port 101 and the NMOS switch, used to detect the voltage at the first port 101, and the output terminal outputs a detection signal through the high-voltage detection port. The control signal CTR1 is generated based on the detection signal. According to the configuration logic determined by one or more functional signals transmitted by the MCU through the communication pins, the control module can directly or indirectly generate the control signal CTR1 in each channel module 01, controlling the NMOS switch in the channel module 01 to turn on or off, ultimately achieving communication between the general-purpose pin and the target functional port in the channel module 01.

[0076] Specifically, the channel module 01 is the channel module 01 proposed in this utility model. That is, as follows... Figure 8As shown, the channel module 01 includes a first port 101, a low-voltage circuit 102, an NMOS switch 103, and a driving circuit 104. The NMOS switch 103 is a high-voltage transistor, and its drain and source are connected between the first port 101 and the low-voltage circuit 102. The driving circuit 104 is connected to the source and gate of the NMOS switch 103 respectively. The driving circuit 104 drives the NMOS switch 103 to turn on or off according to the input control signal CTR1. When the NMOS switch 103 is turned on, the gate voltage of the NMOS switch 103 changes with its source voltage.

[0077] For details regarding the feasible circuit structures and related principles of the control signal CTR1 and the drive circuit 104, please refer to the previous text; they will not be repeated here.

[0078] In the application of electric vehicle controller interface chips, the drive circuit 104 in each channel module 01 can adaptively adjust the gate voltage of the NMOS switch 103 according to the source voltage of the NMOS switch 103, and control the gate-source voltage difference Vgs of the NMOS switch 103 within a fixed value or a fixed range. This not only avoids the problem that the gate-source voltage difference Vgs of the NMOS switch 103 is too large and exceeds the safe operating voltage of the NMOS switch 103, thus damaging the NMOS switch 103, but also effectively avoids the problem that the impedance of the NMOS switch 103 in the channel module 01 is too large, resulting in slow signal establishment, increased power consumption loss of transmitted current signal, increased logic signal transmission delay, and the problem that the increased impedance of the general-purpose pin connected to the first port 101 will cause voltage distortion of the general-purpose pin when it is used as a power supply or ground port.

[0079] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0080] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand this application, and the content of this specification should not be construed as a limitation of this application. Furthermore, for those skilled in the art, there will be different forms of changes in the specific implementation methods and application scope based on this application. It is neither necessary nor possible to exhaustively list all implementation methods here, and obvious changes or modifications derived therefrom are still within the protection scope of this application.

Claims

1. A channel module, characterized in that, include: First port, low-voltage circuit, NMOS switch and drive circuit; The NMOS switch is a high-voltage transistor, and the NMOS switch is connected between the first port and the low-voltage circuit through its drain and source. The driving circuit is connected to the source and gate of the NMOS switch respectively. The driving circuit drives the NMOS switch to turn on or off according to the input control signal. When the NMOS switch is turned on, the gate voltage of the NMOS switch changes with its source voltage.

2. The channel module according to claim 1, characterized in that, The drive circuit includes a current output module and a clamping circuit; The current output module is used to output a first current under the power supply voltage of the first power supply. The clamping circuit is connected between the first voltage and the output terminal of the current output module; The clamping circuit is used to clamp the gate voltage of the NMOS switch to a second voltage so as to drive the NMOS switch to turn on when the control signal indicates that the NMOS switch should be turned on. The second voltage is greater than the first voltage, which is generated based on the source voltage of the NMOS switch.

3. The channel module according to claim 2, characterized in that, The driving circuit also includes a first switch and a first NMOS transistor; The first switch is controlled by the control signal, and the first switch is turned on when the control signal indicates that the NMOS switch is turned on; The gate of the first NMOS transistor is used to connect to the source voltage of the NMOS switch, the drain of the first NMOS transistor is connected to the second power supply voltage through the first switch, and the source of the first NMOS transistor is used to output the first voltage.

4. The channel module according to claim 3, characterized in that, The clamping circuit includes a clamping module. The first terminal of the clamping module is used to connect to the first voltage, and the second terminal is used to connect to the output terminal of the current output module. The second voltage is the voltage of the second terminal of the clamping module. Alternatively, the clamping circuit includes a clamping module and a voltage divider module, which are connected in parallel between the first voltage and the output terminal of the current output module, wherein the second voltage is the voltage divider node voltage of the voltage divider circuit.

5. The channel module according to claim 2, characterized in that, The clamping circuit includes a clamping module. The first terminal of the clamping module is used to connect to the first voltage, and the second terminal is used to connect to the output terminal of the current output module. The first voltage is the source voltage of the NMOS switch, and the second voltage is the voltage at the second terminal of the clamping module. Alternatively, the clamping circuit includes a clamping module and a voltage divider module, which are connected in parallel between the first voltage and the output terminal of the current output module. The first voltage is the source voltage of the NMOS switch, and the second voltage is the voltage divider node voltage of the voltage divider circuit.

6. The channel module according to claim 4 or 5, characterized in that, The clamping module is a Zener diode, the cathode of which is connected to the output terminal of the current output module, and the anode of which is used to connect to the first voltage.

7. The channel module according to claim 3, characterized in that, The driving circuit further includes a current limiting module, which is connected between the first voltage and ground.

8. The channel module according to claim 3, characterized in that, The second power supply voltage is less than the first power supply voltage.

9. The channel module according to any one of claims 1-3, characterized in that, The driving circuit further includes: a first switch and a second switch controlled by the control signal; The first switch is connected to the driving circuit, and the second switch is connected between the gate of the NMOS switch and ground; When the control signal instructs the NMOS switch to be turned on, the first switch is turned on and the second switch is turned off. When the control signal instructs the NMOS switch to be turned off, the first switch is turned off and the second switch is turned on.

10. The channel module according to claim 2 or 8, characterized in that, The current output module includes a first current mirror, a second current mirror, and a withstand voltage unit; The input branch of the first current mirror is used to receive the second current, the output branch of the first current mirror is connected to the input branch of the second current mirror via the withstand voltage unit, and the output branch of the second current mirror is used to output the first current. The second current mirror is connected to the first power supply voltage, and the first current mirror is grounded.

11. The channel module according to claim 10, characterized in that, The withstand voltage unit includes a second NMOS transistor; wherein the source of the second NMOS transistor is connected to the output branch of the first current mirror, the drain of the second NMOS transistor is connected to the input branch of the second current mirror, and the gate of the second NMOS transistor is controlled by the inverted signal of the control signal; Both the MOS transistor in the second current mirror and the second NMOS transistor are high-voltage transistors.

12. The channel module according to claim 1, characterized in that, The channel module also includes: multiple functional ports and a high-voltage detection circuit; The multiple functional ports are divided into high-voltage detection ports and multiple low-voltage ports, and the port types of the different low-voltage ports are different. The low-voltage circuit is connected between the NMOS switch and the plurality of low-voltage ports; The input terminal of the high-voltage detection circuit is connected between the first port and the NMOS switch, and is used to detect the voltage of the first port; the output terminal of the high-voltage detection circuit outputs a detection signal through the high-voltage detection port; wherein, the control signal is generated based on the detection signal.

13. An electric vehicle controller interface chip, characterized in that, include: Multiple general-purpose pins, which are used to provide input ports and / or output ports for functional signals connected to the electric vehicle controller; A channel module is configured for each general-purpose pin, wherein the channel module is as described in any one of claims 1-12, and the first port of the channel module is connected to the corresponding general-purpose pin.

14. The electric vehicle controller interface chip according to claim 13, characterized in that, The channel module also has multiple functional ports, each with a different port type. The interface chip also includes: Communication pins and multiple function pins are used to connect to components in the electric vehicle controller; The control module controls the general-purpose pin to connect to the target function pin via the target function port in the corresponding channel module, based on the configuration logic determined by one or more functional signals transmitted by the communication pin. Wherein, the target functional port is connected to the functional signal of the general-purpose pin, and the target functional pin is connected to the functional signal of the general-purpose pin.

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