Control circuit and chip for hall device

Abstract

The application discloses a control circuit and chip for a Hall device, which comprises a first, second, third, fourth and fifth switch group. The first switch group is connected with a first and second connection end and a reference voltage; the second switch group is connected with a third and fourth connection end and a reference voltage; the third switch group is connected with the second and fourth connection end, a first and second output end; the fourth switch group is connected with the first and third connection end, the first and second output end; and the fifth switch group is connected with the second and fourth connection end, the third and first connection end. According to the control circuit and chip for the Hall device, the Hall device, the reference voltage and the reference voltage and the latter circuit are switched in different stages to eliminate the offset voltage caused by the resistance mismatch of the Hall device. The fifth switch group is arranged to shorten the establishment time of the differential voltage output by the Hall device to the latter circuit in switching, thereby shortening the duration of different stages.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a control circuit and chip for Hall effect devices. Background Technology

[0002] like Figure 1 As shown, taking a 4-terminal Hall effect device as an example, the four equivalent resistances R1, R2, R3, and R4 between terminals A, B, C, and D of the Hall effect device are ideally the same, and the physical characteristics of each terminal of the Hall effect device are also consistent. When a positive reference voltage REF (V) is applied to terminal A and a 0V voltage is applied to the diagonal terminal C, the voltage difference between A and C generates a current as shown by the arrow. If there is no magnetic field at this time, the voltage at terminal B will be equal to the voltage at terminal D, which is equal to REF / 2 (V). If there is a magnetic field at this time, the Hall effect device will generate a differential voltage d between terminals B and D according to the magnetic field shown in the figure. The voltage at terminal B = REF / 2 + d (V), and the voltage at terminal D = REF / 2 - d (V). The value of d will increase as the magnetic field in the current direction increases, allowing the subsequent circuit to monitor d and thus monitor the magnitude of the magnetic field.

[0003] However, in actual Hall effect devices, R1, R2, R3, and R4 are not completely equal. When there is a mismatch in the resistance values ​​of R1, R2, R3, and R4, the voltages at terminals B and D will naturally be unequal when there is no magnetic field. This difference will be identified as a magnetic field signal by the subsequent circuit, and the subsequent circuit cannot distinguish between the offset voltage and the differential voltage generated by the actual magnetic field.

[0004] To address this output offset voltage, traditional 4-terminal Hall effect devices or more-terminal Hall effect devices employ a 2-phase or more-phase rotation method. This allows the subsequent circuitry to separate the output offset voltage from the differential voltage generated by the magnetic field, enabling the subsequent circuitry to eliminate the offset voltage and leave only the differential voltage generated by the magnetic field.

[0005] like Figure 2 and Figure 3 As shown, taking a two-phase rotating configuration as an example:

[0006] The two phases are the first stage PH1 and the second stage PH2, which alternate. The first control signal L1, the fourth connection terminal D, the third control signal H1, and the fourth control signal H2 are the control signals for the switches. A high level controls the switch to close, and a low level controls the switch to open. The first control signal L1 controls switches swL1 and swL3, the second control signal L2 controls switches swL2 and swL4, the third control signal H1 controls switches swH1 and swH2, and the fourth control signal H2 controls switches swH3 and swH4.

[0007] The reference voltage REF is the power supply voltage of the Hall device, the reference voltage AGND is 0 potential, there is a voltage difference REF (V) between the reference voltage REF and the reference voltage AGND, and the first output terminal VOP and the second output terminal VON are the outputs of the Hall device to the subsequent circuit.

[0008] Process description:

[0009] Phase PH2: At time t1, Phase PH2 begins. The third control signal H1 and the first control signal L1 are pulled low, thereby disconnecting switches swL1, swL3, swH1, and swH2. Terminal A is disconnected from the reference voltage REF, terminal C is disconnected from the reference voltage AGND, terminal B is disconnected from the first output terminal VOP, and terminal D is disconnected from the second output terminal VON. The second control signal L2 is then pulled high, thereby closing switches swL2 and swL4. The reference voltage REF is connected to terminal B, and the reference voltage AGND is connected to terminal D.

[0010] During the second stage PH2, terminals A and C of the Hall device will be transmitted as outputs to the subsequent circuit. Since terminals A and C are connected to the reference voltage REF and the reference voltage AGND before t1, and since terminals A and C have an equivalent capacitance Cpar to the reference voltage AGND, it takes a certain amount of time for the difference between terminals A and C to reach a stable value through the RC network.

[0011] like Figure 4 As shown: The AC terminal needs to establish a relatively stable value before transmitting to the subsequent circuit. At time t3, the fourth control signal H2 goes high, and control switches swH3 and swH4 close. Terminal A is connected to the first output terminal VOP, and terminal C is connected to the second output terminal VON. Therefore, before time t3, the difference between terminals A and C needs to reach a relatively stable value. Assuming the stable difference between terminals A and C is the difference generated by the current magnetic field, 2×d (V), the stable value of terminal A is REF / 2-d (V), and the stable value of terminal C is REF / 2+d (V), it is generally desirable for the difference to establish to 90% of 2×d (V) before transmission, meaning an establishment error of 10%×2×d (V). If the difference between terminals A and C is not stable before being transmitted to the subsequent circuit, the magnetic field input signal received by the subsequent circuit will have a large deviation over a period of time, affecting the transient behavior of the subsequent circuit.

[0012] The step voltage between the difference between terminals A and C at time t1 and the ideal stable value after time t1 is Vx1 = REF + 2d (V). Let the resistance of the equivalent resistors R1, R2, R3, and R4 be Rhall, and let the equivalent parasitic capacitances to ground at terminals A, B, C, and D be Cpar. Then, in the RC network, R is Rhall / 2, C is Cpar, and the time constant τ1 = R × C = Rhall × Cpar / 2. The establishment error of the difference between terminals A and C is Vx1 × e^(-x1 × τ1) = 10% × 2 × d (V), where x1 × τ1 represents the time required to reach the establishment error of 10% × 2 × d (V).

[0013] like Figure 3 and Figure 2 As shown, in the first stage PH1: at time t4, the system enters the first stage PH1. The fourth control signal H2 and the second control signal L2 are pulled low, and control switches swL2, swL4, swH3, and swH4 are disconnected. Terminal B is disconnected from the reference voltage REF, terminal D is disconnected from the reference voltage AGND, terminal A is disconnected from the first output terminal VOP, and terminal C is disconnected from the second output terminal VON. The first control signal L1 is pulled high, and control switches swL1 and swL3 are closed. The reference voltage REF is connected to terminal A, and the reference voltage AGND is connected to terminal C. Figure 3 , 5 As shown in Figure 2, during the first stage PH1, at time t6, the third control signal H1 is pulled high, and the control switches swH1 and swH2 are closed. Terminal B is connected to the first output terminal VOP, and terminal D is connected to the second output terminal VON. Therefore, terminals B and D of the Hall device will be transmitted to the subsequent circuit as outputs. However, before time t4, terminal B is connected to the reference voltage REF, and terminal D is connected to the reference voltage AGND. Terminals B and D have an equivalent parasitic capacitance Cpar to the reference voltage AGND. Therefore, it takes a certain amount of time for the difference between terminals B and D to be established to a stable value through the RC network.

[0014] The current magnetic field generates a difference of 2×d (V). The stable value at terminal B is REF / 2+d (V), and the stable value at terminal D is REF / 2-d (V). The difference between terminals B and D needs to reach a relatively stable value before being transmitted to the subsequent circuit. The step voltage between the difference between terminals B and D at time t4 and the ideal stable value after time t4 is Vx2=REF-2d (V). Therefore, the establishment error of the difference between terminals B and D is Vx2×e^(-x2×τ1)=10%×2×d (V), where x2×τ1 represents the time required to reach the establishment error of 10%×2×d (V). Since d (V) is usually within 10mV and much smaller than the reference voltage REF, the differences between Vx2 and Vx1, and between x2×τ1 and x1×τ1, are very small. It can be assumed that the establishment times required for PH1 and PH2 are the same.

[0015] Traditional disadvantages:

[0016] Since the reference voltage REF level is typically around 1V or higher, higher REF, Rhall, and Cpar levels require long time intervals between t1 and t3, and between t4 and t6. This increases the duration of the first stage PH1 and the second stage PH2, reduces the system sampling frequency, and decreases the overall system bandwidth that can handle magnetic field signals.

[0017] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0018] The purpose of this invention is to provide a control circuit and chip for Hall effect devices that can shorten the duration of each stage.

[0019] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: a control circuit for a Hall effect device, wherein the Hall effect device has at least a first connection terminal, a second connection terminal, a third connection terminal, and a fourth connection terminal; the control circuit includes: a first switch group, a second switch group, a third switch group, a fourth switch group, and a fifth switch group; the first switch group is connected to the first connection terminal, the second connection terminal, and a reference voltage to control the on / off state between the first connection terminal and the reference voltage and between the second connection terminal and the reference voltage based on corresponding control signals; the second switch group is connected to the third connection terminal, the fourth connection terminal, and a reference voltage to control the on / off state between the third connection terminal and the reference voltage and between the fourth connection terminal and the reference voltage based on corresponding control signals; the third... A switch group is connected to a second connection terminal, a first output terminal, a fourth connection terminal, and a second output terminal to control the on / off state between the second connection terminal and the first output terminal and between the fourth connection terminal and the second output terminal based on corresponding switch control signals. The first output terminal and the second output terminal are also used to connect to subsequent circuits. The fourth switch group is connected to a first connection terminal, a first output terminal, a third connection terminal, and a second output terminal to control the on / off state between the third connection terminal and the second output terminal and between the first connection terminal and the first output terminal based on corresponding control signals. The fifth switch group is connected to a second connection terminal, a fourth connection terminal, a third connection terminal, and a first connection terminal to control the on / off state between the second connection terminal and the fourth connection terminal and between the third connection terminal and the first connection terminal based on corresponding control signals.

[0020] In one or more embodiments of the present invention, the first switch group includes a first switch and a second switch. A first terminal of the first switch is connected to a reference voltage, and a second terminal of the first switch is connected to a first connection terminal. A first terminal of the second switch is connected to a reference voltage, and a second terminal of the second switch is connected to a second connection terminal. The control terminal of the first switch is used to receive a first control signal, and the control terminal of the second switch is used to receive a second control signal.

[0021] In one or more embodiments of the present invention, the second switch group includes a third switch and a fourth switch. The second terminal of the third switch is connected to a third connection terminal, and the first terminal of the third switch is connected to a reference voltage. The second terminal of the fourth switch is connected to a fourth connection terminal, and the first terminal of the fourth switch is connected to a reference voltage. The control terminal of the third switch is used to receive a first control signal, and the control terminal of the fourth switch is used to receive a second control signal.

[0022] In one or more embodiments of the present invention, the first control signal and the second control signal are a set of inverse control signals.

[0023] In one or more embodiments of the present invention, the third switch group includes a fifth switch and a sixth switch. The second end of the fifth switch is connected to a second connection end, the first end of the fifth switch is connected to a first output end, the first end of the sixth switch is connected to a fourth connection end, the second end of the sixth switch is connected to a second output end, and the control ends of the fifth switch and the sixth switch are used to receive a third control signal.

[0024] In one or more embodiments of the present invention, the fourth switch group includes a seventh switch and an eighth switch. The first end of the seventh switch is connected to a third connection end, the second end of the seventh switch is connected to a second output end, the second end of the eighth switch is connected to a first connection end, and the first end of the eighth switch is connected to a first output end. The control ends of the seventh switch and the eighth switch are used to receive a fourth control signal.

[0025] In one or more embodiments of the present invention, the fifth switch group includes a ninth switch and a tenth switch. The first end of the ninth switch is connected to a second connection end, the second end of the ninth switch is connected to a fourth connection end, the first end of the tenth switch is connected to a third connection end, and the second end of the tenth switch is connected to a first connection end. The control end of the ninth switch is used to receive a fifth control signal, and the control end of the tenth switch is used to receive a sixth control signal.

[0026] In one or more embodiments of the present invention, the first switch group and the second switch group are used to control the first connection terminal to be connected to the reference voltage and the third connection terminal to be connected to the reference voltage in a first stage based on corresponding control signals, and to control the second connection terminal to be connected to the reference voltage and the fourth connection terminal to be connected to the reference voltage in a second stage based on corresponding control signals. The third switch group is used to control the second connection terminal to be connected to the first output terminal and the fourth connection terminal to the second output terminal after the first connection terminal and the third connection terminal to the reference voltage are connected in the first stage based on corresponding control signals. The fourth switch group is used to control the third connection terminal to be connected to the second output terminal and the first connection terminal to the first output terminal after the second connection terminal and the fourth connection terminal to the reference voltage are connected in the second stage based on corresponding control signals.

[0027] In one or more embodiments of the present invention, the fifth switch group is used to control the second connection terminal and the fourth connection terminal to be connected in the first stage based on a corresponding control signal, and to control the second connection terminal and the fourth connection terminal to be disconnected before the second connection terminal is connected to the first output terminal and the fourth connection terminal is connected to the second output terminal. The fifth switch group is also used to control the third connection terminal to be connected to the first connection terminal in the second stage based on a corresponding control signal, and to control the third connection terminal to be disconnected from the first connection terminal before the third connection terminal is connected to the second output terminal and the first connection terminal is connected to the first output terminal.

[0028] This invention discloses a chip, including the control circuit for the Hall device.

[0029] Compared with the prior art, the control circuit and chip for Hall devices of the present invention switch the Hall device with the reference voltage, reference voltage and subsequent circuits at different stages by rotating the first switch group, the second switch group, the third switch group and the fourth switch group in a phase rotation manner to eliminate the offset voltage caused by the resistance mismatch of the Hall device. By setting the fifth switch group, the establishment time of the differential voltage output by the Hall device to the subsequent circuit can be shortened during switching, thereby shortening the duration of different stages and accelerating the switching frequency of different stages.

[0030] When subsequent circuits need to switch clock signals of the same frequency at different stages to process the Hall device output offset voltage and Hall magnetic field differential output, the clock signal frequency of the subsequent circuits is increased accordingly. The increased overall system clock frequency speeds up the processing of the Hall device output offset voltage during initial power-up (e.g., the clock of the integrating operational amplifier), thereby accelerating the rapid processing of the actual magnetic field quantity after initial power-up. This results in a faster output of an analog signal representing the accurate magnetic field quantity, or a faster and more accurate threshold judgment of the current magnetic field magnitude.

[0031] Different switching frequencies represent the sampling frequency of the overall system, thus increasing the bandwidth of magnetic field signals that the overall system can process. For rapidly changing magnetic field signals, the system can sample the changes in the magnetic field more quickly and process them. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a circuit diagram of a Hall effect device in the prior art.

[0034] Figure 2 This is a circuit diagram of a control circuit for a Hall effect device in the prior art.

[0035] Figure 3 This is a waveform diagram of the control signal used in the control circuit for Hall effect devices in the prior art.

[0036] Figure 4 This is a waveform diagram of the A and C terminals of a control circuit used for Hall effect devices in the prior art.

[0037] Figure 5 This is a waveform diagram of the B and D terminals of a control circuit used for Hall effect devices in the prior art.

[0038] Figure 6 This is a circuit diagram of a control circuit for a Hall device according to an embodiment of the present invention.

[0039] Figure 7 This is a control signal waveform diagram of a control circuit for a Hall device according to an embodiment of the present invention.

[0040] Figure 8 This is a signal waveform diagram of the first and third connection terminals of the control circuit for the Hall device in one embodiment of the present invention.

[0041] Figure 9 This is a signal waveform diagram of the second and fourth connection terminals of the control circuit for the Hall device in one embodiment of the present invention. Detailed Implementation

[0042] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0043] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0044] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0045] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0046] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0047] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0048] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0049] According to one embodiment of the present invention, a control circuit for a Hall device is provided, wherein the Hall device includes a plurality of resistor units, each resistor unit is connected in sequence to form a closed loop, and two resistor units form a connection terminal. The resistor units are arranged symmetrically, and the connection terminals are arranged symmetrically.

[0050] like Figure 1 As shown, taking a four-terminal Hall effect device formed by four resistor units R1, R2, R3, and R4 as an example, the four resistor units R1, R2, R3, and R4 connected in a closed loop are symmetrically arranged and symmetrically formed with a first connection terminal A, a second connection terminal B, a third connection terminal C, and a fourth connection terminal D. The resistor units can be different circuit structures and obtained through equivalence. In other embodiments, the number of resistor units can exceed four.

[0051] like Figure 6 As shown, the control circuit includes a first switch group, a second switch group, a third switch group, a fourth switch group, and a fifth switch group. The first switch group is connected to a first connection terminal A, a second connection terminal B, and a reference voltage REF to control the on / off state between the first connection terminal A and the reference voltage REF based on a first control signal L1, and to control the on / off state between the second connection terminal B and the reference voltage REF based on a second control signal L2. In one embodiment, the first control signal L1 and the second control signal L2 are a set of inverted control signals.

[0052] The second switch group is connected to the third connection terminal C, the fourth connection terminal D, and the reference voltage to control the on / off state between the third connection terminal C and the reference voltage AGND based on the first control signal L1, and to control the on / off state between the fourth connection terminal D and the reference voltage AGND based on the second control signal L2. In one embodiment, the reference voltage AGND is ground voltage or other voltage.

[0053] The third switch group is connected to the second connection terminal B, the first output terminal VOP, the fourth connection terminal D, and the second output terminal VON to control the on / off state between the second connection terminal B and the first output terminal VOP and between the fourth connection terminal D and the second output terminal VON based on the third control signal H1. The first output terminal VOP and the second output terminal VON are also used to connect to the subsequent circuit.

[0054] The fourth switch group is connected to the first connection terminal A, the first output terminal VOP, the third connection terminal C, and the second output terminal VON to control the on / off state between the third connection terminal C and the second output terminal VON, and between the first connection terminal A and the first output terminal VOP, based on the fourth control signal H2. In one embodiment, the third control signal H1 and the fourth control signal H2 will not be high at the same time.

[0055] The fifth switch group is connected to the second connection terminal B, the fourth connection terminal D, the third connection terminal C and the first connection terminal A to control the on / off state between the second connection terminal B and the fourth connection terminal D based on the fifth control signal S1 and to control the on / off state between the third connection terminal C and the first connection terminal A based on the sixth control signal S2.

[0056] The first switch group and the second switch group are used to control the first connection terminal A to be connected to the reference voltage REF and the third connection terminal C to be connected to the reference voltage AGND in the first stage PH1 based on the first control signal L1, and to control the second connection terminal B to be connected to the reference voltage REF and the fourth connection terminal D to be connected to the reference voltage AGND in the second stage PH2.

[0057] The third switch group is used to control the second connection terminal B to connect to the first output terminal VOP and the fourth connection terminal D to connect to the second output terminal VON after the first connection terminal A of PH1 is connected to the reference voltage REF and the third connection terminal C is connected to the reference voltage AGND in the first stage, based on the third control signal H1.

[0058] The fourth switch group is used to control the third connection terminal C to connect to the second output terminal VON and the first connection terminal A to the first output terminal VOP after the second connection terminal B of PH2 is connected to the reference voltage REF and the fourth connection terminal D is connected to the reference voltage AGND in the second stage, based on the fourth control signal H2.

[0059] The fifth switch group is used to control the second connection terminal B and the fourth connection terminal to connect in the first stage PH1 based on the fifth control signal S1, and to control the second connection terminal B and the fourth connection terminal D to disconnect before the second connection terminal B connects to the first output terminal VOP and the fourth connection terminal D connects to the second output terminal VON; the fifth switch group is used to control the third connection terminal C to connect to the first connection terminal A in the second stage PH2 based on the sixth control signal S2, and to control the third connection terminal C to disconnect from the first connection terminal A before the third connection terminal C connects to the second output terminal VON and the first connection terminal A connects to the first output terminal VOP.

[0060] like Figure 6As shown, the first switch group includes a first switch swL1 and a second switch swL2. The first terminal of the first switch swL1 is connected to the reference voltage REF, and the second terminal of the first switch swL1 is connected to the first connection terminal A. The first terminal of the second switch swL2 is connected to the reference voltage REF, and the second terminal of the second switch swL2 is connected to the second connection terminal B. The control terminal of the first switch swL1 is used to receive a first control signal L1, and the control terminal of the second switch swL2 is used to receive a second control signal L2.

[0061] like Figure 6 As shown, the second switch group includes a third switch swL3 and a fourth switch swL4. The second terminal of the third switch swL3 is connected to the third connection terminal C, and the first terminal of the third switch swL3 is connected to the reference voltage AGND. The second terminal of the fourth switch swL4 is connected to the fourth connection terminal D, and the first terminal of the fourth switch swL4 is connected to the reference voltage AGND. The control terminal of the third switch swL3 is connected to the first control signal L1, and the control terminal of the fourth switch swL4 is connected to the second control signal L2.

[0062] like Figure 6 As shown, the third switch group includes a fifth switch swH1 and a sixth switch swH2. The second end of the fifth switch swH1 is connected to the second connection terminal B, and the first end of the fifth switch swH1 is connected to the first output terminal VOP. The first end of the sixth switch swH2 is connected to the fourth connection terminal D, and the second end of the sixth switch swH2 is connected to the second output terminal VON. The control terminals of the fifth switch swH1 and the sixth switch swH2 are used to receive the third control signal H1.

[0063] like Figure 6 As shown, the fourth switch group includes a seventh switch swH3 and an eighth switch swH4. The first end of the seventh switch swH3 is connected to the third connection terminal C, and the second end of the seventh switch swH3 is connected to the second output terminal VON. The second end of the eighth switch swH4 is connected to the first connection terminal A, and the first end of the eighth switch swH4 is connected to the first output terminal VOP. The control terminals of the seventh switch swH3 and the eighth switch swH4 are used to receive the fourth control signal H2.

[0064] like Figure 6 As shown, the fifth switch group includes a ninth switch swS1 and a tenth switch swS2. The first end of the ninth switch swS1 is connected to the second connection end B, and the second end of the ninth switch swS1 is connected to the fourth connection end D. The first end of the tenth switch swS2 is connected to the third connection end C, and the second end of the tenth switch swS2 is connected to the first connection end A. The control end of the ninth switch swS1 is used to receive the fifth control signal S1, and the control end of the tenth switch swS2 is used to receive the sixth control signal S2.

[0065] As Figure 7 shown, the second phase PH2: the second phase PH2 is entered after the end of time t1, the third control signal H1 and the first control signal L1 are pulled low, the first control signal L1 controls the first switch swL1 and the third switch swL3 to be turned off, the third control signal H1 controls the fifth switch swH1 and the sixth switch swH2 to be turned off, the first connection terminal A is disconnected from the reference voltage REF, the third connection terminal C is disconnected from the reference voltage AGND, the second connection terminal B is disconnected from the first output terminal VOP, and the fourth connection terminal D is disconnected from the second output terminal VON; the second control signal L2 is pulled high, the second control signal L2 controls the second switch swL2 and the fourth switch swL4 to be closed, the reference voltage REF is communicated with the second connection terminal B, and the fourth connection terminal D is communicated with the reference voltage AGND. Different from the conventional method, at time t1, the sixth control signal S2 is pulled high, the tenth switch swS2 is closed, the first connection terminal A is communicated with the third connection terminal C, at this time, the R in R×C established by the RC network is the on-resistance Ron of the tenth switch swS2, RhAll (resistance values of R1, R2, R3, R4) is usually at kΩ level, while Ron can be only tens of ohms or smaller, and Ron<<RhAll / 2, which can help the first connection terminal A and the third connection terminal C to quickly reach a stable value of REF / 2. In this case, from the perspective of the Hall element structure, the stable voltage of the first connection terminal A and the third connection terminal C is REF / 2. At time t2, the voltage of the first connection terminal A and the third connection terminal C is substantially equal to REF / 2, the sixth control signal S2 is pulled low, the tenth switch swS2 is turned off, and the fast establishment channel is closed. At this time, the R in R×C established by the RC network becomes RhAll / 2 again, and the first connection terminal A and the third connection terminal C are respectively established from REF / 2 to: the stable value of the first connection terminal A is the reference voltage REF / 2-d (V), the stable value of the third connection terminal C is the reference voltage REF / 2+d (V), therefore, the step voltage of (the difference between the first connection terminal A and the third connection terminal C) between the value at time t2 and the ideal stable value after time t2 is Vy1=2d (V). Then the establishment error of the difference between the first connection terminal A and the third connection terminal C is Vy1×e^(-y1×τ1)=10%×2× d (V), where y1×τ1 represents the time required to reach the establishment error of 10%×2×d (V).

[0066] Compared to the traditional method, the settling time is Vx1×e^(-x1×τ1)=10%×2×d(V), where Vx1=REF+2d(V). The d(V) generated by the Hall effect device due to the magnetic field is typically only on the order of 10mV, therefore the reference voltage REF is much larger than d(V). It is evident that the settling time y1×τ1 of this scheme is much shorter than x1×τ1 of the traditional method, shortening the time interval between t1 and t3. At t3, the fourth control signal H2 goes high, the seventh switch swH3 and the eighth switch swH4 close, the first connection terminal A is connected to the first output terminal VOP, and the third connection terminal C is connected to the second output terminal VON. From... Figure 8 It is evident that the time it takes for the difference between the first connection terminal A and the third connection terminal C to reach a stable value is significantly shorter compared to the traditional scheme.

[0067] First phase PH1: the circuit ends at time t4 and enters the first phase PH1. The fourth control signal H2 and the second control signal L2 are pulled low, to control the second switch swL2, the fourth switch swL4, the seventh switch swH3 and the eighth switch swH4 to turn off. The second connection terminal B is disconnected from the reference voltage REF, the fourth connection terminal D is disconnected from the reference voltage AGND, the first connection terminal A is disconnected from the first output terminal VOP, and the third connection terminal C is disconnected from the first output terminal VON. The first control signal L1 is pulled high to control the first switch swL1 and the third switch swL3 to close, the reference voltage REF is communicated with the first connection terminal A, and the reference voltage AGND is communicated with the third connection terminal C. The difference from the conventional method is that at time t4, the fifth control signal S1 is pulled high to control the ninth switch swS1 to close, and the second connection terminal B is connected with the fourth connection terminal D. At this time, the R in the R×C established by the RC network is the on-resistance Ron of the ninth switch swS1. Rhall is usually at the kiloohm level, while Ron can only be tens of ohms or smaller, and Ron<<Rhall / 2, which can help the voltages of the second connection terminal B and the fourth connection terminal D quickly settle to REF / 2. In this case, from the perspective of the Hall element structure, the stable voltages of the second connection terminal B and the fourth connection terminal D are REF / 2. At time t5, the voltages of the second connection terminal B and the fourth connection terminal D are substantially equal to REF / 2, the fifth control signal S1 is pulled low, the ninth switch swS1 is turned off, and the fast settling channel is closed. At this time, the R in the R×C established by the RC network becomes Rhall / 2 again, and the voltages of the second connection terminal B and the fourth connection terminal D are settled from REF / 2 respectively to: the stable value of the second connection terminal B is REF / 2+dV, and the stable value of the fourth connection terminal D is REF / 2-dV. Therefore, the step voltage of (the difference between the second connection terminal B and the fourth connection terminal D) between the value at time t5 and the ideal stable value after time t5 is Vx2=2d(V). The settling error of the difference between the second connection terminal B and the fourth connection terminal D is Vy2×e^(-y2×τ1)=10%×2×dV, where y2×τ1 represents the time required to reach the settling error of 10%×2×d(V).

[0068] Compared with the settling time Vx2×e^(-x2×τ1)=10%×2×d(V) of the conventional method, where Vx2=REF-2d(V), d(V) generated by the Hall device due to the magnetic field is usually only at the 10mV level, so REF is much larger than d(V). It can be seen that the settling time y2×τ1 of the present solution is much smaller than the settling time x2×τ1 of the conventional method, which shortens the time interval from time t4 to time t6. At time t6, the third control signal H1 is pulled high, the fifth switch swH1 and the sixth switch swH2 are closed, the second connection terminal B is connected to the first output terminal VOP, and the fourth connection terminal D is connected to the second output terminal VON. From Figure 9It is evident that the time it takes for the difference between the second connection terminal B and the fourth connection terminal D to reach a stable value is significantly shorter compared to the traditional scheme.

[0069] Since REF is much larger than d(V), the traditional method has Vx1≈Vx2, x1×τ1≈x2×τ1; the improved method has Vy1≈Vy2, y1×τ1≈y2×τ1. Therefore, the differential output setup times of the first stage PH1 and the second stage PH2 in the traditional method can be considered to be the same, and the differential output setup times of the first stage PH1 and the second stage PH2 in the improved method can also be considered to be the same.

[0070] In one embodiment, the first control signal L1, the second control signal L2, the third control signal H1, the fourth control signal H2, the fifth control signal S1, and the sixth control signal S2 can be generated by corresponding signal generation circuits. The structural design of the signal generation circuits can satisfy the timing requirements between the first control signal L1, the second control signal L2, the third control signal H1, the fourth control signal H2, the fifth control signal S1, and the sixth control signal S2.

[0071] The present invention also discloses a chip including the control circuit for Hall devices described above.

[0072] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0073] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A control circuit for a Hall effect device, characterized in that, The Hall effect device has at least a first connection terminal, a second connection terminal, a third connection terminal, and a fourth connection terminal. The control circuit includes a first switch group, a second switch group, a third switch group, a fourth switch group, and a fifth switch group. The first switch group is connected to the first connection terminal, the second connection terminal, and a reference voltage to control the on / off state between the first connection terminal and the reference voltage and between the second connection terminal and the reference voltage based on corresponding control signals. The second switch group is connected to the third connection terminal, the fourth connection terminal, and a reference voltage to control the on / off state between the third connection terminal and the reference voltage and between the fourth connection terminal and the reference voltage based on corresponding control signals. The third switch group is connected to the second connection terminal, the first output terminal, and the fourth connection terminal. The circuit is connected to a second output terminal to control the connection and disconnection between the second connection terminal and the first output terminal and between the fourth connection terminal and the second output terminal based on corresponding switch control signals. The first output terminal and the second output terminal are also used to connect to the subsequent circuit. The fourth switch group is connected to the first connection terminal, the first output terminal, the third connection terminal and the second output terminal to control the connection and disconnection between the third connection terminal and the second output terminal and between the first connection terminal and the first output terminal based on corresponding control signals. The fifth switch group is connected to the second connection terminal, the fourth connection terminal, the third connection terminal and the first connection terminal to control the connection and disconnection between the second connection terminal and the fourth connection terminal and between the third connection terminal and the first connection terminal based on corresponding control signals.

2. The control circuit for a Hall effect device according to claim 1, characterized in that, The first switch group includes a first switch and a second switch. The first terminal of the first switch is connected to a reference voltage, and the second terminal of the first switch is connected to a first connection terminal. The first terminal of the second switch is connected to a reference voltage, and the second terminal of the second switch is connected to a second connection terminal. The control terminal of the first switch is used to receive a first control signal, and the control terminal of the second switch is used to receive a second control signal.

3. The control circuit for a Hall effect device according to claim 1, characterized in that, The second switch group includes a third switch and a fourth switch. The second terminal of the third switch is connected to a third connection terminal, and the first terminal of the third switch is connected to a reference voltage. The second terminal of the fourth switch is connected to a fourth connection terminal, and the first terminal of the fourth switch is connected to a reference voltage. The control terminal of the third switch is used to receive a first control signal, and the control terminal of the fourth switch is used to receive a second control signal.

4. The control circuit for a Hall device according to claim 2 or 3, characterized in that, The first control signal and the second control signal are a set of inverse control signals.

5. The control circuit for a Hall effect device according to claim 1, characterized in that, The third switch group includes a fifth switch and a sixth switch. The second end of the fifth switch is connected to the second connection end, and the first end of the fifth switch is connected to the first output end. The first end of the sixth switch is connected to the fourth connection end, and the second end of the sixth switch is connected to the second output end. The control ends of the fifth switch and the sixth switch are used to receive a third control signal.

6. The control circuit for a Hall effect device according to claim 1, characterized in that, The fourth switch group includes a seventh switch and an eighth switch. The first end of the seventh switch is connected to the third connection end, the second end of the seventh switch is connected to the second output end, the second end of the eighth switch is connected to the first connection end, and the first end of the eighth switch is connected to the first output end. The control ends of the seventh switch and the eighth switch are used to receive the fourth control signal.

7. The control circuit for a Hall effect device according to claim 1, characterized in that, The fifth switch group includes a ninth switch and a tenth switch. The first end of the ninth switch is connected to the second connection end, the second end of the ninth switch is connected to the fourth connection end, the first end of the tenth switch is connected to the third connection end, and the second end of the tenth switch is connected to the first connection end. The control end of the ninth switch is used to receive a fifth control signal, and the control end of the tenth switch is used to receive a sixth control signal.

8. The control circuit for a Hall effect device according to claim 1, characterized in that, The first and second switch groups are used to control the first connection terminal to be connected to the reference voltage and the third connection terminal to the reference voltage in the first stage and to be connected to the reference voltage in the second stage based on corresponding control signals. The third switch group is used to control the second connection terminal to be connected to the first output terminal and the fourth connection terminal to the second output terminal after the first connection terminal and the third connection terminal to the reference voltage are connected in the first stage based on corresponding control signals. The fourth switch group is used to control the third connection terminal to be connected to the second output terminal and the first connection terminal to the first output terminal after the second connection terminal and the fourth connection terminal to the reference voltage are connected in the second stage based on corresponding control signals.

9. The control circuit for a Hall effect device according to claim 8, characterized in that, The fifth switch group is used to control the second connection terminal and the fourth connection terminal to connect in the first stage based on the corresponding control signal, and to control the second connection terminal and the fourth connection terminal to disconnect before the second connection terminal connects to the first output terminal and the fourth connection terminal connects to the second output terminal. The fifth switch group is also used to control the third connection terminal to connect to the first connection terminal in the second stage based on the corresponding control signal, and to control the third connection terminal to disconnect from the first connection terminal before the third connection terminal connects to the second output terminal and the first connection terminal connects to the first output terminal.

10. A chip, characterized in that, Includes the control circuit for Hall devices as described in any one of claims 1 to 9.

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