Clock generation circuit and phase-locked loop

Abstract

The utility model discloses a clock generating circuit, its characterized in that, including: frequency detection unit, current generating unit and flow control oscillation unit. Frequency detection unit is used for detecting the signal of pin end and produces a group of control signal, the pin end is used for receiving clock input signal or is connected with reference voltage through external resistance unit, current generating unit is used for receiving the first input signal or second input signal under the control of control signal to and produces corresponding output current based on the first input signal or second input signal, flow control oscillation unit is used for producing clock control signal based on output current. According to the clock generating circuit and phase-locked loop of the utility model, through the multiplexing of current generating unit, flow control oscillation module and other parts for generating clock control signal, further reduce the area of function realization, realize the compatibility of resistance frequency selection and frequency synchronous mode under single pin.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, specifically relating to a clock generation circuit and a phase-locked loop. Background Technology

[0002] In switching power supply chips, it is sometimes necessary to both select the switching clock frequency by the value of a resistor and synchronize with external input clocks of different frequencies to generate switching clock signals of different frequencies. Existing solutions typically use two different pins to implement the resistor-based frequency selection and frequency synchronization functions, which increases the area cost of implementing these functions.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a clock generation circuit and a phase-locked loop that can switch between resistor-selective frequency mode and frequency synchronization mode using only a single pin in a smaller area, thereby generating the required clock control signal.

[0005] To achieve the above objectives, a specific embodiment of this utility model provides the following technical solution: a clock generation circuit, comprising:

[0006] The frequency detection unit is used to detect the signal at the pin terminal and generate a set of control signals. The pin terminal is used to receive clock input signals or to be connected to a reference voltage through an external resistor unit.

[0007] A current generating unit is configured to receive a first input signal or a second input signal under the control of a control signal, and generate a corresponding output current based on the first input signal or the second input signal; and

[0008] A flow-controlled oscillation unit is used to generate a clock control signal based on the output current.

[0009] In one or more embodiments of the present invention, the current generating unit includes a first switching module and a current generating module. A first terminal of the first switching module is used to receive a first input signal, a second terminal of the first switching module is used to receive a second input signal, and a third terminal of the first switching module is connected to the input terminal of the current generating module. The first switching module is used to control the connection and disconnection between the first terminal of the first switching module and the input terminal of the current generating module based on a control signal, and to control the connection and disconnection between the second terminal of the first switching module and the input terminal of the current generating module.

[0010] In one or more embodiments of this utility model, the current generation module includes: a clamping transmission module and a conversion unit. The clamping transmission module is connected to the third terminal of the first switching module and the conversion unit. The conversion unit is also connected to the pin terminal. The clamping transmission module is used to copy the first input signal or the second input signal to the conversion unit to convert it into a corresponding current and to mirror the current to generate an output current. The conversion unit is used to switch under the control of a control signal to generate a corresponding current based on itself or an external resistor unit connected to the pin terminal.

[0011] In one or more embodiments of the present invention, the clamping transmission module includes: an amplifier, a first transistor and a current mirror, the first input terminal of the amplifier is connected to the third terminal of the first switching module, the second input terminal of the amplifier and the first terminal of the first transistor are connected to the conversion unit, the output terminal of the amplifier is connected to the control terminal of the first transistor, and the second terminal of the first transistor is connected to the current mirror.

[0012] In one or more embodiments of the present invention, the conversion unit includes a second switching module and a resistor unit. The first end of the second switching module is connected to a pin terminal, the second end of the second switching module is connected to the resistor unit, and the third end of the second switching module is connected to a clamping transmission module. The second switching module is used to control the connection and disconnection between the first end and the third end of the second switching module based on a control signal.

[0013] In one or more embodiments of the present invention, the first switching module includes a first switch and a second switch. The first end of the first switch is used to receive a first input signal. The second ends of the first switch and the second ends of the second switch are connected to the input end of the current generating module. The first end of the second switch is used to receive a second input signal. The first switch and the second switch are controlled to turn on or off based on a set of control signals.

[0014] In one or more embodiments of this utility model, the second switching module includes a third switch and a fourth switch. The first end of the third switch is connected to a pin terminal, the second ends of the third switch and the second ends of the fourth switch are connected to a clamping transmission module, and the first end of the fourth switch is connected to a resistor unit.

[0015] In one or more embodiments of this utility model, the flow-controlled oscillation module includes a charging / discharging unit, a comparator, and a control unit. The charging / discharging unit is connected to a current generating unit to generate a voltage signal based on the output current. The first input terminal of the comparator is connected to the charging / discharging unit to receive the voltage signal, and the second input terminal of the comparator is connected to a reference voltage. The comparator is used to compare the voltage signal with the reference voltage to generate a result signal. The control unit is connected to the comparator to generate a clock control signal and a charging / discharging control signal based on the result signal. The charging / discharging unit is connected to the control unit to perform charging and discharging based on the control of the charging / discharging control signal.

[0016] In one or more embodiments of this utility model, the charging and discharging unit includes a capacitor and a fifth switch. The first end of the capacitor and the first end of the fifth switch are connected to a current generating unit to receive the output current. The second end of the capacitor and the second end of the fifth switch are connected to a reference voltage. The fifth switch is connected to a control unit to control the opening or closing based on a charging and discharging control signal.

[0017] This embodiment also discloses a phase-locked loop, including: the clock generation circuit, the phase-locked loop further including a frequency and phase detector, a charge pump and a loop filter connected in sequence, the frequency and phase detector being connected to a pin terminal to receive the signal from the pin terminal, the frequency and phase detector being connected to a current-controlled oscillation unit to receive a clock control signal, the output terminal of the loop filter being connected to the clock generation circuit, and the second input signal being the clock output signal output by the loop filter.

[0018] Compared with the prior art, the clock generation circuit and phase-locked loop of this invention further reduce the area of ​​the function implementation by reusing the current generation unit, current-controlled oscillation module and other parts used to generate clock control signals, and achieves compatibility of resistor frequency selection and frequency synchronization mode under a single pin. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a circuit diagram of the clock generation circuit and phase-locked loop in one embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0022] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0023] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0024] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0025] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0026] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0027] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0028] like Figure 1 As shown, a clock generation circuit in one embodiment of the present invention includes: a frequency detection unit 10, a current generation unit 20, and a current-controlled oscillation unit 30.

[0029] The frequency detection unit 10 is used to detect the signal at the FREQ_SEL pin and generate a set of control signals SYNC_EN and SYNC_ENB. The set of control signals SYNC_EN and SYNC_ENB are inverted signals. The FREQ_SEL pin is used to receive the clock input signal CLK_IN or is connected to the reference voltage through the external resistor unit RSEL. In one embodiment, the reference voltage is the ground voltage.

[0030] The current generation unit 20 is used to receive the first input signal or the second input signal under the control of the control signals SYNC_EN and SYNC_ENB, and generate a corresponding output current based on the first input signal or the second input signal; the current-controlled oscillation unit 30 is used to generate a clock control signal CLK_OUT based on the output current.

[0031] The current generating unit 20 includes a first switching module 21 and a current generating module. A first terminal of the first switching module 21 receives a first input signal VREF_RES, a second terminal receives a second input signal VLPF, and a third terminal is connected to the input terminal of the current generating module. The first switching module 21 is used to control the connection and disconnection between its first terminal and the input terminal of the current generating module, and also to control the connection and disconnection between its second terminal and the input terminal of the current generating module, based on control signals SYNC_EN and SYNC_ENB.

[0032] like Figure 1 As shown, the first switching module 21 includes a first switch SW1 and a second switch SW2. The first terminal of the first switch SW1 is used to receive the first input signal VREF_RES. The second terminal of the first switch SW1 and the second terminal of the second switch SW2 are connected to the input terminal of the current generation module. The first terminal of the second switch SW2 is used to receive the second input signal VLPF. The first switch SW1 and the second switch SW2 are controlled to be turned on or off based on a set of control signals SYNC_EN and SYNC_ENB.

[0033] In one embodiment, the current generation module includes a clamping transmission module and a conversion unit. The clamping transmission module is connected to the third terminal of the first switching module 21 and the conversion unit, and the conversion unit is also connected to the FREQ_SEL pin. The clamping transmission module is used to copy the first input signal VREF_RES or the second input signal VLPF to the conversion unit to convert it into a corresponding current, and then mirror the current to generate an output current. The conversion unit is used to switch under the control of the control signals SYNC_EN and SYNC_ENB to generate a corresponding current based on itself or an external resistor unit RSEL connected to the FREQ_SEL pin.

[0034] like Figure 1 As shown, the clamping transmission module includes an amplifier AMP, a first transistor M1, and a current mirror. The first input terminal of the amplifier AMP is connected to the third terminal of the first switching module 21. The second input terminal of the amplifier AMP and the first terminal of the first transistor M1 are connected to the conversion unit. The output terminal of the amplifier AMP is connected to the control terminal of the first transistor M1, and the second terminal of the first transistor M1 is connected to the current mirror. In one embodiment, the first input terminal of the amplifier AMP is a positive input terminal, and the second input terminal of the amplifier AMP is a negative input terminal. In other embodiments, the second input terminal of the amplifier AMP is a positive input terminal, and the first input terminal of the amplifier AMP is a negative input terminal. In one embodiment, the current mirror includes a second transistor M2 and a third transistor M3. The second transistor M2 and the third transistor M3 mirror current at a ratio of M. The first terminals of the second transistor M2 and the third transistor M3 are connected to the power supply voltage AVCC. The control terminals of the second transistor M2 and the third transistor M3 are connected. The second terminal of the second transistor M2 is connected to the control terminal of the second transistor M2 and the second terminal of the first transistor M1. The second terminal of the third transistor M3 is used to generate the output current.

[0035] The first transistor M1 is an N-channel MOSFET, and the second transistor M2 and the third transistor M3 are P-channel MOSFETs. The first terminal of the first transistor M1, the first terminal of the second transistor M2, and the first terminal of the third transistor M3 are the sources; the second terminals of the first transistor M1, the second terminal of the second transistor M2, and the second terminal of the third transistor M3 are the drains; and the control terminals of the first transistor M1, the second transistor M2, and the third transistor M3 are the gates. In other embodiments, the first transistor M1 is a P-channel MOSFET, and the second transistor M2 and the third transistor M3 are N-channel MOSFETs.

[0036] like Figure 1As shown, the conversion unit includes a second switching module 22 and a resistor unit RSYNC. The first terminal of the second switching module 22 is connected to the FREQ_SEL pin, the second terminal of the second switching module 22 is connected to the first terminal of the resistor unit RSYNC, the second terminal of the resistor unit RSYNC is connected to a reference voltage, and the third terminal of the second switching module 22 is connected to a clamping transmission module. The second switching module 22 is used to control the connection and disconnection between the first and third terminals of the second switching module 22 based on the control signals SYNC_EN and SYNC_ENB.

[0037] In one embodiment, the second switching module 22 includes a third switch SW3 and a fourth switch SW4. The first end of the third switch SW3 is connected to the pin terminal FREQ_SEL. The second ends of the third switch SW3 and the second ends of the fourth switch SW4 are connected to the second input terminal of the amplifier AMP of the clamping transmission module. The first end of the fourth switch SW4 is connected to the resistor unit RSYNC.

[0038] like Figure 1 As shown, the current-controlled oscillation module includes a charging / discharging unit, a comparator CMP, and a control unit. The charging / discharging unit is connected to the current generation unit 20 to generate a voltage signal VOSC based on the output current. The first input terminal of the comparator CMP is connected to the output terminal of the charging / discharging unit and the current mirror to receive the voltage signal VOSC. The second input terminal of the comparator CMP is connected to the reference voltage VREF_OSC. The comparator CMP is used to compare the voltage signal VOSC with the reference voltage VREF_OSC to generate a result signal. The control unit is connected to the comparator CMP to generate a clock control signal CLK_OUT and a charging / discharging control signal RST based on the result signal. The charging / discharging unit is connected to the control unit to perform charging and discharging based on the control of the charging / discharging control signal RST.

[0039] In one embodiment, the charging and discharging unit includes a capacitor COSC and a fifth switch SW5. The first terminal of the capacitor COSC and the first terminal of the fifth switch SW5 are connected to the current mirror of the current generating unit 20 to receive the output current. The second terminal of the capacitor COSC and the second terminal of the fifth switch SW5 are connected to a reference voltage. The fifth switch SW5 is connected to a control unit to be turned on or off based on the control signal RST.

[0040] like Figure 1As shown, the clock generation circuit described above can be applied in a phase-locked loop (PLL) as the voltage-controlled oscillator (VCO) of the PLL. The PLL also includes a frequency and phase detector (PFD), a charge pump (CP), and a loop filter (LPF) connected in sequence. The first input terminal of the PFD is connected to the FREQ_SEL pin to receive the signal from the FREQ_SEL pin. The second input terminal of the PFD is connected to the current-controlled oscillator (CLO) unit 30 to receive the clock control signal CLK_OUT. The PFD generates a control voltage based on the error between the clock control signal CLK_OUT generated by the CLO and the clock input signal CLK_IN. The charge pump (CP) is connected to the PFD to adjust the magnitude of the control voltage. The input terminal of the loop filter (LPF) is connected to the charge pump (CP) to filter the control voltage, and the output terminal of the loop filter (LPF) is connected to the clock generation circuit. When the clock generation circuit is applied to the PLL, the second input signal VLP is the clock output signal from the loop filter (LPF), thus forming a loop. In other embodiments, the clock generation circuit described above can be applied to other circuit systems to provide clock control signals.

[0041] When the FREQ_SEL pin is connected to the external resistor RSEL, the frequency detection unit 10 detects that the signal frequency on the FREQ_SEL pin is lower than the set frequency, and generates a low-level first control signal SYNC_EN and a high-level first control signal SYNC_ENB, switching to the resistor frequency selection mode.

[0042] At this time, the second switch SW2 and the fourth switch SW4 are turned off, the first switch SW1 and the third switch SW3 are turned on, the first input terminal of the amplifier AMP of the control current generating unit 20 is connected to the first input signal voltage REF_RES (the first input signal voltage REF_RES is a reference signal), and the second input terminal of the amplifier AMP of the control current generating unit 20 is connected to the pin terminal FREQ_SEL.

[0043] The first reference current generated across the external resistor RSEL by amplifier AMP in conjunction with the first transistor M1 is:

[0044]

[0045] in, The resistance value of the external resistor RSEL is... The voltage value of the first reference voltage VREF_RES.

[0046] A current mirror replicates the first reference current at a multiple of M to generate the first output current, which charges the capacitor COSC, producing a voltage signal VOSC. A comparator CMP compares the voltage signal VOSC with the reference voltage VREF_OSC. When the voltage signal VOSC is greater than the reference voltage VREF_OSC, the comparator CMP generates a high-level result signal; otherwise, it generates a low-level result signal.

[0047] The control unit generates a high-level charge / discharge control signal RST with a duration on the order of nanoseconds based on the rising edge of the result signal. This signal turns on the fifth switch SW5, discharges the capacitor COSC, resets the voltage signal VOSC to 0, and then repeats the charging cycle. Simultaneously, the control unit also generates a clock control signal CLK_OUT with a frequency half that of the capacitor COSC charging frequency. It can be represented as:

[0048]

[0049] in, This is the capacitance value of the capacitor (COSC). The reference voltage VREF_OSC is the voltage value.

[0050] At this time, since the first input terminal of the current generation unit 20 is not connected to the loop filter LPF, the phase-locked loop composed of the current generation unit 20, the current-controlled oscillation module 30, and the frequency and phase discrimination module PFD is in an open-loop state and does not perform frequency synchronization on the signal at the pin terminal FREQ_SEL. By changing the value of the external resistor RSEL, clock control signals CLK_OUT of different frequencies can be generated.

[0051] When the FREQ_SEL pin is connected to the clock input signal CLK_IN, the frequency detection unit 10 detects that the signal frequency on the FREQ_SEL pin is higher than the set frequency, generates a high-level first control signal SYNC_EN and a low-level first control signal SYNC_ENB, and switches to frequency synchronization mode.

[0052] At this time, the first switch SW1 and the third switch SW3 are turned off, the second switch SW2 and the fourth switch SW4 are turned on, the first input terminal of the amplifier AMP of the control current generating unit 20 is connected to the output terminal of the loop filter LPF to receive the second input signal VLPF, and the second input terminal of the amplifier AMP of the control current generating unit 20 is connected to the resistor unit RSYNC.

[0053] The second reference current generated on the resistor module RSYNC by amplifier AMP in conjunction with the first transistor M1 is:

[0054]

[0055] in, The resistance value of the resistor module RSYNC. This is the filtered control voltage VLPF value.

[0056] Correspondingly, the frequency of the clock control signal CLK_OUT generated by the control unit at this time can be expressed as:

[0057]

[0058] At this time, the phase-locked loop is in closed-loop operation. The frequency and phase detector (PFD) module will synchronize the clock control signal CLK_OUT and the clock input signal CLK_IN, causing the magnitude of the second input signal VLPF to change. Ultimately, this makes the clock control signal CLK_OUT and the clock input signal CLK_IN have the same frequency, thus achieving frequency synchronization.

[0059]

[0060] This utility model also discloses a chip, including the above-mentioned clock generation circuit and / or phase-locked loop.

[0061] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0062] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A clock generation circuit, characterized in that, include: The frequency detection unit is used to detect the signal at the pin terminal and generate a set of control signals. The pin terminal is used to receive clock input signals or to be connected to a reference voltage through an external resistor unit. The current generating unit is used to receive a first input signal or a second input signal under the control of a control signal, and generate a corresponding output current based on the first input signal or the second input signal. as well as A flow-controlled oscillation unit is used to generate a clock control signal based on the output current.

2. The clock generation circuit according to claim 1, characterized in that, The current generating unit includes a first switching module and a current generating module. The first terminal of the first switching module is used to receive a first input signal, the second terminal of the first switching module is used to receive a second input signal, and the third terminal of the first switching module is connected to the input terminal of the current generating module. The first switching module is used to control the connection and disconnection between the first terminal of the first switching module and the input terminal of the current generating module based on a control signal, and to control the connection and disconnection between the second terminal of the first switching module and the input terminal of the current generating module.

3. The clock generation circuit according to claim 2, characterized in that, The current generation module includes a clamping transmission module and a conversion unit. The clamping transmission module is connected to the third terminal of the first switching module and the conversion unit. The conversion unit is also connected to the pin terminal. The clamping transmission module is used to copy the first input signal or the second input signal to the conversion unit to convert it into a corresponding current and mirror the current to generate an output current. The conversion unit is used to switch under the control of the control signal to generate a corresponding current based on itself or an external resistor unit connected to the pin terminal.

4. The clock generation circuit according to claim 3, characterized in that, The clamping transmission module includes an amplifier, a first transistor, and a current mirror. The first input terminal of the amplifier is connected to the third terminal of the first switching module. The second input terminal of the amplifier and the first terminal of the first transistor are connected to the conversion unit. The output terminal of the amplifier is connected to the control terminal of the first transistor. The second terminal of the first transistor is connected to the current mirror.

5. The clock generation circuit according to claim 3, characterized in that, The conversion unit includes a second switching module and a resistor unit. The first end of the second switching module is connected to a pin terminal, the second end of the second switching module is connected to the resistor unit, and the third end of the second switching module is connected to a clamping transmission module. The second switching module is used to control the connection and disconnection between the first end and the third end of the second switching module based on a control signal.

6. The clock generation circuit according to claim 2, characterized in that, The first switching module includes a first switch and a second switch. The first end of the first switch is used to receive a first input signal. The second ends of the first switch and the second ends of the second switch are connected to the input end of the current generating module. The first end of the second switch is used to receive a second input signal. The first switch and the second switch are controlled to turn on or off based on a set of control signals.

7. The clock generation circuit according to claim 5, characterized in that, The second switching module includes a third switch and a fourth switch. The first end of the third switch is connected to a pin terminal, the second ends of the third switch and the second ends of the fourth switch are connected to a clamping transmission module, and the first end of the fourth switch is connected to a resistor unit.

8. The clock generation circuit according to claim 1, characterized in that, The flow-controlled oscillation module includes a charging / discharging unit, a comparator, and a control unit. The charging / discharging unit is connected to a current generation unit to generate a voltage signal based on the output current. The first input terminal of the comparator is connected to the charging / discharging unit to receive the voltage signal, and the second input terminal of the comparator is connected to a reference voltage. The comparator is used to compare the voltage signal with the reference voltage to generate a result signal. The control unit is connected to the comparator to generate a clock control signal and a charging / discharging control signal based on the result signal. The charging / discharging unit is connected to the control unit to perform charging and discharging based on the control of the charging / discharging control signal.

9. The clock generation circuit according to claim 8, characterized in that, The charging and discharging unit includes a capacitor and a fifth switch. The first end of the capacitor and the first end of the fifth switch are connected to the current generating unit to receive the output current. The second end of the capacitor and the second end of the fifth switch are connected to the reference voltage. The fifth switch is connected to the control unit to control the opening or closing based on the charging and discharging control signal.

10. A phase-locked loop, characterized in that, include: The clock generation circuit according to any one of claims 1 to 9 further includes a frequency and phase detector, a charge pump, and a loop filter connected in sequence. The frequency and phase detector is connected to a pin terminal to receive the signal from the pin terminal. The frequency and phase detector is connected to a current-controlled oscillation unit to receive a clock control signal. The output terminal of the loop filter is connected to the clock generation circuit. The second input signal is the clock output signal output by the loop filter.

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