A multi-rate error code instrument device

Abstract

The utility model relates to a kind of multi-rate error code instrument equipment, by integrated power module, data transmission interface board, micro-control monitoring unit MCU, 1:8 I²C bus multiplexing module, multi-frequency crystal oscillator, 1:5 clock driving module and pluggable signal generation and error code analysis module, realize multi-channel extension and transceiver parallel test. Among them, by 1:8 I²C bus multiplexing module realizes single MCU control multiple peripheral equipment (including 4 error code analysis modules, clock driving module and oscillator), solves the I²C address conflict problem of traditional error code instrument;1:5 clock driving module provides 5-way clock output (4-way local use, 1-way extension), supports cascaded multi-device clock synchronization, avoids phase deviation;Signal generation and error code analysis module is pluggable, supports on-demand extension test channel;Power supply voltage division power supply (3.3V logic circuit / 1.8V high-speed circuit) optimizes noise isolation.

Description

Technical Field

[0001] This utility model relates to the field of communication testing equipment technology, specifically to a multi-rate bit error rate tester that supports multi-channel expansion and parallel transmission and reception testing. It is suitable for bit error rate testing of high-speed data transmission systems, especially for multi-channel synchronous testing scenarios. Background Technology

[0002] In the optical module industry, bit error rate testers are the core of testing equipment, used for performance debugging and testing of optical module products. Especially in production lines, a large number of bit error rate testers are needed. Currently, the disadvantages are high purchase cost, high maintenance cost, bulky and difficult to move, and inability to achieve multi-channel parallel testing and optical module expansion testing. Utility Model Content

[0003] In view of the technical defects and drawbacks existing in the prior art, the present invention provides a multi-rate bit error rate tester device that overcomes or at least partially solves the above problems and supports multi-channel expansion and parallel transmission and reception testing. The specific solution is as follows:

[0004] A multi-rate bit error rate tester device supporting multi-channel expansion and parallel transmit / receive testing includes:

[0005] The power module has its input end connected to an AC 220V power socket and its output end electrically connected to an LDO voltage regulator circuit, which provides DC 3.3V and 1.8V power respectively.

[0006] The data transmission interface board is equipped with a USB interface, an RJ45 interface, and multiple module slots;

[0007] The microcontroller monitoring unit (MCU) is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 3.3V output of the LDO voltage regulator circuit, and its I2C controller pin is electrically connected to the control signal input of the 1:8 I2C bus multiplexing module via the I2C bus.

[0008] The 1:8 I2C bus multiplexing module is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 3.3V output of the LDO voltage regulator circuit, its control signal input is electrically connected to the I2C controller pin of the MCU, and its output is electrically connected to the control interfaces of the signal generation and error analysis module, the clock drive module, and the multi-frequency crystal oscillator, respectively.

[0009] A multi-frequency crystal oscillator is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 1.8V output of the LDO voltage regulator circuit, and its frequency selection pin is electrically connected to the first channel output of the 1:8 I2C bus multiplexing module via the I2C bus. The first channel output of the 1:8 I2C bus multiplexing module is electrically connected to the MCU.

[0010] The 1:5 clock drive module is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 1.8V output of the LDO voltage regulator circuit, its clock input pin is connected to the output of the multi-frequency crystal oscillator, and its select signal pin is electrically connected to the second channel output of the 1:8 I2C bus multiplexing module via the I2C bus.

[0011] Four signal generation and error analysis modules are detachably inserted into slots on the data transmission interface board. The power supply pins of each signal generation and error analysis module are electrically connected to the 1.8V output of the LDO voltage regulator circuit. The control pins of the four signal generation and error analysis modules are electrically connected to the 3rd-6th channel outputs of the 1:8 I2C bus multiplexing module via I2C bus (i.e., the control pin of the 1st signal generation and error analysis module is electrically connected to the 3rd channel output of the 1:8 I2C bus multiplexing module via I2C bus, the control pin of the 2nd signal generation and error analysis module is electrically connected to the 4th channel output of the 1:8 I2C bus multiplexing module via I2C bus, the control pin of the 3rd signal generation and error analysis module is electrically connected to the 5th channel output of the 1:8 I2C bus multiplexing module via I2C bus, and the control pin of the 4th signal generation and error analysis module is electrically connected to the 6th channel output of the 1:8 I2C bus multiplexing module via I2C bus). Their clock input pins are connected to the five outputs of the 1:5 clock drive module.

[0012] The clock expansion interface connects its input signal to the expansion output of the 1:5 clock driver module for cascading the clock input of another device.

[0013] This utility model utilizes a 1:8 I²C bus multiplexing module to enable a single MCU to control multiple peripheral devices (including four bit error analysis modules, a clock drive module, and an oscillator), resolving the I²C address conflict problem of traditional bit error rate testers. The 1:5 clock drive module provides five clock outputs (four for local use and one for expansion), supporting cascaded clock synchronization of multiple devices and avoiding phase deviation. The signal generation and bit error analysis modules are pluggable, supporting on-demand expansion of test channels. Power supply voltage division (3.3V logic circuit / 1.8V high-speed circuit) optimizes noise isolation.

[0014] Furthermore, the device also includes a chassis for integrating various hardware modules. The power module and LDO voltage regulator circuit are located at the bottom of the chassis, the data transmission interface board is fixed in the middle of the chassis, and the clock expansion interface is located on the side wall of the chassis.

[0015] Furthermore, the signal generation and error analysis module includes: a PCB substrate with four connector interfaces J1-J4;

[0016] The LVPECL input interface J1 is soldered to the edge of the PCB substrate, and its input terminal receives external clock signals.

[0017] The TX clock management unit is soldered to the middle area of ​​the PCB substrate, and its clock input pin is electrically connected to the output of J1.

[0018] The TX programmable analog generator is soldered onto the PCB substrate and is adjacent to the TX clock management unit. Its enable pin is electrically connected to the control output of the TX clock management unit.

[0019] The CML output interface J2 is soldered to the edge of the PCB substrate, and its differential signal input terminals are electrically connected to the TX+ and TX- output pins of the TX programmable analog generator, respectively.

[0020] CML input interface J3 is soldered to the edge of the PCB substrate;

[0021] The equalizer is soldered to the PCB substrate, and its differential input terminal is electrically connected to the output terminal of J3.

[0022] The RXCDR unit is soldered to the PCB substrate and shares a heat sink with the equalizer. Its signal input pin is electrically connected to the output of the equalizer.

[0023] The RX clock management unit is soldered to the PCB substrate, and its reference clock input pin is electrically connected to the clock recovery output terminal of the RXCDR unit.

[0024] The RX programmable checker is soldered onto the PCB substrate. Its data input pin is electrically connected to the data output terminal of the RXCDR unit, and its clock synchronization pin is electrically connected to the clock output terminal of the RX clock management unit.

[0025] The interrupt management unit is soldered to the PCB substrate, and its error signal input pin is electrically connected to the error status pin of the RX programmable checker.

[0026] The serial communication unit J4 is soldered to the edge of the PCB substrate, and its data pins are electrically connected to the status output terminal of the interrupt management unit via the I2C bus.

[0027] The signal flow within the module forms two physical paths:

[0028] (1) Transmission path: J1 → TX clock management unit → TX programmable analog generator → J2

[0029] (2) Receive path: J3 → equalizer → RXCDR unit → RX clock management unit → RX programmable checker → interrupt management unit → J4.

[0030] Furthermore, it is characterized by:

[0031] The TX programmable analog generator is equipped with a rate adjustment circuit, which includes an adjustable resistor array. Each adjustable resistor control pin is electrically connected to the rate configuration pin group of the serial communication unit J4 via a ribbon cable.

[0032] The TX programmable analog generator is equipped with a data mode selection module, which includes a multi-position DIP switch. The common terminal of each DIP switch is electrically connected to the code pattern control pin of the serial communication unit J4, and each terminal corresponds to a different PRBS code pattern.

[0033] The equalizer is equipped with a compensation adjustment circuit, which includes a multi-stage adjustable capacitor network. Each capacitor adjustment terminal is electrically connected to the compensation control pin group of the serial communication unit J4.

[0034] An impedance matching transformer is provided between the output terminal of the equalizer and the RXCDR unit. Its primary coil pin is electrically connected to the output pad of the equalizer, and its secondary coil pin is soldered to the input pad of the RXCDR unit.

[0035] The TX programmable analog generator chip has a temperature compensation resistor soldered to its back, and its pins are attached to the chip package shell through thermally conductive silicone.

[0036] Furthermore, the 1:8 I2C bus multiplexing module includes:

[0037] The reusable circuit board is equipped with an input port group, an output port group, and a control terminal;

[0038] The input filter is soldered to the input area of ​​the multiplexed circuit board, and its SCL / SDA input pads are electrically connected to the corresponding pins of the input port group.

[0039] The I2C bus controller chip is soldered onto a multiplexed circuit board, and its signal input pads are electrically connected to the output pads of the input filter.

[0040] The switch controls whether the controller is turned on or off. It is soldered to the substrate and shares a heat sink with the I2C bus controller chip. Its enable pin is electrically connected to the control signal output terminal of the I2C bus controller chip.

[0041] A MOS switch array consists of multiple pairs of switches composed of multiple MOS transistors. The gate pin of each pair of switches is electrically connected to the independent control output terminal of the switch on or off controller.

[0042] Each interface of the output port group is connected to the source / drain pin of the corresponding MOS switch group through an impedance matching circuit.

[0043] The address selection pin of the control port is electrically connected to the address decoding input of the switch to turn the controller on or off.

[0044] Furthermore, it is characterized by:

[0045] The switch on / off controller is soldered to a multiplexed circuit board, and its instruction input interface is electrically connected to the control signal output terminal of the microcontroller monitoring unit (MCU).

[0046] The input filter is soldered to the input region of the multiplexed circuit board, and its filtering components include a high-frequency noise suppression circuit.

[0047] The control output terminal of the switch on / off controller is electrically connected to the gate pin of the MOS switch array.

[0048] Furthermore, the 1:5 clock drive module includes:

[0049] Five buffers are soldered to the clock area of ​​the data transmission interface board;

[0050] One AND gate is soldered to the data transmission interface board and located between buffers;

[0051] in:

[0052] The external clock input pin is electrically connected to the first input of the AND gate via a first buffer;

[0053] The internal clock input pin is electrically connected to the second input of the AND gate via a second buffer;

[0054] The clock selection signal pin is electrically connected to the enable terminal of the AND gate through a third buffer;

[0055] The output of the AND gate is connected to the internal clock output pin via a fourth buffer;

[0056] The output of the AND gate is also connected to the extended clock output pin via a fifth buffer;

[0057] The internal clock output pin signal is connected to the clock input pin of the signal generation and error analysis module, and the extended clock output pin signal is connected to the clock extension interface.

[0058] Furthermore, the multi-frequency crystal oscillator includes:

[0059] The oscillator substrate is fixed to the clock region of the data transmission interface board;

[0060] A fixed clock crystal oscillator is soldered to the input area of ​​the oscillator substrate, and its power supply pin is electrically connected to the 1.8V output of the LDO voltage regulator circuit.

[0061] A 10~1000MHz DSPLL clock synthesizer is soldered to an oscillator substrate, and its input pins are electrically connected to the output pins of a fixed clock crystal.

[0062] The buffer is soldered to the output area of ​​the oscillator substrate, and its input pin is electrically connected to the output pin of the DSPLL clock synthesizer.

[0063] The output pin of the buffer is electrically connected to the external clock input interface of the 1:5 clock drive module;

[0064] The frequency selection pin of the DSPLL clock synthesizer is electrically connected to the first channel output of the 1:8 I2C bus multiplexing module via an I2C bus.

[0065] Furthermore, the device supports cascading of multiple devices, and the output of its clock expansion interface can be connected to the external clock input interface of another device via a coaxial cable.

[0066] This utility model has the following beneficial effects:

[0067] 1. In the signal generation and error analysis module of this utility model, the TX programmable analog generator generates a specific data pattern for transmission; the CML circuit outputs differential CML level signals through TX+ and TX-; the RX- and RX+ input CML level signals are compensated for distortion and clocked during signal transmission by an equalizer and RX CDR to ensure signal quality before being input to the RX programmable checker to check whether the received data pattern meets expectations; the clock input is provided to the TX clock management unit and RX clock management unit as a reference clock base frequency for clock synchronization of the TX programmable analog generator and the RX programmable checker through LVPECL level conversion.

[0068] 2. In the 1:8 I2C bus multiplexing module of this utility model, SCL and SDA are filtered by an input filter to ensure the stability and accuracy of data transmission; the I2C bus controller is responsible for managing the I2C bus timing control and meeting the communication protocol; the switch on or off controller is responsible for receiving external control signals and selecting a specific I2C channel for data transmission by controlling the MOS switch.

[0069] 3. In the 1:5 clock drive module of this utility model, the external clock input, internal clock input, and clock selection signal are used to achieve clock selection through an AND gate. When the clock selection is high and the internal clock input is low, the internal clock signal is output. When the clock selection is low and the external clock input is low, the external clock signal is output.

[0070] 4. The multi-frequency crystal oscillator of this utility model can achieve different clock frequency outputs through frequency selection. Here, 155.515MHz, 161.132MHz, 167.187 MHz, and 176.562 MHz are mainly used. The clock frequency selection depends on the bandwidth of the output signal.

[0071] 5. The microcontroller monitoring unit of this utility model selects the frequency of the multi-frequency crystal oscillator, selects the output clock of the 1:5 clock drive module, and configures and checks the data mode of the signal generation and error analysis module through the I2C bus; it manages the I2C bus module and performs initialization, self-test, and task scheduling.

[0072] 6. For example Figure 6 As shown, when testing with expanded optical modules above 40G, the overall equipment frame will be... Figure 1 One clock output can be connected to the external clock input of another device block diagram to achieve 8-channel parallel testing. Attached Figure Description

[0073] Figure 1 This is a schematic diagram of the overall assembly of a multi-rate bit error rate meter device that supports multi-channel expansion and parallel transmission and reception testing, as provided in this embodiment.

[0074] Figure 2 This is a structural diagram of the signal generation and bit error analysis module provided in this embodiment;

[0075] Figure 3 This is a structural diagram of the 1:8 I2C bus multiplexing module provided in this embodiment;

[0076] Figure 4 This is a structural diagram of the 1:5 clock drive module provided in this embodiment;

[0077] Figure 5 This is a structural diagram of the multi-frequency crystal oscillator provided in this embodiment;

[0078] Figure 6 This is a schematic diagram of the multi-channel expansion structure provided in this embodiment. Detailed Implementation

[0079] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the present utility model, and not all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0080] To enable those skilled in the art to better understand the technical solutions of this utility model, exemplary embodiments of this utility model are described below with reference to the accompanying drawings, including various details of the embodiments of this utility model to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this utility model. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0081] Where there is no conflict, the various embodiments of this utility model and the features thereof can be combined with each other.

[0082] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0083] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0084] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0085] See Figure 1 As shown, a multi-rate bit error rate tester device supporting multi-channel expansion and parallel transmit / receive testing is provided in an embodiment of this utility model, comprising:

[0086] The power module has its input end connected to an AC 220V power socket and its output end electrically connected to an LDO voltage regulator circuit. The LDO voltage regulator circuit provides DC 3.3V and 1.8V power respectively. The LDO voltage regulator circuit adopts a voltage divider design, with 3.3V for logic circuits and 1.8V for high-speed circuits.

[0087] The data transmission interface board is equipped with a USB interface, an RJ45 interface, and multiple module slots;

[0088] The microcontroller monitoring unit (MCU) is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 3.3V output of the LDO voltage regulator circuit, and its I2C controller pin is electrically connected to the control signal input of the 1:8 I2C bus multiplexing module via the I2C bus.

[0089] The 1:8 I2C bus multiplexing module is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 3.3V output of the LDO voltage regulator circuit, its control signal input is electrically connected to the I2C controller pin of the MCU, and its output is electrically connected to the I²C interface of the signal generation and error analysis module, the I²C selection pin of the clock drive module, and the frequency selection pin of the multi-frequency crystal oscillator, respectively.

[0090] A multi-frequency crystal oscillator is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 1.8V output of the LDO voltage regulator circuit, and its frequency selection pin is electrically connected to the first channel output of the 1:8 I2C bus multiplexing module via the I2C bus. The first channel output of the 1:8 I2C bus multiplexing module is electrically connected to the MCU.

[0091] The 1:5 clock drive module is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 1.8V output of the LDO voltage regulator circuit, its clock input pin is connected to the output of the multi-frequency crystal oscillator, and its select signal pin is electrically connected to the second channel output of the 1:8 I2C bus multiplexing module via the I2C bus.

[0092] Four signal generation and error analysis modules are detachably inserted into slots on the data transmission interface board. The power supply pins of each signal generation and error analysis module are electrically connected to the 1.8V output of the LDO voltage regulator circuit. The control pins of the four signal generation and error analysis modules are electrically connected to the 3rd-6th channel outputs of the 1:8 I2C bus multiplexing module via I2C bus (i.e., the control pin of the 1st signal generation and error analysis module is electrically connected to the 3rd channel output of the 1:8 I2C bus multiplexing module via I2C bus, the control pin of the 2nd signal generation and error analysis module is electrically connected to the 4th channel output of the 1:8 I2C bus multiplexing module via I2C bus, the control pin of the 3rd signal generation and error analysis module is electrically connected to the 5th channel output of the 1:8 I2C bus multiplexing module via I2C bus, and the control pin of the 4th signal generation and error analysis module is electrically connected to the 6th channel output of the 1:8 I2C bus multiplexing module via I2C bus). Their clock input pins are connected to the five outputs of the 1:5 clock drive module.

[0093] The clock expansion interface connects its input signal to the expansion output of the 1:5 clock driver module for cascading the clock input of another device.

[0094] This invention achieves single-MCU control of multiple peripheral devices (4 error error modules + clock module + oscillator) through a 1:8 I²C bus multiplexing module, solving the problems of I²C address conflicts or the need for multiple MCUs in traditional bit error rate testers; the 1:5 clock drive module provides 5 clock outputs (4 for local modules + 1 for expansion), supporting cascaded clock synchronization of multiple devices and avoiding phase deviation of independent clock sources for multiple devices; the signal generation and bit error analysis module adopts a pluggable design, allowing for expansion of test channels as needed (4 channels by default), while the LDO voltage divider power supply (3.3V logic / 1.8V high-speed circuit) optimizes noise isolation.

[0095] In some embodiments, the device further includes a chassis for integrating various hardware modules, with the power module and LDO voltage regulator circuit located at the bottom of the chassis, the data transmission interface board fixed in the middle of the chassis, and the clock expansion interface located on the side wall of the chassis.

[0096] In the above embodiments, the power module is placed at the bottom to reduce the impact of electromagnetic interference on the data transmission interface board in the middle, and the side wall layout of the clock expansion interface facilitates cable management when multiple devices are cascaded.

[0097] See Figure 2 As shown, in some embodiments, the signal generation and error analysis module includes:

[0098] The PCB substrate has four connector interfaces, J1-J4.

[0099] The LVPECL input interface J1 is soldered to the edge of the PCB substrate, and its input terminal receives external clock signals.

[0100] The TX clock management unit is soldered to the middle area of ​​the PCB substrate, and its clock input pin is electrically connected to the output of J1 through metal traces.

[0101] The TX programmable analog generator is soldered onto the PCB substrate and is adjacent to the TX clock management unit. Its enable pin is electrically connected to the control output of the TX clock management unit via a ribbon cable.

[0102] The CML output interface J2 is soldered to the edge of the PCB substrate. Its differential signal input terminals are electrically connected to the TX+ and TX- output pins of the TX programmable analog generator through an impedance matching circuit, respectively.

[0103] CML input interface J3 is soldered to the edge of the PCB substrate;

[0104] The equalizer is soldered to the PCB substrate, and its differential input is connected to the output of J3 via a coaxial cable.

[0105] The RXCDR unit is soldered to the PCB substrate and shares a heat sink with the equalizer. Its signal input pins are electrically connected to the output of the equalizer via gold wire bonding.

[0106] The RX clock management unit is soldered to the PCB substrate, and its reference clock input pin is electrically connected to the clock recovery output terminal of the RXCDR unit.

[0107] The RX programmable checker is soldered to the PCB substrate. Its data input pin is connected to the data output terminal of the RXCDR unit through a flexible circuit board, and its clock synchronization pin is electrically connected to the clock output terminal of the RX clock management unit.

[0108] The interrupt management unit is soldered to the PCB substrate, and its error signal input pin is electrically connected to the error status pin of the RX programmable checker through a wire harness.

[0109] The serial communication unit J4 is soldered to the edge of the PCB substrate, and its data pins are electrically connected to the status output terminal of the interrupt management unit via the I2C bus.

[0110] The signal flow within the module forms two physical paths:

[0111] (1) Transmission path: J1 → TX clock management unit → TX programmable analog generator (configured via J4) → J2

[0112] (2) Receive path: J3 → equalizer → RXCDR unit → RX clock management unit → RX programmable checker → interrupt management unit → J4.

[0113] In the above embodiments, the transmitting path (J1→TX→J2) and the receiving path (J3→equalizer→RX→J4) are laid out independently to avoid crosstalk between transmitting and receiving signals, improve testing accuracy, and achieve physical isolation between the two paths. The RXCDR unit and the equalizer share a heatsink to ensure the stability of high-speed signal processing; the interrupt management unit reports the bit error status in real time, simplifying fault location.

[0114] In some embodiments, the TX programmable analog generator is provided with a rate adjustment circuit, which includes an adjustable resistor array, and each adjustable resistor control pin is electrically connected to the rate configuration pin group of the serial communication unit J4 via a ribbon cable.

[0115] The TX programmable analog generator is equipped with a data mode selection module, which includes a multi-position DIP switch. The common terminal of each DIP switch is electrically connected to the code pattern control pin of the serial communication unit J4 through a metal trace, and each terminal corresponds to a different PRBS code pattern.

[0116] The equalizer is equipped with a compensation adjustment circuit, which includes a multi-stage adjustable capacitor network. Each capacitor adjustment terminal is connected to the compensation control pin group of the serial communication unit J4 through a gold-plated spring.

[0117] An impedance matching transformer is provided between the output terminal of the equalizer and the RXCDR unit. Its primary coil pin is electrically connected to the output pad of the equalizer through gold wire bonding, and the secondary coil pin is soldered to the input pad of the RXCDR unit.

[0118] The TX programmable analog generator chip has a temperature compensation resistor soldered to its back, and its pins are attached to the chip package shell through thermally conductive silicone.

[0119] In the above embodiments, the adjustable resistor array enables stepless speed adjustment (traditionally a fixed range), the multi-level adjustable capacitor network adaptively compensates for channel loss, the impedance matching transformer eliminates reflection noise caused by impedance mismatch, and the temperature compensation resistor is bonded to the chip through thermally conductive silicone to suppress the effect of temperature drift.

[0120] See Figure 3 As shown, in some embodiments, the 1:8 I2C bus multiplexing module includes:

[0121] The reusable circuit board is equipped with an input port group, an output port group, and a control terminal;

[0122] The input filter is soldered to the input area of ​​the multiplexed circuit board, and its SCL / SDA input pads are connected to the corresponding pins of the input port group through metal traces.

[0123] The I2C bus controller chip is soldered to the center area of ​​the substrate, and its signal input pads are connected to the output pads of the input filter via gold wire bonding.

[0124] The switch controls whether the controller is turned on or off. It is soldered to the substrate and shares a heat sink with the I2C bus controller chip. Its enable pin is connected to the control signal output terminal of the I2C bus controller chip through a miniature pin header.

[0125] A MOS switch array consists of multiple pairs of switches composed of multiple MOS transistors. The gate pin of each pair of switches is connected to the independent control output terminal of the switch on or off controller through a gold-plated wire harness.

[0126] Each interface of the output port group is connected to the source / drain pin of the corresponding MOS switch group through an impedance matching circuit.

[0127] The address selection pin of the control port is connected to the address decoding input of the switch-on or-off controller via a flexible circuit board.

[0128] In the above embodiments, the MOS switch array replaces the mechanical relay, increasing the switching speed by hundreds of times (microseconds), extending the lifespan, and the impedance matching circuit ensures the integrity of long-distance signal transmission.

[0129] In some embodiments, the switch on or off controller is soldered to a multiplexed circuit board, and its instruction input interface is electrically connected to the control signal output terminal of the microcontroller monitoring unit (MCU) via a ribbon cable.

[0130] The input filter is soldered to the input region of the multiplexed circuit board, and its filtering components include a high-frequency noise suppression circuit.

[0131] The control output terminal of the switch on / off controller is connected to the gate pin of the MOS switch array via a gold-plated wire harness.

[0132] In the above embodiments, the input filter integrates a high-frequency noise suppression circuit (such as a π-type filter) to eliminate electromagnetic interference (EMI) on the I²C bus, and the switch controller is directly connected to the MCU to reduce instruction latency.

[0133] refer to Figure 4 As shown, in some embodiments, the 1:5 clock drive module includes:

[0134] Five buffers are soldered to the clock area of ​​the data transmission interface board;

[0135] One AND gate is soldered to the data transmission interface board and located between buffers;

[0136] in:

[0137] The external clock input pin is electrically connected to the first input of the AND gate via a first buffer;

[0138] The internal clock input pin is electrically connected to the second input of the AND gate via a second buffer;

[0139] The clock selection signal pin is electrically connected to the enable terminal of the AND gate through a third buffer;

[0140] The output of the AND gate is connected to the internal clock output pin via a fourth buffer;

[0141] The output of the AND gate is also connected to the extended clock output pin via a fifth buffer, which is dedicated to the extended clock output pin and is independent of the other buffers.

[0142] The internal clock output pin signal is connected to the clock input pin of the signal generation and error analysis module, and the extended clock output pin signal is connected to the clock extension interface.

[0143] In the above embodiments, the following is achieved by combining AND gates and buffers: selecting an internal clock (multi-frequency oscillator) or an external cascaded clock; the buffer enhances the clock driving capability and reduces signal attenuation.

[0144] refer to Figure 5 As shown, in some embodiments, the multi-frequency crystal oscillator includes:

[0145] The oscillator substrate is fixed to the clock region of the data transmission interface board;

[0146] A fixed clock crystal oscillator is soldered to the input area of ​​the oscillator substrate, and its power supply pin is electrically connected to the 1.8V output of the LDO voltage regulator circuit through metal traces.

[0147] A 10~1000MHz DSPLL clock synthesizer is soldered to the center area of ​​the oscillator substrate, and its input pins are connected to the output pins of the fixed clock crystal oscillator via gold wire bonding.

[0148] The buffer is soldered to the output area of ​​the oscillator substrate, and its input pins are connected to the output pins of the DSPLL clock synthesizer via gold wire bonding.

[0149] The output pin of the buffer is connected to the external clock input interface of the 1:5 clock drive module via a coaxial cable.

[0150] The frequency selection pin of the DSPLL clock synthesizer is electrically connected to the first channel output of the 1:8 I2C bus multiplexing module via an I2C bus.

[0151] In the above embodiments, a DSPLL clock synthesizer (10–1000MHz) replaces a fixed-frequency crystal oscillator, supporting software frequency switching (e.g., via I²C instructions) without requiring hardware replacement.

[0152] The buffer enhances clock drive capability and ensures stability under multiple loads.

[0153] refer to Figure 6 As shown, in some embodiments, the device supports multi-device cascading, and the output of its clock expansion interface can be connected to the external clock input interface of another device via a coaxial cable.

[0154] In the above embodiments, the clock expansion interface is connected to the external clock interface of the lower-level device via a coaxial cable, so as to realize the clock synchronization test of multiple devices and break through the limitation of the number of channels of a single device (such as cascading N devices to reach 4N channels).

[0155] It should be noted that the scheme for which protection is sought in this utility model is related to the selection and connection relationship of various hardware devices. Those skilled in the art, upon learning of the hardware scheme of this application, can obtain the corresponding program without any objection. Therefore, the scheme for which protection is sought in this application does not involve any improvement of the program.

[0156] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A multi-rate bit error rate meter, characterized in that, include: The power module has its input end connected to an AC 220V power socket and its output end electrically connected to an LDO voltage regulator circuit, which provides DC 3.3V and 1.8V power respectively. The data transmission interface board is equipped with a USB interface, an RJ45 interface, and multiple module slots; The microcontroller monitoring unit (MCU) is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 3.3V output of the LDO voltage regulator circuit, and its I2C controller pin is electrically connected to the control signal input of the 1:8 I2C bus multiplexing module via the I2C bus. The 1:8 I2C bus multiplexing module is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 3.3V output of the LDO voltage regulator circuit, its control signal input is electrically connected to the I2C controller pin of the MCU, and its output is electrically connected to the control interfaces of the signal generation and error analysis module, the clock drive module, and the multi-frequency crystal oscillator, respectively. A multi-frequency crystal oscillator is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 1.8V output of the LDO voltage regulator circuit, and its frequency selection pin is electrically connected to the first channel output of the 1:8 I2C bus multiplexing module via the I2C bus. The 1:5 clock drive module is soldered onto the data transmission interface board. Its power supply pin is electrically connected to the 1.8V output of the LDO voltage regulator circuit, its clock input pin is connected to the output of the multi-frequency crystal oscillator, and its select signal pin is electrically connected to the second channel output of the 1:8 I2C bus multiplexing module via the I2C bus. Four signal generation and error analysis modules are detachably inserted into the slots of the data transmission interface board. The power supply pins of each signal generation and error analysis module are electrically connected to the 1.8V output of the LDO voltage regulator circuit. The control pins of the four signal generation and error analysis modules are electrically connected to the outputs of channels 3-6 of the 1:8 I2C bus multiplexing module via the I2C bus. Their clock input pin signals are connected to the five outputs of the 1:5 clock drive module. The clock expansion interface connects its input signal to the expansion output of the 1:5 clock driver module for cascading the clock input of another device.

2. The multi-rate bit error rate analyzer device according to claim 1, characterized in that, The device also includes a chassis for integrating various hardware modules. The power module and LDO voltage regulator circuit are located at the bottom of the chassis, the data transmission interface board is fixed in the middle of the chassis, and the clock expansion interface is located on the side wall of the chassis.

3. The multi-rate bit error rate analyzer device according to claim 1, characterized in that, The signal generation and error analysis module includes: The PCB substrate has four connector interfaces, J1-J4. The LVPECL input interface J1 is soldered onto the PCB substrate, and its input terminal receives an external clock signal. The TX clock management unit is soldered onto the PCB substrate, and its clock input pin is electrically connected to the output of J1. The TX programmable analog generator is soldered onto the PCB substrate and is adjacent to the TX clock management unit. Its enable pin is electrically connected to the control output of the TX clock management unit. The CML output interface J2 is soldered onto the PCB substrate, and its differential signal input terminals are electrically connected to the TX+ and TX- output pins of the TX programmable analog generator, respectively. CML input interface J3 is soldered onto the PCB substrate; The equalizer is soldered onto the PCB, and its differential input is electrically connected to the output of J3. The RXCDR unit is soldered to the PCB substrate and shares a heat sink with the equalizer. Its signal input pin is electrically connected to the output of the equalizer. The RX clock management unit is soldered to the PCB substrate, and its reference clock input pin is electrically connected to the clock recovery output terminal of the RXCDR unit. The RX programmable checker is soldered onto the PCB substrate. Its data input pin is electrically connected to the data output terminal of the RXCDR unit, and its clock synchronization pin is electrically connected to the clock output terminal of the RX clock management unit. The interrupt management unit is soldered to the PCB substrate, and its error signal input pin is electrically connected to the error status pin of the RX programmable checker. The serial communication unit J4 is soldered to the edge of the PCB substrate, and its data pins are electrically connected to the status output terminal of the interrupt management unit via the I2C bus.

4. The multi-rate bit error rate analyzer device according to claim 3, characterized in that: The TX programmable analog generator is equipped with a rate adjustment circuit, which includes an adjustable resistor array. Each adjustable resistor control pin is electrically connected to the rate configuration pin group of the serial communication unit J4 via a ribbon cable. The TX programmable analog generator is equipped with a data mode selection module, which includes a multi-position DIP switch. The common terminal of each DIP switch is electrically connected to the code pattern control pin of the serial communication unit J4, and each terminal corresponds to a different PRBS code pattern. The equalizer is equipped with a compensation adjustment circuit, which includes a multi-stage adjustable capacitor network. Each capacitor adjustment terminal is plugged into the compensation control pin group of the serial communication unit J4. An impedance matching transformer is provided between the output terminal of the equalizer and the RXCDR unit. Its primary coil pin is electrically connected to the output pad of the equalizer, and its secondary coil pin is soldered to the input pad of the RXCDR unit. The TX programmable analog generator chip has a temperature compensation resistor soldered to its back, and its pins are attached to the chip package shell through thermally conductive silicone.

5. The multi-rate bit error rate analyzer device according to claim 1, characterized in that, The 1:8 I2C bus multiplexing module includes: The reusable circuit board is equipped with an input port group, an output port group, and a control terminal; The input filter is soldered to the input area of ​​the multiplexed circuit board, and its SCL / SDA input pads are electrically connected to the corresponding pins of the input port group. The I2C bus controller chip is soldered onto a multiplexed circuit board, and its signal input pads are electrically connected to the output pads of the input filter. The switch controls whether the controller is turned on or off. It is soldered to the substrate and shares a heat sink with the I2C bus controller chip. Its enable pin is electrically connected to the control signal output terminal of the I2C bus controller chip. A MOS switch array consists of multiple pairs of switches composed of multiple MOS transistors. The gate pin of each pair of switches is electrically connected to the independent control output terminal of the switch on or off controller. Each interface of the output port group is connected to the source / drain pin of the corresponding MOS switch group through an impedance matching circuit. The address selection pin of the control port is electrically connected to the address decoding input of the switch to turn the controller on or off.

6. The multi-rate bit error rate analyzer device according to claim 5, characterized in that, Its features are: The switch on / off controller is soldered to a multiplexed circuit board, and its instruction input interface is electrically connected to the control signal output terminal of the microcontroller monitoring unit (MCU) via a ribbon cable. The input filter is soldered to the input terminal area of ​​the multiplexed circuit board, and its filtering components include a high-frequency noise suppression circuit. The control output terminal of the switch on / off controller is electrically connected to the gate pin of the MOS switch array.

7. The multi-rate bit error rate analyzer device according to claim 1, characterized in that, The 1:5 clock drive module includes: Five buffers are soldered to the clock area of ​​the data transmission interface board; One AND gate is soldered to the data transmission interface board and located between buffers; in: The external clock input pin is electrically connected to the first input of the AND gate via a first buffer; The internal clock input pin is electrically connected to the second input of the AND gate via a second buffer; The clock selection signal pin is electrically connected to the enable terminal of the AND gate through a third buffer; The output of the AND gate is connected to the internal clock output pin via a fourth buffer; The output of the AND gate is also connected to the extended clock output pin via a fifth buffer; The internal clock output pin signal is connected to the clock input pin of the signal generation and error analysis module, and the extended clock output pin signal is connected to the clock extension interface.

8. The multi-rate bit error rate analyzer device according to claim 1, characterized in that, The multi-frequency crystal oscillator includes: The oscillator substrate is fixed to the clock region of the data transmission interface board; A fixed clock crystal oscillator is soldered to the input area of ​​the oscillator substrate, and its power supply pin is electrically connected to the 1.8V output of the LDO voltage regulator circuit. A 10~1000MHz DSPLL clock synthesizer is soldered to the center area of ​​the oscillator substrate, and its input pins are electrically connected to the output pins of the fixed clock crystal. The buffer is soldered to the output area of ​​the oscillator substrate, and its input pins are connected to the output pins of the DSPLL clock synthesizer via gold wire bonding. The output pin of the buffer is electrically connected to the external clock input interface of the 1:5 clock drive module; The frequency selection pin of the DSPLL clock synthesizer is electrically connected to the first channel output of the 1:8 I2C bus multiplexing module via an I2C bus.

9. The multi-rate bit error rate analyzer device according to claim 1, characterized in that, The device supports cascading of multiple devices, and its clock expansion interface output can be connected to the external clock input interface of another device via a coaxial cable.

Images