Dual-mode multi-protocol gateway based on FPGA

Abstract

The utility model discloses a dual mode multi-protocol gateway based on FPGA, the gateway includes host system module and the multi-protocol module and storage module respectively with host system module connection, the host system module includes FPGA chip and host MCU, the FPGA chip with host MCU passes through first SPI interface electric connection, the FPGA chip integration data processing unit, the listening unit, station site configuration unit and mode control unit, the listening unit is configured as the inside interrupt signal and outside trigger signal are listened to and generate effective listening result when listening to any signal effective, mode control unit is configured as according to the effective listening result of listening unit activates station site configuration unit, and drives gateway to switch between listening mode and working mode. The utility model provides the gateway, can realize the problem of no interference listening and automatic mode switching, solves traditional gateway mode switching cumbersome, the problem that listens to the interference bus.

Description

Technical Field

[0001] This utility model relates to the field of communications, and in particular to a dual-mode multi-protocol gateway based on FPGA. Background Technology

[0002] In the field of industrial control, multi-protocol gateways are key components for enabling data interaction between devices using different communication protocols. While multi-protocol gateway technology is relatively mature, it still has shortcomings in mode switching and wireless communication adaptation. Traditional gateways typically do not support automatic switching between "listening" and "working" modes, requiring manual operation, resulting in low switching efficiency and difficulty meeting the real-time requirements of scenarios such as port cranes. Furthermore, traditional gateways lack dedicated hardware support for wireless communication, leading to insufficient communication stability in complex industrial environments and impacting overall system reliability. Utility Model Content

[0003] In view of the above-mentioned shortcomings of current multi-protocol gateways, this utility model provides a dual-mode multi-protocol gateway based on FPGA, which can realize interference-free monitoring and automatic mode switching, and solve the problems of cumbersome mode switching and monitoring interference bus of traditional gateways.

[0004] To achieve the above objectives, the embodiments of this utility model adopt the following technical solutions:

[0005] A dual-mode multi-protocol gateway based on FPGA is disclosed. The gateway includes a main control module, a multi-protocol module, and a storage module, which are respectively connected to the main control module. The main control module includes an FPGA chip and a main MCU. The FPGA chip and the main MCU are electrically connected via a first SPI interface. The FPGA chip integrates a data processing unit, a monitoring unit, a station configuration unit, and a mode control unit. The monitoring unit is configured to monitor internal interrupt signals and external trigger signals and generate a valid monitoring result when any signal is valid. The mode control unit is configured to activate the station configuration unit based on the valid monitoring result of the monitoring unit and drive the gateway to switch between monitoring mode and working mode.

[0006] According to one aspect of the present invention, the gateway further includes a power supply module; the reset pin of the FPGA chip is connected to the output terminal of the power supply module, and the power supply module is configured to output a reset signal to the reset pin when the gateway is powered on, so that the FPGA chip enters a listening mode.

[0007] According to one aspect of the present invention, the external trigger signal is input through the IO70 pin of the FPGA chip; the internal interrupt signal is generated by the IEC61131-3 software through the internal interrupt INT0 of the FPGA chip.

[0008] According to one aspect of the present invention, the mode control unit, triggered by a valid listening result, wakes up the station configuration unit via the IO69 pin to read preset station information in the FPGA on-chip ROM.

[0009] According to one aspect of the present invention, the storage module includes a storage MCU and an SRAM, wherein the storage MCU is electrically connected to the main MCU via a second SPI interface, and the SRAM is electrically connected to the storage MCU.

[0010] According to one aspect of this utility model, the multi-protocol module includes a CAN interface circuit, an RS-232 interface circuit, and an Ethernet interface circuit; the communication pins of the CAN interface circuit, the RS-232 interface circuit, and the Ethernet interface circuit are all connected to the I / O pins of the storage MCU.

[0011] According to one aspect of this utility model, the SRAM stores data by dividing address segments according to protocol type.

[0012] According to one aspect of the present invention, the Ethernet interface circuit includes an Ethernet physical layer chip and a network transformer. The Ethernet physical layer chip is connected to the storage MCU via an RMII interface, and the network transformer is connected between the Ethernet physical layer chip and the RJ45 interface.

[0013] According to one aspect of the present invention, the gateway further includes a wireless adaptation codec unit and a wireless parameter DIP switch; the wireless adaptation codec unit is integrated inside the FPGA chip; the wireless parameter DIP switch is connected to the IO pin of the FPGA chip or the main MCU.

[0014] According to one aspect of the present invention, the gateway further includes a retransmission parameter DIP switch and a wireless communication retransmission control unit; the wireless communication retransmission control unit is integrated inside the FPGA chip; the retransmission parameter DIP switch is connected to the IO pin of the FPGA chip or the main MCU.

[0015] The advantages of this invention are as follows: By adopting domestically produced FPGA and ARM chips as the main control core, integrating RS485, CAN, and Ethernet multi-protocol interface circuits, and constructing a dual-mode automatic switching mechanism based on hardware logic, the gateway achieves reliable monitoring of the bus with zero interference during initial deployment and subsequent intelligent online operation. Furthermore, the built-in dedicated wireless codec unit and wireless communication retransmission control unit effectively ensure a low packet loss rate in wireless communication. The hardware architecture of this solution is independently controllable, effectively improving the adaptability, reliability, and domestic substitution capabilities of industrial gateways in complex scenarios. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a dual-mode multi-protocol gateway based on FPGA according to the present invention;

[0018] Figure 2 This is a schematic diagram of the FPGA structure of a dual-mode multi-protocol gateway based on FPGA according to the present invention.

[0019] Figure 3 This is a schematic diagram of an FPGA chip circuit for a dual-mode multi-protocol gateway based on FPGA, as described in this utility model.

[0020] Figure 4 This is a schematic diagram of the main MUC circuit of a dual-mode multi-protocol gateway based on FPGA according to the present invention.

[0021] Figure 5 This is a schematic diagram of the main control module circuit of a dual-mode multi-protocol gateway based on FPGA according to the present invention.

[0022] Figure 6 This is a schematic diagram of a storage MUC circuit for a dual-mode multi-protocol gateway based on FPGA, as described in this utility model.

[0023] Figure 7 This is a schematic diagram of an SRAM circuit for a dual-mode multi-protocol gateway based on FPGA according to the present invention.

[0024] Figure 8 This is a schematic diagram of a multi-protocol module circuit for a dual-mode multi-protocol gateway based on FPGA according to the present invention.

[0025] Figure 9 This is a schematic diagram of the power module circuit of a dual-mode multi-protocol gateway based on FPGA as described in this utility model. Detailed Implementation

[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0027] Example 1

[0028] A dual-mode multi-protocol gateway based on FPGA includes a main control module and a multi-protocol module and a storage module respectively connected to the main control module. The main control module includes an FPGA chip and a main MCU, with the FPGA chip and the main MCU electrically connected via a first SPI interface. The FPGA chip integrates a data processing unit, a monitoring unit, a station configuration unit, and a mode control unit. The monitoring unit is configured to monitor internal interrupt signals and external trigger signals and generate a valid monitoring result when any signal is valid. The mode control unit is configured to activate the station configuration unit based on the valid monitoring result of the monitoring unit and drive the gateway to switch between monitoring mode and working mode. The dual-mode multi-protocol gateway works collaboratively through its hardware structure to achieve automatic switching between monitoring mode and working mode.

[0029] In practical use, the gateway also includes a power module; the reset pin of the FPGA chip is connected to the output of the power module, and the power module is configured to output a reset signal to the reset pin when the gateway is powered on, so that the FPGA chip enters the listening mode.

[0030] Specifically, the power module is configured to provide operating voltage to the FPGA chip and output a reset signal to its reset pin (IO25); wherein the reset signal is active low and is configured to remain low for 100ms after power-on before being released, so that the FPGA chip automatically enters the listening mode.

[0031] In practical use, the external trigger signal is input through the IO70 pin of the FPGA chip; the internal interrupt signal is generated by the IEC61131-3 software through the internal interrupt INT0 of the FPGA chip.

[0032] Specifically, the triggering conditions for the gateway to switch from monitoring mode to working mode depend on the generation and determination of two types of trigger signals, as implemented as follows:

[0033] External trigger signal generation and determination: The IO70 pin of the FPGA chip is connected to an external trigger interface, such as the dry contact signal interface of a PLC. When an external device sends a high-level trigger signal to the IO70 pin, and the duration of the high-level trigger signal is greater than 50ms, the external trigger signal is determined to be valid.

[0034] Generation and determination of internal trigger signals: When processing data in the data processing unit using IEC61131-3 software, if a preset trigger condition is detected, such as receiving a start control command frame or the number of data anomalies exceeding 3, the IEC61131-3 software generates an internal interrupt signal through the FPGA's internal interrupt signal INT0.

[0035] The aforementioned external trigger signal and internal interrupt signal are input to the OR logic gate of the monitoring unit; after the OR logic gate determines whether either the external trigger signal or the internal interrupt signal is valid, the trigger mode control unit performs a switching operation from the monitoring mode to the working mode.

[0036] In practical use, when the mode control unit is triggered by a valid listening result, it wakes up the station configuration unit via the IO69 pin to read the preset station information in the FPGA on-chip ROM.

[0037] Specifically, after the mode control unit receives a valid listening result from the monitoring unit, the FPGA outputs a high level through pin IO69 to wake up the station configuration unit. The station configuration unit reads preset station information from the FPGA's on-chip ROM (addresses 0x1000-0x1FFF), which includes the station ID, communication baud rate, protocol type, etc. Subsequently, the FPGA outputs a high level through pin IO67, and the mode control unit drives the data processing unit to switch its internal data path from a receive-only state to a bidirectional transmit / receive state, officially entering the working mode. The mode switching status can be fed back through the indicator light connected to pin IO143; for example, a solid blue light indicates monitoring, and a solid red light indicates operation. The entire switching process takes less than 200ms.

[0038] In practical use, the storage module includes a storage MCU and an SRAM. The storage MCU is electrically connected to the main MCU through a second SPI interface, and the SRAM is electrically connected to the storage MCU.

[0039] Specifically, the storage MCU uses a GD32F407, and the main MCU uses a GD32F407VX. Pins 138-141 of the storage MCU are connected to pins 77-80 of the main MCU in sequence. The SRAM and the storage MCU are electrically connected through the FSMC pin.

[0040] In practical use, the multi-protocol module includes a CAN interface circuit, an RS-232 interface circuit, and an Ethernet interface circuit; the communication pins of the CAN interface circuit, RS-232 interface circuit, and Ethernet interface circuit are all connected to the I / O pins of the storage MCU.

[0041] Specifically, the CAN interface circuit's ports CAN1_RX and CAN1_TX are connected to the storage MCU; the RS-232 interface circuit's ports PA9_USART1_TX and PA10_USART1_RX are connected to the storage MCU; and the Ethernet interface circuit is connected to the storage MCU via the RMII function pin.

[0042] In practical use, SRAM stores data by dividing address segments according to protocol type.

[0043] Specifically, the SRAM used can be the IS62WV51216, with a capacity of 8MB. Data is stored in address segments divided according to protocol type: RS485 data corresponds to the 0x00000-0x1FFFF address segment, CAN data to the 0x20000-0x3FFFF address segment, and Ethernet data to the 0x40000-0x7FFFF address segment. When the cache is full, it automatically overwrites the oldest data, and a yellow indicator light can be triggered to flash as a reminder via an I / O pin.

[0044] In practical use, the Ethernet interface circuit includes an Ethernet physical layer chip and a network transformer. The Ethernet physical layer chip is connected to the storage MCU through the RMII interface, and the network transformer is connected between the Ethernet physical layer chip and the RJ45 interface.

[0045] Specifically, the Ethernet physical layer chip can be LAN8720Ai, the network transformer can be HR911105A, and the RJ45 interface is J2, which is integrated with HR911105A.

[0046] In summary, the working principle of a dual-mode multi-protocol gateway is as follows:

[0047] (1) Working principle of monitoring mode

[0048] After the gateway powers on, the power module outputs a reset signal to the FPGA chip's reset pin, causing the FPGA to automatically enter listen mode. In this mode, the gateway's core task is to receive and buffer bus data without interference, without responding to any requests on the bus. The specific implementation process is as follows:

[0049] Physical layer receive suppression: The FPGA's mode control unit outputs a low level through its IO66-IO67 pins. This signal is connected to the transmit enable pin of each interface circuit in the multi-protocol module, such as CAN_TX of the CAN interface. This disables the transmit drive function of all interfaces, ensuring that the gateway passively receives bus data only through the receiver, such as CAN_RX of the CAN interface, without actively or reactively sending any signals to the bus, thereby avoiding any interference with the original bus communication.

[0050] Data link layer response masking: This is a data processing unit embedded within the FPGA, occupying approximately 10% of the logic units. It only performs the function of parsing received frames. It can correctly parse the received data frame format and perform verification, but its internal response frame generation circuitry is masked. Therefore, the parsed valid data packets are transmitted to the storage module through the internal data bus without generating any acknowledgment signals such as ACK frames or site response frames.

[0051] Application layer data forwarding and response disabled: The parsed data is sent to the storage module. The FPGA outputs a low level to the storage MCU via the IO11 pin, putting it into data forwarding mode. In this mode, the application layer program running on the storage MCU only adds timestamps and other information to the received data, classifies it according to protocol type, and stores it in the designated address range of SRAM. Its request-response mode is completely disabled, meaning it does not perform any application layer command parsing or response.

[0052] In summary, in monitoring mode, the data stream is received unidirectionally: data is first received at the physical layer by the multi-protocol module, then transmitted to the data processing unit within the FPGA chip for parsing, further transmitted to the storage MCU for application layer decoding, and finally stored in the SRAM cache. The gateway completes the full decoding from physical signals to application data, but suppresses any form of transmission throughout the entire process.

[0053] (2) Working mode and working principle

[0054] When the monitoring unit detects a valid trigger signal, the mode control unit initiates a mode switching process, causing the gateway to switch from monitoring mode to working mode, thus enabling full bidirectional data interaction capabilities. The specific implementation process is as follows:

[0055] Site Configuration and Wake-up: The mode control unit first outputs a high level through the IO69 pin to wake up the site configuration unit. This unit reads the pre-programmed site information, such as the site ID and communication parameters, from a specified address in the FPGA's on-chip ROM and configures it into the application layer codec module, thus granting the gateway a legitimate identity in the network.

[0056] Communication Enable and Path Establishment: The mode control unit outputs a high level through pins such as IO67 to re-enable the transmit drive function of each interface circuit in the multi-protocol module. Simultaneously, it enables the response frame generation circuit of the FPGA's internal data processing unit. The storage MCU is controlled via pin IO11 to exit data forwarding mode and enter a complete request-response mode.

[0057] In summary, in operating mode, the gateway's data path is fully open. It can receive bus data like in listening mode, and can also generate corresponding application-layer data based on received requests or internal logic processing results. After data link layer encapsulation by the FPGA, this data is sent to the bus through the physical interface. Simultaneously, the mode switching process is accompanied by status indicators connected to the FPGA's IO143 pin; for example, a solid blue light indicates listening, and a solid red light indicates operating. The entire switching process is completed within 200ms.

[0058] Example 2

[0059] Based on the hardware of Embodiment 1, this embodiment adds a wireless adaptation codec unit, a dedicated retransmission algorithm hardware unit, and a wireless bridge interface circuit to achieve stable communication with the wireless bridge.

[0060] In practical use, the dual-mode multi-protocol gateway also includes a wireless adapter codec unit and a wireless parameter DIP switch; the wireless adapter codec unit is integrated inside the FPGA chip; the wireless parameter DIP switch is connected to the IO pins of the FPGA chip or the main MCU.

[0061] Specifically, the wireless adapter codec unit is integrated inside the FPGA chip, occupying a portion of the FPGA's logic units to form the codec core. This module communicates with the main MCU via a first SPI interface, which is connected to the FPGA's dedicated communication pin group. The wireless parameter DIP switch is a multi-bit switch, and its output is connected to the FPGA's general-purpose input / output pins for configuring wireless communication parameters.

[0062] Furthermore, the encoding / decoding module supports data compression and format conversion. When the gateway needs to transmit data wirelessly, the main MCU sends the data to be sent to the encoding / decoding module via the SPI bus. The module's internal hardware logic compresses the data and converts the protocol format before outputting it to the subsequent processing unit.

[0063] In practical use, the dual-mode multi-protocol gateway also includes a retransmission parameter DIP switch and a wireless communication retransmission control unit; the wireless communication retransmission control unit is integrated inside the FPGA chip; the retransmission parameter DIP switch is connected to the IO pins of the FPGA chip or the main MCU.

[0064] Specifically, the wireless communication retransmission control unit is integrated within the FPGA chip, forming dedicated retransmission control logic. This unit is connected to the SRAM via an internal bus, enabling direct reading and writing of buffered data. The output of the retransmission parameter DIP switch is connected to the FPGA's configuration pin.

[0065] Furthermore, the retransmission control unit employs a hardware-implemented timeout retransmission mechanism. During data transmission, the unit assigns a sequence number to each data frame and starts a hardware timer. After receiving an acknowledgment frame, the unit updates its status register; if no acknowledgment is received within the timeout period, the hardware logic automatically triggers the retransmission sequence.

[0066] In practical use, the dual-mode multi-protocol gateway also includes a wireless bridge interface circuit. This circuit serves as a dedicated hardware interaction channel between the gateway and the external wireless bridge, and its structure is adapted to the FPGA architecture. The specific implementation is as follows:

[0067] A standard RJ45 interface with a shielded shell is adopted to enhance the anti-electromagnetic interference capability. The interface is internally coupled to the RTL8211F Ethernet physical layer chip connected to the FPGA via the network transformer H1102, supporting an adaptive communication rate of 10 / 100Mbps. A domestic DC-DC chip MP2307 is integrated near the interface, which outputs 5V / 1A voltage with ripple ≤50mV to provide stable auxiliary power supply for the external wireless bridge. An optocoupler isolation chip TLP521-4 is connected in series in the signal path to achieve electrical isolation of the signal, effectively suppressing the surge voltage introduced by the wireless bridge and protecting the core circuit of the gateway.

[0068] The advantages of this invention are as follows: By adopting domestically produced FPGA and ARM chips as the main control core, integrating RS485, CAN, and Ethernet multi-protocol interface circuits, and constructing a dual-mode automatic switching mechanism based on hardware logic, the gateway achieves reliable monitoring of the bus with zero interference during initial deployment and subsequent intelligent online operation. Furthermore, the built-in dedicated wireless codec unit and wireless communication retransmission control unit effectively ensure a low packet loss rate in wireless communication. The hardware architecture of this solution is independently controllable, effectively improving the adaptability, reliability, and domestic substitution capabilities of industrial gateways in complex scenarios.

[0069] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A dual-mode multi-protocol gateway based on FPGA, the gateway comprising a main control module and a multi-protocol module and a storage module respectively connected to the main control module, characterized in that, The main control module includes an FPGA chip and a main MCU. The FPGA chip and the main MCU are electrically connected via a first SPI interface. The FPGA chip integrates a data processing unit, a monitoring unit, a site configuration unit, and a mode control unit. The monitoring unit is configured to monitor internal interrupt signals and external trigger signals and generate a valid monitoring result when any signal is detected. The mode control unit is configured to activate the site configuration unit based on the valid monitoring result of the monitoring unit and drive the gateway to switch between monitoring mode and working mode.

2. The dual-mode multi-protocol gateway according to claim 1, characterized in that, The gateway also includes a power module; the reset pin of the FPGA chip is connected to the output of the power module, and the power module is configured to output a reset signal to the reset pin when the gateway is powered on, so that the FPGA chip enters a listening mode.

3. The dual-mode multi-protocol gateway according to claim 1, characterized in that, The external trigger signal is input through the IO70 pin of the FPGA chip; the internal interrupt signal is generated by the IEC61131-3 software through the internal interrupt INT0 of the FPGA chip.

4. The dual-mode multi-protocol gateway according to claim 1, characterized in that, When triggered by a valid monitoring result, the mode control unit wakes up the station configuration unit via the IO69 pin to read the preset station information in the FPGA on-chip ROM.

5. The dual-mode multi-protocol gateway according to claim 1, characterized in that, The storage module includes a storage MCU and an SRAM. The storage MCU is electrically connected to the main MCU via a second SPI interface, and the SRAM is electrically connected to the storage MCU.

6. The dual-mode multi-protocol gateway according to claim 5, characterized in that, The multi-protocol module includes a CAN interface circuit, an RS-232 interface circuit, and an Ethernet interface circuit; the communication pins of the CAN interface circuit, RS-232 interface circuit, and Ethernet interface circuit are all connected to the I / O pins of the storage MCU.

7. The dual-mode multi-protocol gateway according to claim 5, characterized in that, The SRAM stores data by dividing address segments according to protocol type.

8. The dual-mode multi-protocol gateway according to claim 6, characterized in that, The Ethernet interface circuit includes an Ethernet physical layer chip and a network transformer. The Ethernet physical layer chip is connected to the storage MCU through an RMII interface, and the network transformer is connected between the Ethernet physical layer chip and the RJ45 interface.

9. The dual-mode multi-protocol gateway according to claim 1, characterized in that, The gateway also includes a wireless adaptation codec unit and a wireless parameter DIP switch; the wireless adaptation codec unit is integrated inside the FPGA chip; the wireless parameter DIP switch is connected to the IO pins of the FPGA chip or the main MCU.

10. The dual-mode multi-protocol gateway according to claim 9, characterized in that, The gateway also includes a retransmission parameter DIP switch and a wireless communication retransmission control unit; the wireless communication retransmission control unit is integrated inside the FPGA chip; the retransmission parameter DIP switch is connected to the IO pin of the FPGA chip or the main MCU.

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