Performance test system for pre-distortion algorithm based on television exciter

Abstract

The application relates to the field of signal processing and testing, in particular to a pre-distortion algorithm performance test system based on a television exciter. The system comprises an FPGA chip, a DAC chip, an ADC chip, a power amplifier, an IQ demodulator and an MCU control module, the MCU control module controls the FPGA chip to run, the FPGA chip, the DAC chip and the power amplifier form a signal transmission link, the IQ demodulator, the ADC chip and the FPGA chip form a signal feedback link, and the system further comprises a circuit board provided with a digital area and an analog area, the chips and the modules are reasonably arranged in the corresponding areas, and the radio frequency analog area and the digital area are isolated through a shielding ground slit. The application can effectively test the pre-distortion algorithm performance based on the television exciter, and through reasonable arrangement and isolation design, the technical effects of guaranteeing stable operation of the system and testing accuracy are achieved.

Description

Technical Field

[0001] This application relates to the field of signal processing and testing, and in particular to a performance testing system for a predistortion algorithm based on a television exciter. Background Technology

[0002] The DTMB terrestrial digital television broadcast exciter is a core component of the digital television transmission system. It is responsible for processing the input digital television transport stream (TS) through channel coding, modulation, and frequency conversion, ultimately outputting a high-quality radio frequency (RF) signal that conforms to national standards (such as GB 20600-2006). Its performance directly determines the transmitter's output signal quality, coverage, and the stability of the entire system.

[0003] While existing exciter products meet basic national standards for several key performance indicators, such as frequency accuracy in single-frequency network (SFN) mode, local oscillator phase noise, shoulder characteristics, modulation error rate (MER), and error vector accuracy (EVM), there is still room for optimization. In particular, with the dual goals of pursuing higher power efficiency and better signal quality, the requirements for the linearization of the internal power amplifier of the exciter are becoming increasingly stringent.

[0004] Digital predistortion (DPD) technology is one of the key means to overcome the above-mentioned bottlenecks. Power amplifiers (PAs) exhibit nonlinear characteristics when operating at high efficiency, causing in-band distortion and out-of-band spectral spread, leading to MER deterioration and adjacent channel interference. DPD technology compensates for power amplifier nonlinearity by performing inverse predistortion on the signal in the baseband, and is one of the most effective linearization techniques currently available. However, the DPD algorithm is highly complex and computationally intensive. When conducting actual performance testing of the DPD algorithm deployed in DTMB products, the time and manpower costs are typically high, thus affecting the speed of algorithm iteration and optimization. Therefore, designing a DPD algorithm performance testing system for DTMB scenarios with independent transmit and receive testing and verification to improve testing speed and flexibility while reducing costs is an urgent problem to be solved. Utility Model Content

[0005] This application provides a predistortion algorithm performance testing system based on a television exciter, which can improve the testing speed and flexibility of DPD algorithm performance while reducing costs. The technical solution adopted is as follows: A performance testing system for a predistortion algorithm based on a television exciter includes: an FPGA chip, a DAC chip, an ADC chip, a power amplifier, an IQ demodulator, and an MCU control module; the MCU control module is communicatively connected to the FPGA chip to control the operation of the FPGA chip. The FPGA chip, DAC chip, and power amplifier form a signal transmission link; the FPGA chip is connected to the host computer to receive test data and generate digital signals; the DAC chip is connected to the FPGA chip to convert digital signals into analog signals; and the power amplifier is connected to the DAC chip to emit radio frequency signals. The IQ demodulator, ADC chip, and FPGA chip form a signal feedback link; the input of the IQ demodulator is used to acquire radio frequency signals and convert them into analog signals; the ADC chip is communicatively connected to the IQ demodulator to convert analog signals into digital signals; the FPGA chip is communicatively connected to the ADC chip to process the digital signals and feed them back to the host computer.

[0006] By adopting the above technical solution, the system uses a heterogeneous dual-core architecture with FPGA and MCU working together, which leverages the parallel processing capability of FPGA and the complex logic management capability of MCU, ensuring the real-time processing performance of high-speed data streams and improving the system's flexibility, maintainability and intelligent management level. The transmit link module and the feedback link module are set up independently and form a closed-loop test path, realizing the integration of a complete digital predistortion performance test loop. The RF output of the transmit link and the return signal of the feedback link can be observed and compared separately, and the two links can be flexibly verified and optimized for specific modules.

[0007] Preferably, the system has a memory for storing test data, and the FPGA chip has a data processing module for reading, converting, and outputting the test data in the memory. The data processing module, together with the DAC chip and the power amplifier, forms a signal transmission link.

[0008] By adopting the above technical solution, the test data can be read and converted by the data processing module in the FPGA chip, which can keep the transmission link relatively independent, thus facilitating data detection.

[0009] Preferably, the FPGA chip has a feedback signal processing module for processing the digital signal generated by the ADC chip and feeding the processed signal back to the host computer; the IQ demodulator, the ADC chip and the feedback signal processing module form a signal feedback link.

[0010] By adopting the above technical solution, the feedback signal processing module in the FPGA chip processes the signal and feeds it back to the host computer, which can keep the feedback link relatively independent, thereby facilitating the comparison and detection of data.

[0011] Preferably, the input terminal of the IQ demodulator is coupled to the output terminal of the power amplifier for acquiring radio frequency signals.

[0012] By adopting the above technical solution, the input terminal of the IQ demodulator is coupled to the output terminal of the power amplifier to facilitate the acquisition of radio frequency signals for subsequent processing, which effectively simplifies the acquisition method of radio frequency signals and improves efficiency.

[0013] Preferably, the MCU control module communicates with the FPGA chip via an SPI interface.

[0014] By adopting the above technical solution, a unified register mapping space is created within the FPGA. The MCU control module reads and writes to this space via the SPI bus, enabling configuration and status monitoring of all functional modules within the FPGA. This leverages both the parallel processing capabilities of the FPGA and the complex logic management capabilities of the MCU, ensuring the system's real-time processing performance for high-speed data streams and improving the system's flexibility, maintainability, and intelligent management level.

[0015] Preferably, the FPGA chip communicates with the host computer via the UDP protocol.

[0016] By adopting the above technical solution, the FPGA chip and the host computer communicate via the UDP protocol, enabling the FPGA to parse and encapsulate network protocols at high speed and accurately, and process and transmit data in real time.

[0017] Preferably, it also includes a circuit board, which has a digital area and an analog area; the FPGA chip and MCU control module are located in the digital area, and the DAC chip, ADC chip, power amplifier, and IQ demodulator are all located in the analog area; A shielded ground gap is provided between the radio frequency analog area and the digital area to achieve isolation.

[0018] By adopting the above technical solution, the sensitive analog part is spatially isolated from the noisy digital part, and the noise coupling path on the ground plane is cut off by the ground gap, which effectively suppresses the interference of digital noise on the analog signal.

[0019] Preferably, a power supply and heat dissipation area is provided at the edge of the circuit board for arranging the system's power module.

[0020] By adopting the above technical solution, the heat source and the power module that may generate electromagnetic interference are placed in the edge power and heat dissipation area, away from sensitive radio frequency and clock circuits. At the same time, it facilitates the centralized wiring of power lines and ground lines, reducing loop area.

[0021] In summary, this application includes at least one of the following beneficial technical effects: 1. Employing a heterogeneous dual-core architecture that integrates FPGA and MCU, this system leverages the parallel processing capabilities of the FPGA and the complex logic management capabilities of the MCU. This ensures real-time processing performance of high-speed data streams and enhances the system's flexibility, maintainability, and intelligent management. Independent testing and comparative experiments on the transmit and feedback links reduce the time cost of performance improvements, doubling the speed of the optimization algorithm. This hardware foundation allows the DPD algorithm to fully function, effectively compensating for the power amplifier's nonlinear distortion. It significantly reduces out-of-band spurious emissions (better than -55dBc) and improves the MER to over 40dB, thus meeting stringent broadcast transmission standards and allowing the power amplifier to operate at higher efficiency. It can respond promptly after algorithm optimization. 2. Modular physical partitioning creates digital, analog, and power supply / heat dissipation zones. The digital zone houses the FPGA chip and MCU control module, while the analog zone houses the DAC chip, ADC chip, power amplifier, and IQ demodulator. This spatially isolates the sensitive analog components from the noisier digital components, reducing digital noise interference with analog signals. 3. A shielded ground gap is provided between the analog area and the digital area. The shielded ground gap can cut off the noise coupling path on the ground plane and further achieve isolation. The heat source and power modules that may generate electromagnetic interference are placed in the edge power and heat dissipation area, away from sensitive radio frequency and clock circuits. At the same time, it facilitates the centralized wiring of power lines and ground lines and reduces loop area. Attached Figure Description

[0022] Figure 1 This is a circuit block diagram of the test system in an embodiment of this application; Figure 2 This is a schematic diagram of the modular physical layout of the board in the embodiments of this application.

[0023] The following labels are used in the attached diagram: 1. FPGA chip; 11. Data processing module; 12. Feedback signal processing module; 2. DAC chip; 3. ADC chip; 4. Power amplifier; 5. IQ demodulator; 6. MCU control module; 7. Transmit link; 8. Feedback link; 9. Circuit board; 91. Digital area; 92. Analog area; 93. Shielding gap; 94. Power supply and heat dissipation area. Detailed Implementation

[0024] The following is in conjunction with the appendix Figures 1-2 This application will be described in further detail.

[0025] The predistortion algorithm performance testing system based on a TV exciter provided in this application includes an FPGA chip 1, a DAC chip 2, an ADC chip 3, a power amplifier 4, an IQ demodulator 5, and an MCU control module 6. These functional modules are integrated onto a single circuit board 9, forming a single board. The board connects to a host computer via UDP and transmits data via an Ethernet port. The Ethernet chip (optionally RTL8211EG) receives and parses the test data, storing it in memory. The FPGA chip 1, DAC chip 2, and power amplifier 4 form a transmission link 7. Specifically, the FPGA chip 1 reads and processes the test data, converts it into an analog signal via the DAC chip 2, and then transmits it as an RF signal via the power amplifier 4. Finally, an oscilloscope and other devices receive the RF signal and perform performance analysis.

[0026] The IQ demodulator 5, ADC chip 3, and FPGA chip 1 form feedback link 8. Specifically, the IQ demodulator 5 receives the RF signal coupled from the output of the power amplifier 4, converts it into an analog signal, and then the ADC converts it into a digital signal, which is input to the FPGA chip 1. The FPGA chip 1 processes the signal and feeds it back to the host computer, which then processes and analyzes the data using software. The MCU communicates with the FPGA chip 1 via an SPI interface. The FPGA chip 1 implements a register-mapped bus, receiving and parsing instructions from the MCU, decoding the MCU's read and write operations, and routing them to the corresponding functional modules within the FPGA chip 1, ensuring the stable operation of each functional module.

[0027] Thus, the system forms a dual-core architecture with "FPGA as the data processing core and MCU as the control core", and improves the efficiency and accuracy of DPD performance testing by implementing a flexible and controllable transmit and receive process through independent transmit link 7, feedback link 8 and MCU.

[0028] Specifically, FPGA chip 1 can be an XC7K325T series chip, such as the XC7K325T-2FFG900I, which has powerful parallel processing capabilities and can be used as an "execution engine" for data stream processing. FPGA chip 1 adopts an integrated circuit structure, which contains a large number of logic units and programmable resources.

[0029] Furthermore, the FPGA chip 1 has a data processing module 11. The system uses RAM as its memory, and the data processing module 11 uses a RAM control module to read, convert, and output the test data in the RAM memory. The FPGA chip 1 also has a feedback signal processing module 12, which processes the digital signals generated by the ADC chip 3 and feeds the processed signals back to the host computer.

[0030] Therefore, the RAM control module, DAC chip 2, and power amplifier 4 form the signal transmission link 7, while the IQ demodulator 5, ADC chip 3, and feedback signal processing module 12 form the signal feedback link 8.

[0031] In this application, DAC chip 2 can be a high-speed DAC such as MAX5868. ADC chip 3 can be a high-speed ADC such as AD9238.

[0032] Power Amplifier 4 consists of power amplification circuitry and a heat dissipation device, ensuring signal quality while operating at high efficiency. It features high power amplification and linearity, and utilizes a common RF power amplifier.

[0033] The MCU control module 6 serves as the "command center" for system status and configuration. It typically consists of a microcontroller and related peripheral circuits. The microcontroller can be an STM32F407 series chip, which has strong logic management capabilities. The MCU control module 6 communicates with the FPGA chip 1 via an SPI interface. The FPGA internally allocates a unified register mapping space, which the MCU reads and writes to via the SPI bus. The MCU initiates transmissions as the SPI master, and the FPGA responds as the slave. Each register address corresponds to a specific function, such as transmit / receive start / stop / refresh enable bits, RF frequency settings, and power amplifier 4 over-temperature alarm status bits.

[0034] This mechanism abstracts complex hardware control into simple register read and write operations, enabling configuration and status monitoring of all functional modules within the FPGA, and greatly reducing the complexity of hardware and software co-development.

[0035] In this application, the FPGA and MCU adopt a hierarchical task allocation strategy: the FPGA side undertakes all high-throughput, low-latency hard real-time tasks. Specifically, this includes parsing and encapsulating high-speed UDP / IP network protocols; real-time and accurate processing of transmitted and received data; driving high-speed parallel data interfaces for DAC (MAX5868) and ADC (AD9238); and precise timing control, such as symbol timing and frame synchronization.

[0036] The MCU side is responsible for soft real-time tasks with high complexity and relatively low real-time requirements. Specifically, this includes: running the embedded operating system and managing multi-task scheduling; responding to user configuration commands from the host computer via a web server (such as setting transmit / receive start / stop refresh, transmit power, and channel frequency); monitoring system health status (such as temperature, power supply voltage, and the status of each chip's phase-locked loop); handling abnormal events reported by the FPGA and executing complex fault recovery strategies.

[0037] Reference Figure 2Furthermore, the modular physical partitioning of each module device in this application has been further improved. A digital area 91, an analog area 92, and a power supply and heat dissipation area 94 are set on the circuit board 9. The digital area 91 is used to house the FPGA chip 1 and the MCU control module 6, the analog area 92 is used to house the DAC chip 2, the ADC chip 3, the power amplifier 4, and the IQ demodulator 5, and the power supply and heat dissipation area 94 is used to arrange the system's power supply module.

[0038] A shielded ground joint 93 is provided between the analog area 92 and the digital area 91 to achieve physical isolation between the two areas, cut off the noise coupling path on the plane of the circuit board 9, and further achieve isolation. Spatially isolating the sensitive analog part from the noisier digital part reduces the interference of digital noise on the analog signal.

[0039] The power supply and heat dissipation area 94 is located at the edge of the circuit board 9, placing heat sources such as heat sinks and power modules that may generate electromagnetic interference at the edge and away from sensitive radio frequency and clock circuits. At the same time, it facilitates the centralized wiring of power lines and ground lines, reducing loop area.

[0040] The implementation principle of this embodiment is as follows: This system adopts a heterogeneous dual-core architecture where FPGA and MCU work together. Through a hierarchical task allocation strategy, the FPGA undertakes high-throughput, low-latency hard real-time tasks, while the MCU is responsible for high-complexity, relatively low-real-time tasks, fully leveraging the advantages of both. A bus-based data interaction mechanism based on register mapping abstracts complex hardware control into simple register read / write operations, reducing the complexity of hardware and software co-development.

[0041] Simultaneously, the transmit and feedback links 8 are integrated onto a single hardware platform, forming a flexible and controllable optimization system. This allows for separate observation and comparative analysis of the RF output of the transmit link 7 and the return signal of the feedback link 8. Furthermore, both links can be flexibly verified and optimized for specific modules. This design not only improves the testing speed and flexibility of the DPD algorithm and reduces costs, but also facilitates iterative optimization of the algorithm, enhancing the overall performance and practicality of the system. Compared to existing technologies, this represents a significant improvement and enhancement in DPD algorithm testing.

[0042] The FPGA chip 1, DAC chip 2, ADC chip 3, power amplifier 4, IQ demodulator 5, and MCU control module 6 used in this application are all common devices on the market. Their internal structure and data operation principles are common knowledge to those skilled in the art, and this application will not provide a detailed description.

[0043] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A performance testing system for a predistortion algorithm based on a television exciter, characterized in that: include: FPGA chip (1), DAC chip (2), ADC chip (3), power amplifier (4), IQ demodulator (5) and MCU control module (6); the MCU control module (6) is communicatively connected to the FPGA chip (1) to control the operation of the FPGA chip (1); The FPGA chip (1), DAC chip (2), and power amplifier (4) form a signal transmission link (7); the FPGA chip (1) is connected to the host computer to receive test data and generate digital signals; the DAC chip (2) is connected to the FPGA chip (1) to convert digital signals into analog signals; and the power amplifier (4) is connected to the DAC chip (2) to emit radio frequency signals. The IQ demodulator (5), ADC chip (3) and FPGA chip (1) form a signal feedback link (8); the input of the IQ demodulator (5) is used to collect radio frequency signals and convert the radio frequency signals into analog signals; the ADC chip (3) is communicatively connected to the IQ demodulator (5) to convert analog signals into digital signals; the FPGA chip (1) is communicatively connected to the ADC chip (3) to process digital signals and feed them back to the host computer.

2. The performance testing system for the predistortion algorithm based on a television exciter according to claim 1, characterized in that: The system has a memory for storing test data. The FPGA chip (1) has a data processing module (11). The data processing module (11) is used to read, convert and output the test data in the memory. The data processing module (11), together with the DAC chip (2) and the power amplifier (4), forms a signal transmission link (7).

3. The performance testing system for the predistortion algorithm based on a television exciter according to claim 1, characterized in that: The FPGA chip (1) has a feedback signal processing module (12) for processing the digital signal generated by the ADC chip (3) and feeding the processed signal back to the host computer; the IQ demodulator (5), the ADC chip (3) and the feedback signal processing module (12) form a signal feedback link (8).

4. The performance testing system for the predistortion algorithm based on a television exciter according to claim 1, characterized in that: The input terminal of the IQ demodulator (5) is coupled to the output terminal of the power amplifier (4) for acquiring radio frequency signals.

5. The performance testing system for the predistortion algorithm based on a television exciter according to claim 1, characterized in that: The MCU control module (6) is connected to the FPGA chip (1) via the SPI interface.

6. The performance testing system for the predistortion algorithm based on a television exciter according to claim 1, characterized in that: The FPGA chip (1) is connected to the host computer via UDP protocol.

7. The performance testing system for the predistortion algorithm based on a television exciter according to claim 1, characterized in that: It also includes a circuit board (9), which has a digital area (91) and an analog area (92); the FPGA chip (1) and the MCU control module (6) are located in the digital area (91), and the DAC chip (2), ADC chip (3), power amplifier (4), and IQ demodulator (5) are all located in the analog area (92); A shielded ground gap (93) is provided between the analog area (92) and the digital area (91) to achieve isolation.

8. The performance testing system for the predistortion algorithm based on a television exciter according to claim 7, characterized in that: The circuit board (9) has a power supply and heat dissipation area (94) at its edge for arranging the power supply module of the system.

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