8-way CXP camera high-speed acquisition system based on double FMC daughter cards

Abstract

The utility model relates to data transmission technical field especially, more particularly to a kind of 8-way CXP camera high-speed acquisition system based on double FMC daughter card, comprising: FPGA main control board module, including PL end and PS end;Power switching module is connected with FPGA main control board module;Gigabit network interface module one end is connected with PL end, and the other end is connected with host computer;DDR memory module and GPIO interface module are connected with FPGA main control board module;Two FMC interfaces are all connected with a CXP FMC acquisition daughter card, CXP FMC acquisition daughter card has 4 CXP links, FMC interface supports four-way high-speed GT interface, and high-speed GT interface and CXP link connection are all connected with a CXP camera.The utility model is inserted in FPGA main control board module by two CXP FMC acquisition daughter card, has realized the compact integration of 8-way CXP camera, system structure is simple, small in size, is convenient for deployment and maintenance.

Description

Technical Field

[0001] This utility model relates to the field of data transmission technology, and in particular to a high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards. Background Technology

[0002] CoaXPress (CXP) is a leading data transmission standard for industrial and scientific cameras. It uses coaxial cable for high-speed point-to-point serial communication and is designed to replace the older Camera Link protocol. CXP is widely used in scientific research, industrial automation, medical imaging, and aerospace defense. Its ability to provide data rates up to 12.5Gbps per link, long-distance transmission, and power supply over a single cable has made it the standard choice for high-end camera interfaces. Furthermore, CXP supports multi-channel configurations, enabling higher data bandwidth through multiple coaxial cables, providing a more flexible and reliable solution for applications requiring high-performance data acquisition.

[0003] Currently, there are three main types of CXP data acquisition solutions on the market: The first type uses multiple PCIe acquisition cards, employing an industrial computer as the control unit. Multiple PCIe acquisition cards supporting the CXP protocol are inserted for camera connection and data processing. This method offers good scalability, supporting more cameras by adding acquisition cards. However, it also requires more PCIe slots, increasing system complexity and presenting challenges in heat dissipation and space management. The second type is based on a single FMC daughter card design. An FPGA carrier board with an FMC interface can connect to a 4-channel CXP FMC daughter card, enabling direct data processing on the FPGA. This design features low latency and high efficiency. However, this design is limited by the number of daughter cards and cannot meet the needs of multi-camera systems. The third type uses non-standard adapter boards, connecting multiple camera interfaces via ribbon cables or flying wires. While this can be effective in specific situations with hardware compatibility and space constraints, this method suffers from complex wiring, lower reliability, and difficulty in maintenance.

[0004] Therefore, there is an urgent need for a more integrated, reliable, and efficient solution that can overcome the shortcomings of the above-mentioned technical solutions, improve system integration, reduce external cabling and space requirements, support more camera data acquisition, and have flexible system scalability and convenient power management capabilities. Utility Model Content

[0005] In view of at least one of the above technical problems, the present invention provides an 8-channel CXP camera high-speed acquisition system based on dual FMC daughter cards, which adopts an integrated system to reduce wiring and space requirements.

[0006] According to a first aspect of this utility model, an 8-channel CXP camera high-speed acquisition system based on dual FMC daughter cards is provided, comprising:

[0007] The FPGA main control board module includes a PL terminal and a PS terminal, which are connected via an AXI bus; the PS terminal includes a network driver unit; the PL terminal includes a data acquisition unit, a protocol parsing unit, and a data buffer unit.

[0008] The power switching module is connected to the FPGA main control board module and converts the external input power into various voltages required by the system.

[0009] The gigabit Ethernet module connects to the PL terminal at one end and communicates with the host computer via Ethernet at the other end for data transmission and control command interaction.

[0010] The DDR memory module is connected to the FPGA main control board module and stores temporary data and program code.

[0011] The GPIO interface module is connected to the FPGA main control board module and is used to connect to external devices;

[0012] Two FMC interfaces are set on the FPGA main control board module. Each FMC interface is connected to a CXP FMC acquisition sub-card. The CXP FMC acquisition sub-card has 4 CXP links. The FMC interface supports four high-speed GT interfaces. One high-speed GT interface is connected to one CXP link. Each high-speed GT interface is connected to a CXP camera.

[0013] In some embodiments of this utility model, the CXP FMC acquisition daughter card also has an analog front-end circuit, which includes a cable equalizer and a driver. The analog front-end circuit compensates and shapes the differential signal output by the CXP FMC acquisition daughter card to obtain an analog signal, and outputs the analog signal to the FPGA main control board module.

[0014] In some embodiments of this utility model, the FPGA main control board module has a GT module for converting the serial data of the analog signal into parallel data. The GT module includes a clock and data recovery unit for outputting the on-path clock, an 8B / 10B decoding unit for decoding, and a high-speed serial-to-parallel conversion unit for converting serial data into parallel data.

[0015] In some embodiments of this utility model, the PL terminal also has a CXP Host protocol parsing unit. The CXP Host protocol parsing unit is implemented based on the CXP HOST IP Core and is used to identify and process the video data stream and its control information from the CXP camera, output downlink video data through the AXI Stream Video interface, receive configuration instructions from the PS terminal through the AXI Lite bus, and send control signals back to the CXP camera.

[0016] In some embodiments of this utility model, the FPGA main control board module has a number of data receiving engine units corresponding to the CXP camera, and each data receiving engine unit has a state machine and a deep FIFO structure.

[0017] In some embodiments of this utility model, the image data processed by the data receiving engine unit is written into the DDR memory module for storage via the AXI bus.

[0018] In some embodiments of this utility model, the PS terminal runs an embedded Linux operating system, integrates network drivers and custom hardware drivers, and manages the CXP HOST IP Core and data receiving engine unit of the PL terminal.

[0019] In some embodiments of this utility model, the CXP FMC acquisition daughter card also has a PoCXP power supply circuit, and a current and voltage monitoring circuit integrated on each CXP link for real-time acquisition of the voltage and current values ​​of the CXP link.

[0020] In some embodiments of this utility model, each of the CXP FMC acquisition daughter cards is equipped with four MicroBNC connectors at the front end for connecting four CXP coaxial cables.

[0021] In some embodiments of this utility model, the CXP FMC acquisition daughter card also has an SMA connector for receiving external trigger signals or outputting synchronization pulses, an EEPROM for storing the serial number, calibration parameters or user-defined information of the CXP FMC acquisition daughter card, and a dual-color LED indicator for displaying link status and fault information.

[0022] The beneficial effects of this utility model are as follows: By connecting the PL and PS ends of the FPGA via an AXI bus, this utility model provides a robust and efficient data transmission channel. The network driver unit integrated on the PS end ensures that the system can easily communicate with the host computer, while the PL end is responsible for data acquisition, protocol parsing, and data caching. The overall architecture greatly simplifies the data path, reduces latency, and improves the overall system performance. The introduction of the power switching module allows for flexible conversion of external power to various voltages required by the system, optimizing power management, reducing dependence on external power modules, and making the system more compact. The combination of the gigabit Ethernet module and the DDR memory module enables data to be quickly transmitted back via Ethernet and efficiently stored locally, greatly improving the efficiency of data processing and transmission. The GPIO interface module allows for easy connection of various external devices, accelerating the system integration process. Two FMC interfaces are located on the FPGA main control board, connecting with the CXP... The FMC acquisition daughter cards are connected, and each daughter card supports 4 CXP links, communicating with CXP cameras through a high-density, high-speed GT interface. Compared with traditional solutions, this design, which is integrated on the same board, eliminates the need for additional cables, improves signal integrity and system anti-interference capability, and makes the system more flexible and cost-effective in terms of scalability. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of an 8-channel CXP camera high-speed acquisition system based on dual FMC daughter cards in an embodiment of this utility model;

[0025] Figure 2 This is a logic diagram of the FPGA main control board module in an 8-channel CXP camera high-speed acquisition system based on dual FMC daughter cards, as described in this utility model embodiment.

[0026] Figure reference numerals: 01, Host computer; 1, FPGA main control board module; 11, PL terminal; 11a, Data acquisition unit; 11b, Protocol parsing unit; 11c, Data buffer unit; 12, PS terminal; 12a, Network driver unit; 13, AXI bus; 2, Power switching module; 3, Gigabit Ethernet module; 4, DDR memory module; 5, GPIO interface module; 6, FMC interface; 7, CXP FMC acquisition daughter card; 71, CXP link; 72, High-speed GT interface; 8, CXP camera. Detailed Implementation

[0027] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.

[0028] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] like Figure 1 , Figure 2 The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards shown includes:

[0031] The FPGA main control board module 1 includes a PL terminal 11 and a PS terminal 12, which are connected via an AXI bus 13. The PS terminal 12 includes a network driver unit 12a. The PL terminal 11 includes a data acquisition unit 11a, a protocol parsing unit 11b, and a data buffer unit 11c. The FPGA main control board module 1 undertakes the entire process from multi-channel camera data access, protocol parsing, stream splitting to final storage in DDR memory. The system adopts a highly integrated architecture design, giving full play to the advantages of the FPGA main control board module 1 in high-speed interface processing and parallel computing, and realizing the ability of high bandwidth, low latency, and multi-channel synchronous acquisition, meeting the stringent requirements of real-time performance and reliability in fields such as industrial inspection and machine vision.

[0032] Power switching module 2 is connected to FPGA main control board module 1 and converts external input power into various voltages required by the system.

[0033] The gigabit Ethernet module 3 connects to the PL terminal 11 on one end and communicates with the host computer 01 via Ethernet on the other end for data transmission and control command interaction.

[0034] DDR memory module 4 is connected to FPGA main control board module 1 to store temporary data and program code;

[0035] GPIO interface module 5 is connected to FPGA main control board module 1 and is used to connect external devices;

[0036] Two FMC interfaces 6 are located on the FPGA main control board module 1. Each FMC interface 6 is connected to a CXP FMC acquisition daughter card 7. The CXP FMC acquisition daughter card 7 has four CXP links 71. The FMC interface 6 supports four high-speed GT interfaces 72, with one high-speed GT interface 72 connected to one CXP link 71. Each high-speed GT interface 72 is connected to one CXP camera 8. The system is configured with a maximum of eight CXP cameras 8 supporting the CXP interface, labeled Camera0 to Camera7. To improve the modularity and signal integrity of the system, all cameras are divided into two groups: Camera0 to Camera3 are connected to the first CXP FMC acquisition daughter card 70, and Camera4 to Camera7 are connected to the second CXP FMC acquisition daughter card 71. Each FMC card receives the high-speed serial data stream from the corresponding camera through four independent CXP links 71, making full use of the high bandwidth characteristics of the CXP interface to achieve synchronous acquisition of multiple high-definition images.

[0037] This invention provides a robust and efficient data transmission channel by connecting the PL terminal 11 and PS terminal 12 of the FPGA via an AXI bus 13. The network driver unit 12a integrated in the PS terminal 12 ensures that the system can easily communicate with the host computer 01, while the PL terminal 11 is responsible for data acquisition, protocol parsing, and data caching. The overall architecture greatly simplifies the data path, reduces latency, and improves the overall system performance. The introduction of the power switching module 2 allows for flexible conversion of external power to various voltages required by the system, optimizing power management, reducing dependence on external power modules, and making the system more compact. The cooperation between the gigabit Ethernet module 3 and the DDR memory module 4 enables data to be quickly transmitted back via Ethernet and efficiently stored locally, greatly improving the efficiency of data processing and transmission. The GPIO interface module 5 allows for easy connection of various external devices, accelerating the system integration process. Two FMC interfaces 6 are located on the FPGA main control board and connect to the CXP. The FMC acquisition daughter card 7 is connected to each other, and each daughter card supports 4 CXP links 71. It communicates with the CXP camera 8 through a high-density, high-speed GT interface. Compared with traditional solutions, this design, which is integrated on the same board, eliminates the need for additional cables, improves signal integrity and system anti-interference capability, and makes the system more flexible and cost-effective in terms of scalability.

[0038] During high-frequency signal transmission, signal integrity is often affected by factors such as cable length, impedance mismatch, and signal attenuation. This can lead to data transmission errors and reduce the overall performance of the system. In some embodiments of this invention, the CXP FMC acquisition daughter card 7 also has an analog front-end circuit, which includes a cable equalizer and a driver. The analog front-end circuit compensates and shapes the differential signal output from the CXP FMC acquisition daughter card 7 to obtain an analog signal, and then outputs the analog signal to the FPGA main control board module 1. The analog front-end circuit is used to compensate and shape the signal after long-distance coaxial cable transmission, overcome high-frequency attenuation and inter-symbol interference, and ensure that the signal quality meets the FPGA reception requirements. The processed analog signal then enters the FPGA's dedicated GT high-speed transceiver channel.

[0039] Data is typically transmitted serially to maximize bandwidth utilization and simplify physical wiring. However, serial data needs to be converted into parallel data at the receiving end for more efficient processing and analysis. In some embodiments of this invention, the FPGA main control board module 1 includes a GT module for converting serial analog signal data into parallel data. The GT module includes a clock and data recovery unit for outputting the accompanying clock, an 8B / 10B decoding unit for decoding, and a high-speed serial-to-parallel conversion unit for converting serial data into parallel data. The high-speed serial-to-parallel conversion unit supports high-speed parallel processing of data, improving processing capability through parallel channels and significantly reducing latency and processing burden compared to traditional pure serial processing. The clock and data recovery unit ensures precise alignment of data and clock, reducing data jitter and bit error rate, and improving system reliability. In contrast, traditional methods may require more external devices for clock synchronization. The 8B / 10B decoding unit increases the robustness of the data link by providing DC balance and fast data locking characteristics. The integrated design of the GT module reduces hardware complexity, decreases the overall system size and power consumption, and improves the ease of maintenance and expansion.

[0040] Modern industrial applications place increasingly higher demands on camera interfaces, requiring more intelligent solutions to process video data streams and transmit control information simultaneously. The PL terminal 11 also features a CXP Host protocol parsing unit 11b, implemented based on the CXP HOST IP Core. This unit identifies and processes the video data stream and control information from the CXP camera 8, outputting downlink video data via the AXI Stream Video interface, receiving configuration commands from the PS terminal 12 via the AXI Lite bus, and sending control signals back to the CXP camera 8. Utilizing the AXI Stream Video interface to output downlink video data ensures efficient and low-latency video data transmission, reducing latency in the video signal processing chain compared to traditional methods. Receiving configuration commands via the AXI Lite bus and sending control signals back to the CXP camera 8 makes the system more flexible and efficient in operation. This integration reduces additional control lines and simplifies system design; the protocol parsing unit 11b is designed based on the general CXP HOST IP Core, which makes system upgrades and function expansion easier and reduces the complexity of maintenance and updates; the integrated protocol parsing scheme reduces the risk of data and control signals losing synchronization in multi-module systems and improves system robustness.

[0041] With the development of high-speed and multi-channel CXP cameras, data throughput has increased significantly. Traditional data receiving methods may face problems such as insufficient data stream management, limited buffer capacity, and inter-channel interference, especially in scenarios with high concurrent processing requirements. This often leads to data loss, increased latency, or system instability. The FPGA main control board module 1 contains a number of data receiving engine units corresponding to the number of CXP cameras. Each data receiving engine unit has a state machine and a deep FIFO structure. Each data receiving engine unit is directly connected to its corresponding CXP camera, ensuring the parallel processing capability of real-time data streams from multiple cameras. The deep FIFO structure provides ample storage space, effectively absorbing bursts or jitter in high-speed data streams, significantly improving data stream stability compared to simple shallow buffer structures. The state machine dynamically tracks the data receiving state, adjusting operations according to the current data stream conditions to ensure data integrity and adapt to different transmission rates. By combining the receiving control process with dynamic buffer management, this design effectively avoids packet loss due to data overflow or improper management, improving the overall system's data processing efficiency. On the data stream path, the parsed main video stream is split into eight independent data channels, namely Stream 0 to Stream 7. Each channel corresponds to the data output of one CXP camera 8. These eight data streams are buffered and scheduled by dedicated data receiving engine units. Each data receiving engine unit has an independent state machine and a deep FIFO structure, which can effectively manage the data traffic of each channel, prevent congestion and frame loss, and ensure the stable transmission of multiple concurrent data.

[0042] With the continuous improvement of image resolution and frame rate, the throughput of image data has increased significantly. Efficient data transmission and storage are crucial to ensuring system performance. Image data processed by the data receiving engine unit is written to the DDR memory module 4 for storage via the AXI bus 13. The AXI bus 13 can provide transmission rates of up to tens of GB / s. Compared with traditional low-bandwidth interfaces, its efficient parallel transmission mechanism significantly improves the speed and efficiency of data transmission. The large capacity of DDR memory supports the system in processing larger datasets without frequent storage device swapping or reliance on external storage, enhancing system flexibility and scalability. Through the standardized AXI interface, the system can be more easily scheduled and managed on the data bus, improving data access efficiency and facilitating real-time complex data processing and dynamic resource allocation. The RAM architecture of DDR memory supports fast data access and high-frequency storage operations, reducing bottlenecks caused by data storage latency and improving the overall system reliability and response speed. It should be noted that the DDR memory module 4 can be DDR4, DDR5, or other types of DDR memory modules. The system allocates 128MB of dedicated cache space to each CXP camera 8 for applications such as short-term video caching, anomaly backtracking, or local preview. This caching strategy optimizes the utilization efficiency of memory resources while ensuring data integrity.

[0043] In some embodiments of this invention, the PS terminal 12 runs an embedded Linux operating system, integrating network drivers and custom hardware drivers to manage the CXP Host IP Core and data receiving engine unit of the PL terminal 11. Linux's modular design and extensive hardware support allow the system to be easily expanded and adapted to various hardware environments, which typically requires complex firmware updates or hardware replacements in traditional systems. Its mature kernel driver library and community support reduce the time and complexity of custom driver development, ensuring the system can quickly support new hardware interfaces and protocols, which would be time-consuming and labor-intensive in traditional real-time operating systems. The integrated network driver supports multiple communication protocols, improving data transmission efficiency and the system's remote management capabilities, making it suitable for the needs of modern distributed and networked devices.

[0044] Through the AXI bus 13, the PS terminal 12 can configure and monitor the data flow channels inside the FPGA main control board module 1, coordinating the reception and buffering of data from the eight CXP cameras 8. After image data is processed by the GT module and the CXP Host protocol parsing unit 11b, it is transmitted to the data receiving engine unit via AXI Stream and finally written to the DDR memory module 4 managed by the PS terminal 12. The PS terminal 12 uses the DMA mechanism to efficiently move the buffered image data to the gigabit network port module 3 interface, realizing high-speed network backhaul. The host computer 01 communicates with the system through monitoring software developed in C#, supporting device scanning, camera parameter configuration, real-time image display, and data storage functions. The software automatically identifies camera information based on the API interface and XML configuration file provided by the manufacturer. Users can dynamically adjust the gain, exposure, and other parameters of each camera and view the eight video streams in real time. The entire system, from image acquisition, FPGA processing, embedded scheduling to host computer 01 visualization, achieves full-process autonomous control and efficient collaboration, with good real-time performance, configurability, and scalability.

[0045] Traditional coaxial cable connections may require additional dedicated power wiring, complicating system design and increasing cable clutter. In some embodiments of this invention, the CXP FMC acquisition daughter card 7 also features a PoCXP power supply circuit and a current-voltage monitoring circuit integrated on each CXP link 71 for real-time acquisition of voltage and current values. The four Micro BNC connectors aim to provide a stable and reliable signal transmission interface, while merging power and data transmission to reduce the number of cables, improve system integration and ease of use. The high-frequency performance and low reflection characteristics of the Micro BNC connectors optimize signal transmission and provide improved signal integrity.

[0046] In some embodiments of this invention, each CXP FMC acquisition daughter card 7 is equipped with four MicroBNC connectors at its front end for connecting four CXP coaxial cables. Micro BNC connectors are known for their compact size and excellent electrical performance, enabling high-density connections within a limited space. The Micro BNC design improves connection reliability and reduces signal reflection and transmission loss. By using Micro BNC connectors, the CXP FMC acquisition daughter card 7 can effectively support high-speed parallel transmission of multiple signals, optimizing physical space usage and improving overall transmission rate and signal quality, enabling the system to handle higher frequency signals and larger data volumes.

[0047] In some embodiments of this invention, the CXP FMC acquisition daughter card 7 also includes an SMA connector for receiving external trigger signals or outputting synchronization pulses, an EEPROM for storing the serial number, calibration parameters, or user-defined information of the CXP FMC acquisition daughter card 7, and a dual-color LED indicator for displaying link status and fault information. The SMA connector is used to receive external trigger signals or output synchronization pulses, ensuring time accuracy and functional synchronization between internal and external devices. These connectors are ideal due to their reliable connection and high-frequency performance, especially in applications requiring stringent electrical performance. The EEPROM is configured to meet the needs of storing and managing device information; by storing serial numbers, calibration parameters, or user-defined information, the EEPROM supports device identification and long-term stable operation. The dual-color LED indicator provides quick and intuitive feedback on device status; the indicator accurately displays link status and fault information, helping users quickly identify and resolve problems, thereby improving system reliability and maintenance efficiency.

[0048] Those skilled in the art should understand that this utility model is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of this utility model. Various changes and modifications can be made to this utility model without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed utility model. The scope of protection of this utility model is defined by the appended claims and their equivalents.

Claims

1. A high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards, characterized in that, include: The FPGA main control board module includes a PL terminal and a PS terminal, which are connected via an AXI bus; the PS terminal includes a network driver unit; the PL terminal includes a data acquisition unit, a protocol parsing unit, and a data buffer unit. The power switching module is connected to the FPGA main control board module and converts the external input power into various voltages required by the system. The gigabit Ethernet module connects to the PL terminal at one end and communicates with the host computer via Ethernet at the other end for data transmission and control command interaction. The DDR memory module is connected to the FPGA main control board module and stores temporary data and program code. The GPIO interface module is connected to the FPGA main control board module and is used to connect to external devices; Two FMC interfaces are set on the FPGA main control board module. Each FMC interface is connected to a CXP FMC acquisition sub-card. The CXP FMC acquisition sub-card has 4 CXP links. The FMC interface supports four high-speed GT interfaces. One high-speed GT interface is connected to one CXP link. Each high-speed GT interface is connected to a CXP camera.

2. The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards according to claim 1, characterized in that, The CXP FMC acquisition daughter card also has an analog front-end circuit, which includes a cable equalizer and a driver. The analog front-end circuit compensates and shapes the differential signal output by the CXP FMC acquisition daughter card to obtain an analog signal, and outputs the analog signal to the FPGA main control board module.

3. The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards according to claim 2, characterized in that, The FPGA main control board module has a GT module inside, which is used to convert the serial data of the analog signal into parallel data. The GT module includes a clock and data recovery unit for outputting the on-path clock, an 8B / 10B decoding unit for decoding, and a high-speed serial-to-parallel conversion unit for converting serial data into parallel data.

4. The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards according to claim 1, characterized in that, The PL terminal also has a CXP Host protocol parsing unit, which is implemented based on the CXP HOST IP Core. It is used to identify and process the video data stream and its control information from the CXP camera, output downlink video data through the AXI StreamVideo interface, receive configuration instructions from the PS terminal through the AXI Lite bus, and send control signals back to the CXP camera.

5. The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards according to claim 4, characterized in that, The FPGA main control board module has a number of data receiving engine units corresponding to the number of CXP cameras. Each data receiving engine unit has a state machine and a deep FIFO structure.

6. The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards according to claim 5, characterized in that, The image data processed by the data receiving engine unit is written to the DDR memory module for storage via the AXI bus.

7. The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards according to claim 5, characterized in that, The PS terminal runs an embedded Linux operating system, integrates network drivers and custom hardware drivers, and manages the CXP HOST IP Core and data receiving engine unit of the PL terminal.

8. The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards according to claim 1, characterized in that, The CXP FMC acquisition daughter card also has a PoCXP power supply circuit, and a current and voltage monitoring circuit integrated on each CXP link for real-time acquisition of the voltage and current values ​​of the CXP link.

9. The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards according to claim 1, characterized in that, Each of the CXP FMC acquisition daughter cards is equipped with four Micro BNC connectors at the front end for connecting four CXP coaxial cables.

10. The high-speed acquisition system for an 8-channel CXP camera based on dual FMC daughter cards according to claim 1, characterized in that, The CXP FMC acquisition daughter card also has an SMA connector for receiving external trigger signals or outputting synchronization pulses, an EEPROM for storing the serial number, calibration parameters or user-defined information of the CXP FMC acquisition daughter card, and a dual-color LED indicator for displaying link status and fault information.

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