A directional sound circuit and a directional sound system

Abstract

A directional sound circuit and system, relating to the field of directional sound technology, includes: a carrier generation circuit; an audio input circuit; a modulation circuit, the modulation circuit including an analog multiplier, the output terminal of the carrier generation circuit being connected to the input terminal of a first transistor of the analog multiplier, and the output terminal of the audio input circuit being connected to the input terminal of a second transistor of the analog multiplier; and a filtering circuit, the input terminal of which is connected to the output terminal of the analog multiplier. This application utilizes an analog multiplier chip to construct the hardware circuit, achieving a good balance between cost, performance, and system efficiency.

Description

Technical Field

[0001] This utility model relates to the field of directional sound technology, specifically a directional sound circuit and a directional sound system. Background Technology

[0002] Directional sound technology is a technique that modulates audible sound signals onto a high-frequency ultrasonic carrier wave and utilizes the nonlinear effect of ultrasonic waves propagating in the air to reproduce the original audible sound. This achieves the effect of sound propagating in a direction like a flashlight beam, avoiding disturbance to residents. It is widely used in exhibitions, advertising, and personal audio spaces.

[0003] Currently, the mainstream implementation schemes fall into two categories:

[0004] One approach is the all-digital solution: This uses a high-performance digital signal processor (DSP) or field-programmable gate array (FPGA) to perform audio signal processing and modulation algorithms (such as amplitude shift keying, ASK) in the digital domain, and then outputs the signal via a high-speed digital-to-analog converter (DAC) and a traditional Class AB audio power amplifier. This solution offers excellent performance and high modulation accuracy. However, the high cost of high-performance DSP / FPGA chips and the high technical barrier required for their development (requiring specialized digital signal processing knowledge and programming skills) further complicates the process. Additionally, the inherently low efficiency of Class AB amplifiers leads to a significant amount of electrical energy being converted into heat, resulting in high system power consumption and necessitating additional heat dissipation design. Therefore, this solution suffers from high hardware costs, significant development challenges, and high system power consumption.

[0005] The second approach is a purely analog solution: using a large number of discrete components (such as transistors and operational amplifiers) to build modulation circuits (such as balanced modulators). This solution is less expensive, but because it involves many discrete components, each component has tolerances in its parameters. The accumulation of errors from multiple components can lead to inconsistent circuit performance. During mass production, each device requires tedious debugging to achieve optimal performance, resulting in poor consistency, low reliability, and complex debugging, making it difficult to achieve mass production and practical application.

[0006] Therefore, there is an urgent need to develop a directional sound circuit and directional sound system to solve the problems in the existing technology. Utility Model Content

[0007] The purpose of this invention is to provide a directional sound circuit and a directional sound system, which solves the problem that existing solutions mentioned in the background art are difficult to balance between cost and performance by applying an analog multiplier.

[0008] To achieve the above objectives, this utility model provides the following technical solution:

[0009] A directional sound circuit, comprising:

[0010] Carrier generation circuit;

[0011] Audio input circuit;

[0012] A modulation circuit, comprising an analog multiplier, wherein the output terminal of the carrier generation circuit is connected to the input terminal of the first transistor of the analog multiplier, and the output terminal of the audio input circuit is connected to the input terminal of the second transistor of the analog multiplier;

[0013] A filter circuit, wherein the input terminal of the filter circuit is connected to the output terminal of the analog multiplier.

[0014] Furthermore, the analog multiplier includes:

[0015] Constant current source circuit;

[0016] A single differential amplifier, wherein the single differential amplifier is connected to the constant current source circuit and the single differential amplifier is connected to the audio input circuit;

[0017] A dual differential amplifier is connected to the single differential amplifier and to the carrier generation circuit.

[0018] Furthermore, the dual differential amplifier includes:

[0019] First transistor, second transistor, third transistor, and fourth transistor;

[0020] The collector of the first transistor is connected to the sixth pin, the base is connected to the eighth pin, and the emitter is connected to the collector of the fifth transistor.

[0021] The collector of the second transistor is connected to the twelfth pin, the base is connected to the tenth pin, and the emitter is connected to the collector of the fifth transistor.

[0022] The collector of the third transistor is connected to the sixth pin, the base is connected to the tenth pin, and the emitter is connected to the collector of the sixth transistor.

[0023] The collector of the fourth transistor is connected to the twelfth pin, the base is connected to the eighth pin, and the emitter is connected to the collector of the sixth transistor.

[0024] The single differential amplifier includes:

[0025] The fifth transistor has its base connected to the fourth pin and its emitter connected to the constant current source circuit.

[0026] The sixth transistor has its base connected to the first pin and its emitter connected to the constant current source circuit.

[0027] Furthermore, the constant current source circuit includes:

[0028] The seventh transistor has its collector connected to the emitter of the fifth transistor, its base connected to the fifth pin, and its emitter connected to the fourteenth pin via a resistor.

[0029] The eighth transistor has its collector connected to the emitter of the sixth transistor, its base connected to the fifth pin, and its emitter connected to the fourteenth pin via a resistor.

[0030] The diode has its positive terminal connected to the fifth pin and its negative terminal connected to the first and fourth pins via a resistor.

[0031] Furthermore, a third pin is provided between the collector of the seventh transistor and the emitter of the fifth transistor;

[0032] A second pin is provided between the collector of the eighth transistor and the emitter of the sixth transistor;

[0033] The second and third pins are used for connecting external resistors.

[0034] Furthermore, it also includes:

[0035] A single-ended to differential circuit, wherein the input terminal of the single-ended to differential circuit is connected to the output terminal of the filter circuit;

[0036] An audio power amplifier circuit is connected to the output terminal of the single-ended to differential circuit.

[0037] Furthermore, the audio power amplifier circuit includes a Class D audio power amplifier.

[0038] Furthermore, the audio input circuit includes a filter, and the carrier generation circuit includes a controller and a filter, or the carrier generation circuit includes a controller, a carrier generator, and a filter.

[0039] Furthermore, it also includes an ultrasonic transducer array, the input of which is connected to the output of the audio power amplifier circuit.

[0040] A directional sound system includes the aforementioned directional sound circuit.

[0041] Compared with the prior art, the beneficial effects of this utility model are:

[0042] (1) The application uses an analog multiplier chip, which is a general-purpose and inexpensive analog chip, far lower than the cost of DSP / FPGA.

[0043] (2) This application is a hardware circuit, and its operation is not affected by MCU software crashes or interrupt delays, and it has strong anti-interference ability.

[0044] (3) The modulation process of this application is physical electronic motion, with almost no delay, and is not limited by software processing speed or sampling theorem.

[0045] In summary, this application achieves a good balance between cost, performance, and system efficiency.

[0046] Other features and advantages of this utility model will be disclosed in detail in the following specific embodiments and accompanying drawings. Attached Figure Description

[0047] Figure 1 This is a block diagram of the overall hardware structure of the system;

[0048] Figure 2 This is a circuit diagram for a single-ended to differential circuit.

[0049] Figure 3 This is a diagram simulating the internal structure of a multiplier;

[0050] Figure 4 Circuit replacement module diagram for an analog multiplier;

[0051] Figure 5 This is a simulation circuit diagram for a multiplier.

[0052] Figure 6 The simulation waveform diagram of the multiplier (1≥Ma≥0);

[0053] Figure 7 The simulation waveform diagram of the analog multiplier (Ma≥1);

[0054] Figure 8 This is a topology diagram of a Sallen-Key low-pass filter;

[0055] Figure 9 Simulation circuit diagram of a 20kHz fourth-order Butterworth filter;

[0056] Figure 10 The simulation results for a 20kHz fourth-order Butterworth filter are shown in the figure.

[0057] Figure 11 The simulation results for a 40kHz fourth-order Butterworth filter are shown in the figure.

[0058] Figure 12 This is a topology diagram of a second-order bandpass MFB filter;

[0059] Figure 13 The simulation circuit diagram of an eighth-order Chebyshev bandpass filter;

[0060] Figure 14 The simulation results of an eighth-order Chebyshev bandpass filter are shown in the figure.

[0061] Figure 15 This is a diagram showing the resonant frequency analysis of a single transducer. Detailed Implementation

[0062] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention.

[0063] A directional sound circuit, such as Figure 1 As shown, it includes:

[0064] Carrier generation circuit;

[0065] Audio input circuit;

[0066] A modulation circuit, comprising an analog multiplier, wherein the output of the carrier generation circuit is connected to the input of the first transistor Q1 of the analog multiplier, and the output of the audio input circuit is connected to the input of the second transistor Q2 of the analog multiplier;

[0067] A filter circuit, wherein the input terminal of the filter circuit is connected to the output terminal of the analog multiplier;

[0068] A single-ended to differential circuit, wherein the input terminal of the single-ended to differential circuit is connected to the output terminal of the filter circuit;

[0069] An audio power amplifier circuit is connected to the output terminal of the single-ended to differential circuit.

[0070] In this embodiment, the analog multiplier is a four-quadrant analog multiplier, the input terminal of the first transistor Q1 is the X input terminal of the analog multiplier, and the input terminal of the second transistor Q2 is the Y input terminal of the analog multiplier.

[0071] This application utilizes an analog multiplier, connecting the carrier signal and modulation signal to corresponding pins of an analog multiplier chip. The analog multiplier chip internally performs analog multiplication on the two input signals and precisely sets its carrier suppression point to maximize carrier output suppression by adjusting the RP potentiometer. The underlying principle is to utilize the symmetry of the double-balanced differential structure to cancel each other out at the differential output. Externally, this is achieved by using an external carrier zero-adjustment potentiometer to compensate for the inherent asymmetry of the transistors within the chip, optimizing this cancellation effect and minimizing carrier leakage. Ultimately, a double-sideband suppressed carrier (DSB-SC) signal is directly generated at its output.

[0072] This application uses the modulation circuit as an analog multiplier, which has the following advantages:

[0073] ① Excellent real-time performance: The modulation process is a physical electronic movement with almost no delay, and is not limited by software processing speed or sampling theorem.

[0074] ② High stability: As a hardware circuit, its operation is not affected by MCU software crashes or interrupt delays, and it has strong anti-interference capabilities.

[0075] ③Low cost: Analog multiplier chips are general-purpose and inexpensive analog chips, with costs far lower than DSP / FPGA.

[0076] ④ It overcomes the problems of high cost and high difficulty of digital solutions and poor consistency and difficult debugging of pure analog solutions, and achieves a balance between high performance and low cost.

[0077] Specifically, such as Figure 2 As shown, in this embodiment, the analog multiplier includes:

[0078] Constant current source circuit;

[0079] A single differential amplifier, wherein the single differential amplifier is connected to the constant current source circuit and the single differential amplifier is connected to the audio input circuit;

[0080] A dual differential amplifier is provided, which is connected to the single differential amplifier and to the carrier generation circuit. The output of the dual differential amplifier serves as the output of an analog multiplier.

[0081] The dual differential amplifier includes:

[0082] The first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4;

[0083] The collector of the first transistor Q1 is connected to the sixth pin, the base is connected to the eighth pin, and the emitter is connected to the collector of the fifth transistor Q5.

[0084] The collector of the second transistor Q2 is connected to the twelfth pin, the base is connected to the tenth pin, and the emitter is connected to the collector of the fifth transistor Q5.

[0085] The collector of the third transistor Q3 is connected to the sixth pin, the base is connected to the tenth pin, and the emitter is connected to the collector of the sixth transistor Q6.

[0086] The collector of the fourth transistor Q4 is connected to the twelfth pin, the base is connected to the eighth pin, and the emitter is connected to the collector of the sixth transistor Q6.

[0087] The single differential amplifier is used to drive the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4, including:

[0088] The fifth transistor Q5 has its base connected to the fourth pin and its emitter connected to the constant current source circuit.

[0089] The sixth transistor Q6 has its base connected to the first pin and its emitter connected to the constant current source circuit.

[0090] The constant current source circuit includes:

[0091] The seventh transistor Q7 has its collector connected to the emitter of the fifth transistor Q5, its base connected to the fifth pin, and its emitter connected to the fourteenth pin through a resistor.

[0092] The eighth transistor Q8 has its collector connected to the emitter of the sixth transistor Q6, its base connected to the fifth pin, and its emitter connected to the fourteenth pin through a resistor.

[0093] The diode has its positive terminal connected to the fifth pin and its negative terminal connected to the first and fourth pins via a resistor.

[0094] The fourteenth pin is the negative power supply terminal; the fifth pin is connected to an external resistor to bias the current and mirror the current.

[0095] A third pin is provided between the collector of the seventh transistor Q7 and the emitter of the fifth transistor Q5;

[0096] A second pin is provided between the collector of the eighth transistor Q8 and the emitter of the sixth transistor Q6;

[0097] The second and third pins are used to connect external resistors to generate current negative feedback for the fifth transistor Q5 and the sixth transistor Q6, which can adjust the signal gain of the multiplier and extend the linear dynamic range of the input voltage.

[0098] The working process of the simulated multiplier in this application is as follows:

[0099] Input: A low-frequency modulated signal is input to the linear transconductance stage (pin 1 / pin 4) and is converted into a differential current controlled by it.

[0100] Switch control: A high-frequency carrier signal is input to the switching stage (pin 8 / pin 10), which acts like a high-speed electronic switch, alternately guiding the flow of the aforementioned differential current.

[0101] Multiplication: At the output node (pin 6 / pin 12), the guided currents are combined into a new signal. The amplitude of this signal varies with the low-frequency modulation signal, while its frequency and phase are determined by the high-frequency carrier signal. Essentially, this completes the multiplication operation between the low-frequency modulation signal and the high-frequency carrier signal.

[0102] Suppressed carrier: Due to the perfect symmetry of the circuit, the output does not contain a carrier component when there is no modulation signal.

[0103] Output filtering: The differential output is filtered through a capacitor to extract the required upper and lower sidebands (DSB-SC signals) and filter out unnecessary DC components.

[0104] In this embodiment, the carrier generation circuit includes a controller and a filter. The output terminal of the controller is connected to the input terminal of the filter, and the output terminal of the filter serves as the output terminal of the carrier generation circuit. In this embodiment, the carrier signal is a fixed-frequency 40kHz sine wave signal. An STM32F10RET6 microcontroller (MCU) generates a 40kHz sine wave signal through its internal DAC channel. After passing through a 40kHz low-pass filter to remove the high-order harmonic components generated by the DAC, a pure 40kHz sine wave is output as the carrier signal and sent to the carrier input terminal of the analog multiplier. By using the internal DAC of the microcontroller (MCU) to generate the carrier, additional carrier generation circuits such as single-precision timers are eliminated, reducing cost and complexity.

[0105] Optionally, the carrier generation circuit can also be 1, wherein the controller is used to control the start and stop of the carrier generator, and the carrier generator includes an independent crystal oscillator circuit or silicon oscillator chip, which can generate a more accurate and stable 40kHz sine wave carrier, suitable for occasions with extremely high requirements for carrier frequency accuracy and stability.

[0106] This application leverages the programmability of the MCU to integrate more complex control algorithms. For example, it can introduce environmental sensors such as temperature and humidity to dynamically adjust parameters to compensate for the effects of changes in sound speed, or achieve dynamic beamforming to adjust the directivity of the sound beam to a certain extent. The implementation of dynamic beamforming requires multi-channel output, and the principle is similar to the beamforming weight vector calculation in the Baolun Electronics patent.

[0107] The audio input circuit includes a filter, and the output of the filter serves as the output of the audio input circuit. In this embodiment, the audio input circuit receives the original audible sound signal and passes it through a 20kHz low-pass filter circuit to filter out high-frequency noise and unwanted harmonics outside the audio range before sending it to the modulation signal input of the analog multiplier.

[0108] In this embodiment, the DSB-SC signal output by the analog multiplier chip contains unwanted harmonic components generated by modulation. Therefore, it is passed through a 30kHz-50kHz bandpass filter circuit to filter out these noises, retaining a pure DSB-SC signal. Subsequently, in order to match the optimal input mode of the subsequent Class D power amplifier and improve common-mode interference immunity, a single-ended to differential circuit is used to convert the single-ended signal into a differential signal, thereby improving the dynamic range and signal-to-noise ratio of the signal.

[0109] Specifically, the 30kHz-50kHz filter circuit is existing technology and will not be described in detail in this application.

[0110] Optionally, although this embodiment uses DSB-SC as the main modulation method, other forms of modulation signals, such as ordinary AM signals or SSB signals, can be generated by adjusting the bias of the analog multiplier or adding appropriate filtering circuits, in order to meet the requirements of different application scenarios for sound quality and efficiency.

[0111] like Figure 3 As shown, the single-ended to differential circuit includes a first operational amplifier U4A and a second operational amplifier U4B. The non-inverting input of the first operational amplifier U4A is connected to a 6V voltage, the inverting input is connected to the output of an analog multiplier, and the output is output. The non-inverting input of the second operational amplifier U4B is connected to a 6V voltage, the inverting input is connected to the output of the first operational amplifier U4A, and the output is output. Optionally, the single-ended to differential circuit can refer to existing technology, which will not be described in detail in this application.

[0112] In this embodiment, the Class D audio power amplifier is model TPA3255DDVR. This chip supports mono-bridged load mode, enabling multiple internal output stages to be connected in parallel to drive a single load, thereby providing high output power (up to several hundred watts) sufficient to drive an ultrasonic transducer array. Simultaneously, this type of amplifier has extremely high switching efficiency (typically exceeding 90%), significantly reducing system heat loss and eliminating the need for large heat dissipation devices, thus facilitating system miniaturization.

[0113] Class D amplifiers are extremely efficient (typically >90%), far exceeding the efficiency of traditional Class AB amplifiers. This significantly reduces system power consumption and heat generation, eliminating the need for large heat sinks and allowing for a very compact system design. This solves the problems of high power consumption and high heat generation in all-digital solutions for Class AB amplifiers.

[0114] Optionally, the Class D audio power amplifier can be replaced with any other chip model that supports single-channel bridged load operation and provides sufficient output power. The inductor and capacitor parameters of the output stage LC filter should be optimized based on the impedance-frequency characteristics of the actual transducer array to achieve efficient power transfer and suppress electromagnetic interference.

[0115] Finally, the highly amplified electrical signal drives an ultrasonic transducer array, typically composed of multiple 40kHz piezoelectric ceramic transducers arranged in a specific pattern. The array design can reference an arc-shaped arrangement to enhance directivity. The ultrasonic transducer array converts this into mechanical vibrations, emitting a highly directional ultrasonic beam. This ultrasonic wave self-demodulates in the air due to nonlinear effects, restoring the original audible sound. The arrangement of the transducer array helps to further concentrate the sound beam and improve the directivity effect.

[0116] In this embodiment, the low-pass and band-pass filters can be passive RC / LC filters or active filters composed of operational amplifiers. Active filters can provide better out-of-band rejection performance and a steeper roll-off characteristic, but the cost is slightly higher. The choice can be made based on the requirements for signal purity. In addition, with technological advancements, highly integrated directional acoustic modules can also be considered as the final output stage of the system to further simplify the design and ensure acoustic performance, but the cost may increase accordingly.

[0117] In circuit simulation software, an analog multiplier modulation circuit module is constructed. An analog multiplier is an active nonlinear device that multiplies two analog signals (voltage or current). Its main function is to multiply two uncorrelated signals, meaning the output signal is proportional to the product of the two input signals. The multiplier modulation circuit is a four-quadrant multiplier chip based on the basic principle of a double-differential-pair analog multiplier. It is a core component in amplitude modulation circuits, but this component is not available in the simulation component database. Therefore, the internal structure diagram of the analog multiplier can be created in the editing window of the circuit simulation software platform. Relevant options can be set, and after generating the sub-circuit, it can be added to a custom database and saved. The internal structure diagram of the analog multiplier is attached. Figure 2 As shown, the sub-circuit replacement module is defined as attached. Figure 4 As shown.

[0118] In the circuit simulation software, select the necessary peripheral circuit components for the multiplier module, and create a double-sideband amplitude modulation simulation circuit simulating the multiplier, as shown in the attached diagram. Figure 5As shown. In amplitude modulation (AM), the carrier signal is applied to the input terminals of Q1 and Q4, i.e., pins IO8 and IO10. The modulation signal is applied to the differential amplifiers Q5 and Q6, i.e., pins IO1 and IO4. External resistors are connected to pins IO2 and IO3 to expand the dynamic range of the modulation signal. The modulated signal is output from the two collectors of the dual differential amplifier. Resistors R3 and R4 connected to the positive power supply circuit are used for voltage division to provide the base bias voltage for transistors Q1-Q4 inside the multiplier; the negative power supply is supplied to the base bias voltage for transistors Q5 and Q6 inside the multiplier through the voltage division of RP, R5, R6, and R7, R8. RP is a carrier zero-adjustment potentiometer; adjusting RP makes the circuit symmetrical to reduce the carrier signal output; R10 and R11 are the load resistors at the output terminals. Resistor R1 connected to the IO2 and IO3 terminals expands the linear dynamic range of the analog multiplier and controls the gain of the multiplier.

[0119] ① The carrier signal is a 0.5Vrms / 40kHz sine wave controlled by V1, which is applied to the input terminals IO8 and IO10 of the multiplier through capacitors C2, C3 and R2.

[0120] ② The modulation signal is a 0.5Vrms / 1kHz sine wave controlled by V1, which is applied to the input terminals IO1 and IO4 of the multiplier through capacitor C1 and resistors R5 and R7.

[0121] ③ The output signal is output through C4.

[0122] The waveform obtained through simulation is shown in the attached figure. Figure 6 Adjusting the balancing potentiometer RP reveals that the amplitude of the high-frequency carrier signal and the modulating signal exhibit the same variation pattern; that is, the carrier amplitude changes according to the signal's pattern. The amplitude modulation coefficient is Ma = |Vmmax - Vmmin / Vmmax + Vmmin| × 100%. Clearly, the attached... Figure 6 At this point, 1 ≥ Ma ≥ 0. If Ma ≥ 1, then an additional condition will occur. Figure 7 Waveform. As can be seen from the figure, the envelope shape of the modulated wave is different from that of the amplitude-modulated signal, resulting in severe envelope distortion. This should be avoided as much as possible in practical applications, ensuring that the amplitude modulation coefficient is between 0 and 1.

[0123] Detailed simulation analysis using circuit simulation software effectively verified the feasibility and superiority of the core modulation circuit of this invention. Simulation results confirmed that the adopted analog multiplier architecture can stably generate DSB-SC signals with high carrier rejection ratios and low distortion. This provides precise theoretical basis and data support for component selection, parameter determination, and debugging objectives in actual PCB design, significantly reducing R&D risks and timelines.

[0124] The 20kHz low-pass filter circuit employs a fourth-order Butterworth low-pass filter with maximum flatness within the passband, aiming for a cutoff frequency of 25kHz. Implementation method: cascading two identical second-order Sallen-Key low-pass filters. This is due to its advantages of high input impedance, low output impedance, and ease of design and adjustment. The fourth-order filter is implemented by cascading two second-order filters. The Sallen-Key low-pass filter topology is attached. Figure 8 .

[0125] For a fourth-order Butterworth filter, the quality factor Q of each stage needs to be determined by looking up a table.

[0126] From the table, we find that Q1=0.541 for the first level and Q2=1.306 for the second level.

[0127] The cutoff frequency fc for each stage is 25 kHz.

[0128] The calculation formula for the Sallen-Key circuit:

[0129] Cutoff frequency: (in )

[0130]

[0131] Based on the calculations, a fourth-order Butterworth filter circuit was built using circuit simulation software, as shown in the attached diagram. Figure 9 Open the signal analyzer function of the circuit simulation software and view the simulation results of the filter, as shown in the attached image. Figure 10 As can be seen, at 25kHz, the attenuation is about 4dB.

[0132] The 40kHz low-pass filter also uses a fourth-order Butterworth low-pass filter, with a design target of a 50kHz cutoff frequency. This effect can be achieved by simply modifying the parameters of the 20kHz low-pass filter circuit. Simulation results are attached. Figure 11 .

[0133] The 30kHz-50kHz bandpass filter circuit uses an eighth-order Chebyshev bandpass filter. The design goals are: center frequency 40kHz, passband bandwidth (BW) 20 kHz (i.e., passband range 30kHz to 50 kHz), and stopband requirement: attenuation ≥ 40 dB at 80kHz.

[0134] The eighth-order Chebyshev bandpass filter consists of four second-order bandpass MFB filters (as shown in the attached diagram). Figure 11 The second-order bandpass MFB filter topology is shown in the attached diagram, consisting of cascaded sections. Figure 12Because an eighth-order transfer function means there are eight poles, and each second-order section provides a pair of conjugate poles. After calculating the bandpass poles with software assistance, the coefficients of the four second-order sections, as well as the center frequency (f0) and quality factor (Q) for each section, are obtained. The four calculated second-order sections are then cascaded in order of increasing Q value. This places the most "smooth" (low Q) section first, helping to prevent the high-Q sections from saturating due to excessively large input signals and improving the dynamic range.

[0135] The calculation formula for a second-order bandpass MFB circuit: When C1=C2=C:

[0136] Center frequency: ;

[0137] Quality Factor: ;

[0138] Gain at center frequency: ;

[0139] The symbol indicates the opposite phase;

[0140] bandwidth: ;

[0141] Based on the calculations, an eighth-order Chebyshev bandpass filter circuit was constructed using circuit simulation software, as shown in the attached diagram. Figure 13 Open the signal analyzer function of the circuit simulation software and view the simulation results of the filter, as shown in the attached image. Figure 14 It can be seen that in the passband range of 30kHz to 50kHz, the center frequency is around 40kHz, and the attenuation at 80kHz is around 40dB.

[0142] The 20kHz low-pass filter circuit employs a fourth-order Butterworth low-pass filter with maximum flatness within the passband, aiming for a cutoff frequency of 25kHz. Implementation method: cascading two identical second-order Sallen-Key low-pass filters. This is due to its advantages of high input impedance, low output impedance, and ease of design and adjustment. The fourth-order filter is implemented by cascading two second-order filters. The Sallen-Key low-pass filter topology is attached. Figure 8 .

[0143] For a fourth-order Butterworth filter, the quality factor Q of each stage needs to be determined by looking up a table.

[0144] From the table, we find that Q1=0.541 for the first level and Q2=1.306 for the second level.

[0145] The cutoff frequency fc for each stage is 25 kHz.

[0146] The calculation formula for the Sallen-Key circuit:

[0147] • Cutoff frequency: ;

[0148] in, .

[0149] .

[0150] Based on the calculations, a fourth-order Butterworth filter circuit was built using circuit simulation software, as shown in the attached diagram. Figure 9 Open the signal analyzer function of the circuit simulation software and view the simulation results of the filter, as shown in the attached image. Figure 10 As can be seen, at 25kHz, the attenuation is about 4dB.

[0151] The 40kHz low-pass filter also uses a fourth-order Butterworth low-pass filter, with a design target of a 50kHz cutoff frequency. This effect can be achieved by simply modifying the parameters of the 20kHz low-pass filter circuit. Simulation results are attached. Figure 11 .

[0152] The 30kHz-50kHz bandpass filter circuit uses an eighth-order Chebyshev bandpass filter. The design goals are: center frequency 40kHz, passband bandwidth (BW) 20 kHz (i.e., passband range 30kHz to 50 kHz), and stopband requirement: attenuation ≥ 40 dB at 80kHz.

[0153] The eighth-order Chebyshev bandpass filter consists of four second-order bandpass MFB filters (as shown in the attached diagram). Figure 11 The second-order bandpass MFB filter topology is shown in the attached diagram, consisting of cascaded sections. Figure 12 Because an eighth-order transfer function means there are eight poles, and each second-order section provides a pair of conjugate poles. After calculating the bandpass poles with software assistance, the coefficients of the four second-order sections, as well as the center frequency (f0) and quality factor (Q) for each section, are obtained. The four calculated second-order sections are then cascaded in order of increasing Q value. This places the most "smooth" (low Q) section first, helping to prevent the high-Q sections from saturating due to excessively large input signals and improving the dynamic range.

[0154] The calculation formula for a second-order bandpass MFB circuit: When C1=C2=C:

[0155] Center frequency: ;

[0156] Quality Factor: ;

[0157] Gain at center frequency: ; where the symbol represents the opposite phase.

[0158] bandwidth: .

[0159] Based on the calculations, an eighth-order Chebyshev bandpass filter circuit was constructed using circuit simulation software, as shown in the attached diagram. Figure 13 Open the signal analyzer function of the circuit simulation software and view the simulation results of the filter, as shown in the attached image. Figure 14 It can be seen that in the passband range of 30kHz to 50kHz, the center frequency is around 40kHz, and the attenuation at 80kHz is around 40dB.

[0160] The ultrasonic transmitter array is the key component for achieving directional sound. This design uses 16mm diameter transducers, arranged horizontally in arrays of 14, 13, 14, 15, 14, 13, and 14 modules. Three modules are connected together to form a long, narrow array. Since the signal input to each ultrasonic transducer probe should be identical, a parallel connection is used instead of a series connection.

[0161] For testing the resonant frequency of a single transducer, a 40kHz sine wave signal was output from a signal generator and connected to the single transducer. A signal analyzer was then used to receive and analyze the signal emitted by the single transducer to obtain the resonant frequency. Figure 15 It can be seen that the resonant frequency of a single transducer is around 40kHz.

[0162] A strip-shaped transducer array module was connected to the output of a power amplifier using a high-efficiency Class D audio power amplifier integrated circuit module. Audio signals modulated by a computer using a 40kHz sine wave and 50Hz-20kHz audio frequencies were input into the high-efficiency Class D audio power amplifier integrated circuit module. In an anechoic chamber, a sound level meter was used to test the frequency response, directional attenuation, and maximum sound pressure level of the transducer array. The test results are shown in the table below.

[0163]

[0164]

[0165]

[0166] The test results show that:

[0167] The high-efficiency Class D audio power amplifier integrated circuit module, combined with the long strip transducer array module, shows little change in sound pressure level at different frequencies, exhibiting relatively stable performance.

[0168] The sound intensity of the self-demodulated signal exhibits significant pressure changes in the 0° and 15° directions, demonstrating its directional effect.

[0169] The high-efficiency Class D audio power amplifier driving the strip transducer array module provides sufficient power.

[0170] In summary, this application, through an innovative architecture combining a controller, an analog multiplier, and a Class D power amplifier, achieves the following objective and significant technical effects:

[0171] 1. Achieves the ultimate balance between cost and performance: BOM cost is significantly lower than that of all-digital solutions, saving the cost of high-end DSP / FPGA.

[0172] 2. Achieves high efficiency and low heat generation: The overall system efficiency is high, the efficiency of Class D power amplifier is >90%, the heat generation is low, and the structure is compact.

[0173] 3. Ensures high stability and reliability of the system: Key modulation functions are completed by hardware, with strong anti-interference ability and stable operation.

[0174] 4. Significantly reduces development and production difficulty: It mainly adopts the standard application circuit of mature chips, the principle is clear, and the debugging mainly revolves around the bias of the analog multiplier. The debugging is simple and easy to mass-produce.

[0175] 5. Retains good flexibility in functional expansion: The programmability of the MCU leaves room for intelligent system control, such as volume and mode switching.

[0176] 6. Effective directional sound generation is achieved: Through ultrasonic carrier modulation and transducer array, directional sound propagation is achieved, reducing interference.

[0177] A directional sound system includes the aforementioned directional sound circuit.

[0178] This invention provides a directional sound circuit and a directional sound system, which are simple in structure, easy to use, and highly reliable.

[0179] Although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A directional sound circuit, characterized in that, include: Carrier generation circuit; Audio input circuit; A modulation circuit, comprising an analog multiplier, wherein the output terminal of the carrier generation circuit is connected to the input terminal of the first transistor of the analog multiplier, and the output terminal of the audio input circuit is connected to the input terminal of the second transistor of the analog multiplier; A filter circuit, wherein the input terminal of the filter circuit is connected to the output terminal of the analog multiplier.

2. The directional sound circuit according to claim 1, characterized in that, The analog multiplier includes: Constant current source circuit; A single differential amplifier, wherein the single differential amplifier is connected to the constant current source circuit and the single differential amplifier is connected to the audio input circuit; A dual differential amplifier is connected to the single differential amplifier and to the carrier generation circuit.

3. A directional sound circuit according to claim 2, characterized in that, The dual differential amplifier includes: First transistor, second transistor, third transistor, and fourth transistor; The collector of the first transistor is connected to the sixth pin, the base is connected to the eighth pin, and the emitter is connected to the collector of the fifth transistor. The collector of the second transistor is connected to the twelfth pin, the base is connected to the tenth pin, and the emitter is connected to the collector of the fifth transistor. The collector of the third transistor is connected to the sixth pin, the base is connected to the tenth pin, and the emitter is connected to the collector of the sixth transistor. The collector of the fourth transistor is connected to the twelfth pin, the base is connected to the eighth pin, and the emitter is connected to the collector of the sixth transistor. The single differential amplifier includes: The fifth transistor has its base connected to the fourth pin and its emitter connected to the constant current source circuit. The sixth transistor has its base connected to the first pin and its emitter connected to the constant current source circuit.

4. A directional sound circuit according to claim 2, characterized in that, The constant current source circuit includes: The seventh transistor has its collector connected to the emitter of the fifth transistor, its base connected to the fifth pin, and its emitter connected to the fourteenth pin via a resistor. The eighth transistor has its collector connected to the emitter of the sixth transistor, its base connected to the fifth pin, and its emitter connected to the fourteenth pin via a resistor. The diode has its positive terminal connected to the fifth pin and its negative terminal connected to the first and fourth pins via a resistor.

5. A directional sound circuit according to claim 4, characterized in that, A third pin is provided between the collector of the seventh transistor and the emitter of the fifth transistor; A second pin is provided between the collector of the eighth transistor and the emitter of the sixth transistor; The second and third pins are used for connecting external resistors.

6. A directional sound circuit according to any one of claims 1-5, characterized in that, Also includes: A single-ended to differential circuit, wherein the input terminal of the single-ended to differential circuit is connected to the output terminal of the filter circuit; An audio power amplifier circuit is connected to the output terminal of the single-ended to differential circuit.

7. A directional sound circuit according to claim 6, characterized in that, The audio power amplifier circuit includes a Class D audio power amplifier.

8. A directional sound circuit according to claim 7, characterized in that, The audio input circuit includes a filter, and the carrier generation circuit includes a controller and a filter, or the carrier generation circuit includes a controller, a carrier generator, and a filter.

9. A directional sound circuit according to claim 7, characterized in that, It also includes an ultrasonic transducer array, the input of which is connected to the output of the audio power amplifier circuit.

10. A directional sound system, characterized in that, Includes the directional sound circuit as described in any one of claims 1-9.

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