PCB board structure for reducing short circuit rejection rate of inner layer of printed circuit board

Abstract

The utility model discloses a kind of PCB board structure for reducing printed circuit board inner layer short-circuit scrappage rate, including multilayer PCB board body, several punching areas are preset on the multilayer PCB board body, the size of the punching area is same with the size of punch pin, a windowed area is set in the position of each punching area of the copper layer of the multilayer PCB board body, and the size of the windowed area is greater than the size of the punching area.The utility model is optimized and designed to the structure of multilayer PCB board not less than 6, from the root, the problem that the copper scrap is caused by copper layer contact in the automatic punching process in prior art leads to inner layer short-circuit.

Description

Technical Field

[0001] This utility model relates to the field of printed circuit board (PCB) manufacturing technology, specifically to a PCB board structure that reduces the scrap rate of inner layer short circuits in printed circuit boards. Background Technology

[0002] In the field of printed circuit board (PCB) manufacturing, as electronic devices develop towards higher integration and complexity, multilayer PCBs with at least six layers are widely used because they can meet the requirements of high-density wiring. However, due to the large number of layers and complex structure, the production process of such products involves multiple steps such as pattern transfer, etching, lamination, and punching. Various quality defects are prone to occur during the production process, among which short circuits in the inner layers are one of the core problems leading to product scrap, significantly affecting production efficiency and product yield.

[0003] Production data statistics and fault analysis show that up to 50% of short-circuit anomalies occurring during the electrical testing phase of multilayer PCB products with at least six layers can be traced back to copper dust contamination in the inner layers. Further production process tracing and verification revealed that these copper dust particles primarily originate from the automatic punching process in the inner layers. In current PCB design and manufacturing models, all preset punching positions in the automatic punching process correspond to the copper layer areas of the PCB board. The punching process uses a cutting and extrusion method, during which the copper layer generates fine copper dust due to mechanical force. This copper dust easily falls into any interlayer gaps in the inner layers during production. As subsequent lamination processes occur, it becomes fixed within the board. When the product completes production and enters the electrical testing phase or is actually used, the copper dust forms conductive paths, causing short circuits in the inner layer circuitry, ultimately leading to product scrap and resulting in significant yield losses and increased production costs for the manufacturing company. Utility Model Content

[0004] In order to overcome the problem that copper dust is generated in the automatic punching process of multilayer PCB products with no less than 6 layers in the prior art due to the presence of copper layers at the punching position, which in turn causes short circuits and scrapping of the inner layers, this utility model provides a PCB board structure that reduces the scrapping rate of inner layers of printed circuit boards.

[0005] The technical solution of this utility model is as follows: A PCB board structure for reducing the scrap rate of inner layer short circuits in printed circuit boards includes a multilayer PCB board body. The multilayer PCB board body has a number of pre-set punching areas. The size of the punching area is the same as the size of the punch. The copper layer of the multilayer PCB board body has a window area at the position of each punching area, and the size of the window area is larger than the size of the punching area.

[0006] In a preferred embodiment of this utility model, the center point of the perforated area and the center point of the corresponding window area are on the same axis.

[0007] As a preferred embodiment of this utility model, the length and width dimensions of the window area are both 1-3 mil larger than the length and width dimensions of the punched area.

[0008] In a preferred embodiment of this utility model, the length and width of the window area are both 2 mil larger than the length and width of the punched area.

[0009] As a preferred embodiment of this utility model, the length and width dimensions of the window area are both 1 mil larger than the length and width dimensions of the perforated area.

[0010] As a preferred embodiment of this utility model, the length and width of the window area are both 3 mil larger than the length and width of the punched area.

[0011] As a preferred embodiment of this utility model, the short and long sides of the multilayer PCB board body are each pre-set with a number of uniformly distributed punched areas.

[0012] As a preferred embodiment of this utility model, a punching area is pre-set in the middle of the short side of the multilayer PCB board body, and three punching areas are evenly pre-set in the long side of the multilayer PCB board body.

[0013] As a preferred embodiment of this utility model, the number of layers of the multilayer PCB board body is not less than 6 layers.

[0014] As a preferred embodiment of this utility model, the number of layers in the multilayer PCB board body is less than 6.

[0015] Compared with the prior art, the beneficial effects of this utility model are as follows: This invention provides a window area at each punching location in the copper layer of a multilayer PCB board, removing the copper layer within the punching area. This ensures that the extrusion and cutting action of the automatic punching process acts only on the substrate, not the copper layer, fundamentally eliminating the conditions for copper shavings generation. This significantly reduces the risk of internal short circuits caused by copper shavings, directly improving product yield and reducing material waste, labor time loss, and rework costs due to short circuit scrap. Simultaneously, the size of the window area is larger than the size of the punching area (i.e., larger than the size of the punch), providing necessary error margin for the punching process. Even with slight positional deviations during punching, the punch can still fully act on the substrate within the window area, avoiding contact with surrounding unremoved copper layers, further ensuring no copper shavings are generated. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a PCB board structure for reducing the scrap rate of inner layer short circuits in a certain embodiment of the present invention. Figure 2 for Figure 1 Enlarged view of section A.

[0018] In the diagram, 1. Multilayer PCB board body; 2. Punching area; 3. Copper layer; 4. Windowed area. Detailed Implementation

[0019] To make the technical problem to be solved, the technical solution, and the beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. It is also declared that the embodiments described below are only for explaining this utility model and are not intended to limit this utility model.

[0020] It should be noted that the terms "installation," "setting," "connection," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly defined. Indications of orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used in the application's product, or the orientation or positional relationship commonly understood by those skilled in the art, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. "A plurality" means two or more, unless otherwise explicitly defined. "Several" means one or more, unless otherwise explicitly defined.

[0021] Please see Figure 1 , Figure 2The present invention provides a PCB board structure for reducing the scrap rate of inner layer short circuits in printed circuit boards, including a multilayer PCB board body 1, the multilayer PCB board body 1 having no less than 6 layers, a number of punched areas 2 pre-set on the multilayer PCB board body 1, the size of the punched area 2 being the same as the size of the punch, and a window area 4 opened in the copper layer 3 of the multilayer PCB board body 1 at the position of each punched area 2, and the size of the window area 4 being larger than the size of the punched area 2. By creating a window area 4 at each punching area 2 of the copper layer 3 in the multilayer PCB board body 1, the copper layer 3 within the punching area 2 is removed. This ensures that the extrusion and cutting action of the automatic punching process acts only on the substrate, not the copper layer 3, fundamentally eliminating the conditions for copper shavings generation. This significantly reduces the risk of internal short circuits caused by copper shavings, directly improving product yield and reducing material waste, time loss, and rework costs due to short circuit scrap. At the same time, the size of the window area 4 is larger than the size of the punching area 2 (i.e., larger than the size of the punch), providing necessary error redundancy space for the punching process. Even if there is a slight positional deviation during the punching process, the punch can still act completely on the substrate within the window area 4, avoiding contact with the surrounding copper layer 3 that has not been removed, further ensuring no copper shavings are generated.

[0022] It should be noted that this utility model is applicable not only to multilayer PCB board bodies 1 with no less than 6 layers, but also to multilayer PCB board bodies 1 with fewer than 6 layers. This utility model does not impose any limitations on this.

[0023] In one embodiment, the center point of the punched area 2 and the corresponding windowed area 4 are on the same axis. The coaxial design of the center point ensures that the windowed area 4 is evenly distributed around the punched area 2, avoiding insufficient window size on one side due to positional deviation. It also ensures that the punch remains on the substrate within the windowed area 4 regardless of the direction of slight deviation during the punching process, completely eliminating the risk of the punch contacting the copper layer 3.

[0024] In one embodiment, the length and width of the window area 4 are both 1-3 mil larger than the length and width of the punching area 2. This 1-3 mil size difference range can adapt to the precision requirements of different production scenarios. It can satisfy the error compensation of ordinary precision punching equipment (such as choosing a larger difference when the equipment positioning accuracy is low), while in high-precision equipment scenarios, a smaller difference can reduce excessive removal of the inner copper layer 3 of the PCB, balancing protection and material utilization. Simultaneously, by controlling the size difference within a reasonable range, excessive window size can prevent excessive loss of the inner copper layer 3, thus preventing a decrease in the local structural strength of the PCB or limitations in circuit layout, ensuring that the core functions of the product are not affected.

[0025] Preferably, the length and width of the window area 4 are both 2 mil larger than the length and width of the punched area 2. This 2 mil size difference (1 mil on each side) design avoids the risk of protection failure that may be caused by too small a difference, while also preventing the waste of copper layer 3 caused by too large a difference. Moreover, it can be achieved through conventional etching processes, thus balancing the protective effect and production economy.

[0026] Alternatively, the dimensions of the window area 4 are both 1 mil larger than those of the punching area 2. This 1 mil difference minimizes the area to be removed from the inner copper layer 3 while meeting the basic protection requirements of high-precision punching equipment. This is suitable for scenarios with extremely high requirements for the density of the inner PCB circuitry, avoiding interference with the surrounding circuitry layout and ensuring that the core electrical performance of the product is not affected.

[0027] Alternatively, the dimensions of the windowed area 4 are both 3 mil larger than those of the punched area 2. This 3 mil difference provides greater tolerance for errors in the punching process, effectively addressing scenarios with low equipment positioning accuracy, large operational errors, or significant dimensional fluctuations in mass production. It ensures that even with large deviations, the punch does not contact the copper layer 3, improving protective stability under complex production conditions. The larger window size reduces the stringent requirements for positioning accuracy during production, lowering the risk of protective failure due to process fluctuations. This makes it suitable for production scenarios with moderate equipment accuracy or large batch sizes, ensuring consistent copper chip protection.

[0028] Please see Figure 1 In one embodiment, a punching area 2 is pre-set in the middle of the short side of the multilayer PCB board body 1, and three punching areas 2 are evenly pre-set in the long side of the multilayer PCB board body 1. The layout of setting a single punching area 2 in the middle of the short side and three punching areas 2 evenly distributed in the long side meets the force balance requirements of the multilayer PCB board in the automatic punching process. The evenly distributed punching positions can avoid uneven force on the board caused by local concentrated punching, reduce the risk of board deformation or damage, and ensure the structural integrity of the PCB board.

[0029] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

[0030] The present utility model patent has been described above with reference to the accompanying drawings. Obviously, the implementation of the present utility model patent is not limited to the above-described manner. Any improvements made by adopting the inventive concept and technical solution of the present utility model patent, or the direct application of the inventive concept and technical solution of the present utility model patent to other occasions without modification, are all within the protection scope of the present utility model.

Claims

1. A PCB board structure for reducing the scrap rate of inner layer short circuits on a printed circuit board, comprising a multilayer PCB board body, wherein the multilayer PCB board body has a plurality of pre-set punched areas, the size of the punched areas being the same as the size of the punch, characterized in that, The copper layer of the multilayer PCB board body has a window area at the location of each punched area, and the size of the window area is larger than the size of the punched area.

2. The PCB board structure for reducing the scrap rate of inner layer short circuits on printed circuit boards according to claim 1, characterized in that, The center point of the perforated area and the center point of the corresponding window area are on the same axis.

3. The PCB board structure for reducing the scrap rate of inner layer short circuits on printed circuit boards according to claim 1, characterized in that, The length and width of the windowed area are both 1-3 mil larger than the length and width of the perforated area.

4. The PCB board structure for reducing the scrap rate of inner layer short circuits on printed circuit boards according to claim 1, characterized in that, The length and width of the windowed area are both 2 mil larger than the length and width of the perforated area.

5. The PCB board structure for reducing the scrap rate of inner layer short circuits on printed circuit boards according to claim 1, characterized in that, The length and width of the windowed area are both 1 mil larger than the length and width of the perforated area.

6. The PCB board structure for reducing the scrap rate of inner layer short circuits on printed circuit boards according to claim 1, characterized in that, The length and width of the windowed area are both 3 mil larger than the length and width of the perforated area.

7. The PCB board structure for reducing the scrap rate of inner layers of printed circuit boards according to claim 1, characterized in that, The short and long sides of the multilayer PCB board body are each pre-set with several evenly distributed punched areas.

8. The PCB board structure for reducing the scrap rate of inner layers of printed circuit boards according to claim 1, characterized in that, The multilayer PCB board body has a pre-set punched area in the middle of the short side, and three pre-set punched areas are evenly distributed along the long side of the multilayer PCB board body.

9. The PCB board structure for reducing the scrap rate of inner layers of printed circuit boards according to claim 1, characterized in that, The number of layers in the multilayer PCB board body is not less than 6.

10. The PCB board structure for reducing the scrap rate of inner layers of printed circuit boards according to claim 1, characterized in that, The number of layers in the multilayer PCB board body is less than 6.

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