Semiconductor device and memory device

Abstract

A semiconductor device and a memory device include a first transistor disposed on a first side of a substrate, and the first transistor includes a pair of first source / drain features. The semiconductor device includes a first interconnect structure disposed on a second side of the substrate opposite the first side. The semiconductor device includes a first memory element disposed on the second side, and the first memory element includes a first capacitor. The first memory element is electrically coupled to the first source / drain features through the first interconnect structure.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and memory devices. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). Generally, the increase in integration density comes from the continuous reduction of the minimum feature size, which allows more components to be integrated into a given area. Utility Model Content

[0003] Some embodiments described herein provide a semiconductor device. The semiconductor structure includes a first transistor disposed on a first side of a substrate, the first transistor including a pair of first source / drain features. The semiconductor device includes a plurality of first interconnect structures disposed on a second side of the substrate opposite the first side. The semiconductor device includes a first memory element disposed on the second side, wherein the first memory element includes a first capacitor. The first memory element is electrically coupled to one of the pair of first source / drain features through the plurality of first interconnect structures.

[0004] Some embodiments described herein provide a memory device. The memory device includes a first memory cell and a second memory cell adjacent to the first memory cell along a first lateral direction. The first memory cell includes a first transistor disposed on a front side of a substrate. The first memory cell includes a plurality of first interconnect structures disposed above the first transistor on the front side. The first memory cell includes a first memory element disposed on the front side, wherein the first memory element is electrically coupled in series to the first transistor through the plurality of first interconnect structures. The second memory cell includes a second transistor disposed on the front side and spaced apart from the first transistor along the first lateral direction. The second memory cell includes a plurality of second interconnect structures disposed on a rear side of the substrate opposite to the front side. The second memory cell includes a second memory element disposed on the rear side, wherein the second memory element is electrically coupled in series to the second transistor through the plurality of second interconnect structures.

[0005] Some embodiments described herein provide a semiconductor device. This semiconductor device includes a first transistor disposed on a first side of a substrate, the first transistor including a pair of first source / drain features. This semiconductor device includes a plurality of first interconnect structures disposed on a second side of the substrate opposite to the first side. This semiconductor device includes a first memory element disposed on the second side, wherein the first memory element includes a first capacitor. The first memory element is electrically coupled to one of the pair of first source / drain features through the plurality of first interconnect structures. The first transistor and the first memory element are configured to form a first memory cell having a first dimension in a lateral direction and a second dimension in a lateral direction, the second dimension being larger than the first dimension. Attached Figure Description

[0006] The best understanding of the embodiments of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 According to some embodiments of this disclosure, cross-sectional views of a portion or the entirety of an exemplary semiconductor device are each illustrated;

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 According to some embodiments, each is illustrated Figure 1 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 A portion of one or more of the exemplary semiconductor devices shown in one or more of the examples;

[0009] Figure 14 According to some embodiments of this disclosure, flowcharts of exemplary methods for manufacturing exemplary semiconductor devices are illustrated;

[0010] Figure 15 According to some embodiments of this disclosure, illustrations are provided for implementing... Figure 14 Example method flowcharts for one or more steps of a flowchart method;

[0011] Figure 16 According to some embodiments of this disclosure, three-dimensional perspective views of a portion or the entirety of an exemplary semiconductor device are illustrated;

[0012] Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23A , Figure 24A , Figure 25 , Figure 26 and Figure 27 According to some embodiments of this disclosure, each is illustrated in Figure 14 and Figure 15 During the various manufacturing stages of the method shown in the flowchart, Figure 16 A partial or complete cross-sectional view of an example semiconductor device;

[0013] Figure 23B and Figure 24B According to some embodiments disclosed herein, each is illustrated separately. Figure 23A and Figure 24A A top view of an example semiconductor device.

[0014] [Symbol Explanation]

[0015] 10: Front-side transistors / FSTs

[0016] 11: Inner isolation layer

[0017] 13: Nanostructure / Semiconductor Layer / Channel Layer

[0018] 14: Source / Drain Characteristics

[0019] 14D: Drain characteristics

[0020] 14S: Source Characteristics

[0021] 15: Front-side interconnect structure / FSLs

[0022] 16: Active gate structure

[0023] 17: Gate spacer

[0024] 18: Source / Drain Contacts

[0025] 20: Rear Interconnect Structure / BSLs

[0026] 40: Rear Memory Components / BSM

[0027] 42: IMD layer

[0028] 43: IMD layer

[0029] 44: Bottom Electrode

[0030] 46: Dielectric layer

[0031] 48: Top electrode

[0032] 50: First through hole

[0033] 52: Second through hole

[0034] 80: Front-side memory element / FSM

[0035] 82, 83: IMD layer

[0036] 84: Bottom Electrode

[0037] 86: Dielectric layer

[0038] 88: Top Electrode

[0039] 90: First through hole

[0040] 92: Second through hole

[0041] 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H: Device 102: Substrate

[0042] 102B: Rear side

[0043] 102F: Front

[0044] 108: Isolation Structure

[0045] 117: Interlayer dielectric layer / ILD layer

[0046] 120, 122, 124, 126, 128, 130, 140, 144, 148, 152: IMD layer; 145: Dielectric layer

[0047] 196: Dummy gate structure

[0048] 198: Dielectric Structure

[0049] 200: Method

[0050] 202,204,206,208,210,212,214: Operations

[0051] 252,254,256,258,260,262,264,266,268,270: Sub-operation 300: Semiconductor device

[0052] 302:Substrate

[0053] 302F: Front

[0054] 304: Semiconductor layer

[0055] 306: Semiconductor layer

[0056] 400, 400A, 400B, 400C: Fin Structure

[0057] 402: Graphic Mask

[0058] 410: Trench

[0059] 504: Isolation structure / isolation area

[0060] 600: Dummy gate structure

[0061] 602: Etching Stop Layer

[0062] 604: Hard mask

[0063] 702: Gate spacer

[0064] 704: Inner isolation layer

[0065] 706: Source / Drain Groove

[0066] 802: Source / Drain Characteristics

[0067] 806: Interlayer Dielectric / ILD

[0068] 900: Active gate structure

[0069] 902: Source / Drain Contact

[0070] 910: Trench

[0071] 912: Dielectric Structure

[0072] 1000: Front-side transistors / FSTs

[0073] 1001, 1003, 1005, 1007: IMD layer

[0074] 1002, 1004, 1006, 1008: Conductivity characteristics

[0075] 1019: Bottom Electrode

[0076] 1021: Top Electrode

[0077] 1022: Through hole

[0078] 1023: Dielectric layer

[0079] 1024: Through hole

[0080] 1025: IMD layer

[0081] 1026: Electrical conductivity characteristics

[0082] 1100: Front-side interconnect structure / FSLs

[0083] 1101, 1103, 1105, 1107, 1135, 1137: IMD layer

[0084] 1102, 1106: Through holes

[0085] 1104, 1108, 1142, 1150: Metal wire

[0086] 1141: Bottom Electrode

[0087] 1143: Top Electrode

[0088] 1200: Front Side Memory Components / FSM

[0089] 1300: Rear Interconnect Structure / BSLs

[0090] 1400: Rear Memory Components / BSM

[0091] AA': line

[0092] BM0, BM1, BMX, BMX-1: Metallic wire

[0093] BV0, BV1, BVX, BVX-1: Through holes

[0094] D1, D2, D3, D4, D5, D6, D7: Dimensions

[0095] L1, L2: Dimensions

[0096] M0, M1, MX: Metal wire

[0097] MC: Memory Unit

[0098] MIM: Metal-Insulator-Metal

[0099] T: Size

[0100] V0, V1, VX: Through holes

[0101] x, y, z: Direction Detailed Implementation

[0102] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify the implementation of this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, the embodiments of this disclosure may repeatedly refer to numbers and / or letters. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0103] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0104] In modern semiconductor device manufacturing processes, a large number of semiconductor devices, such as field-effect transistors (FETs), are fabricated on a single wafer. Non-planar transistor device architectures, such as fin-based transistors (often called "FinFETs"), can provide higher device density and performance than planar transistors. Some advanced non-planar transistor device architectures, such as nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, gate all-loop (GAA) transistors, multi-bridge channel (MBC) transistors, etc.), can further improve device performance. Nanostructure transistors typically include a gate structure surrounding one or more nanostructures to improve control over channel current.

[0105] Considering how to form nanostructured transistors, these transistors typically allow for more efficient formation of interconnect structures on both the front and back sides of the device. In contrast, planar transistor device architectures usually require forming the corresponding interconnect structures only above the top surface of the transistors (e.g., the portion commonly referred to as back-end process (BEOL) wiring). In the prior art, various memory cells in a memory device can be integrated with such nanostructured transistors in the BEOL wiring on the front side of the memory device. In this respect, the various components of the memory device are formed in the same space (e.g., BEOL wiring), making it increasingly challenging to increase the device density on the front side. Therefore, there is a need to increase device density without compromising device performance.

[0106] Figure 1 According to some embodiments of this disclosure, a partial or overall cross-sectional view of an exemplary semiconductor device 100A (or memory device) is illustrated. The semiconductor device 100A (or simply "device") includes a substrate 102 consisting of a front side 102F (e.g., a first side) and a rear side 102B (e.g., a second side) opposite to the front side 102F. The device 100A includes a plurality of front-side transistors 10 (FSTs) and a plurality of front-side interconnect structures 15 (FSLs) disposed above (or on) the front side 102F, wherein at least some portions of the FSLs 15 are electrically coupled to the FSTs 10. In the depicted embodiment, the FSLs 15 are disposed above (or on) the FSTs 10 along a vertical direction (e.g., the Z-axis). Figure 1 In the illustrated embodiment, FSTs 10 are configured as logic devices (e.g., drivers) constituting the logic portion of device 100A.

[0107] As used herein, the term “electrical coupling” may be used interchangeably with “physical coupling” or “operational coupling”. The term “electrical coupling” may be used to describe any direct electrical connection between two components without any intermediate components; or it may be used to describe any indirect electrical connection between two components and one or more intermediate components therebetween.

[0108] like Figure 1As shown, the bottom portion of FSTs 10 (e.g., near the substrate 102) is embedded (or encapsulated) in an isolation structure 108 disposed above the substrate 102, and the top portion of FSTs 10 (e.g., away from the substrate 102) is embedded in an interlayer dielectric (ILD) layer 117. The isolation structure 108 is configured to electrically isolate adjacent active structures (e.g., adjacent fin structures or adjacent stacked nanostructure channel layers) from each other. The isolation structure 108 may comprise oxides, such as silicon oxide, nitrides, low-k dielectric materials (e.g., dielectric materials with a dielectric constant less than that of silicon oxide, which has a dielectric constant of approximately 3.9), such as silicon phosphide glass (PSG), borosilicate glass (BSG), borosilicate phosphoglass (BPSG), undoped silicon glass (USG), other suitable materials, or combinations thereof.

[0109] like Figure 1 As shown, device 100A may include a plurality of FSTs 10 arranged in a finned configuration along a first lateral direction (e.g., the Y-axis). Please refer to... Figure 2 Each FST 10 comprises a plurality of nanostructures 13 stacked along a vertical direction. The nanostructures 13 contain semiconductor material and are configured as multiple channels of the FSTs 10. In the embodiments disclosed herein, the nanostructures 13 may alternatively be referred to as semiconductor layers 13 or channel layers 13. Although the nanostructures 13 are described as nanosheets in this embodiment, the nanostructures 13 may alternatively be shaped into other types of structures, such as nanopillars or nanowires.

[0110] Nanostructure 13 may comprise any suitable semiconductor material, such as silicon (Si), silicon germanium (SiGe), compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, any other suitable material or combination thereof. In some embodiments, nanostructure 13 is substantially free of any dopant (e.g., p-type or n-type dopant). In some embodiments, nanostructure 13 is intentionally doped. For example, nanostructure 13 may be doped with p-type dopant, such as boron (B), aluminum (Al), indium (In), gallium (Ga), other p-type dopant, or combinations thereof. Alternatively, nanostructure 13 may be doped with n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), other n-type dopant, or combinations thereof.

[0111] Please refer to Figure 2FST 10 includes source feature 14S and drain feature 14D (hereinafter collectively referred to as source / drain feature 14), each source feature 14S and drain feature 14D being electrically coupled to one end of nanostructure 13. Thus, the source / drain features 14 each extend vertically over the stacked nanostructure 13. In embodiments where FST 10 is configured as an n-type device, the source / drain features 14 may comprise Si doped with the n-type dopant described herein. In embodiments where FST 10 is configured as a p-type device, the source / drain features 14 may comprise SiGe doped with the p-type dopant described herein. In some embodiments, each source feature 14S is a common source feature shared by two adjacent FSTs 10 disposed along a first lateral direction (see...). Figure 10 and Figure 12 ).

[0112] Please continue to refer to this. Figure 2 FST 10 includes an active gate structure 16 having at least a bottom (or lower) portion surrounding each nanostructure 13. In this respect, the bottom of the active gate structure 16 is interleaved with the stack of nanostructures 13. Furthermore, the active gate structure 16 includes a top (or upper) portion disposed above the topmost nanostructure 13 in the stack. In some embodiments, the active gate structure 16 includes a gate dielectric layer and a gate metal (not in the form of a gate dielectric layer) located above the gate dielectric layer. Figure 2 (Displayed separately in the text).

[0113] The gate dielectric layer can comprise any suitable dielectric material, such as a high-k dielectric material (e.g., a dielectric material with a dielectric constant greater than that of silicon oxide, which has a dielectric constant of approximately 3.9). Examples of high-k dielectric materials include metal oxides or metallic silicon of Hf, Al, Zr, La, Mg, Ba, Ti, and Pb, any other suitable material, or combinations thereof. Alternatively or concurrently, the gate dielectric layer may comprise silicon oxide, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The gate dielectric layer may comprise a stack of various dielectric materials.

[0114] The gate metal can comprise a stack of various metallic materials. For example, the gate metal may comprise at least one work function layer (not shown separately) and a conductive fill layer (not shown separately) disposed above the work function layer. The work function layer may comprise a p-type work function layer, an n-type work function layer, multiple layers thereof, any other suitable material, or a combination thereof. The work function layer may also be referred to as the work function metal. Exemplary work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable materials, or combinations thereof. The conductive fill layer may comprise any suitable conductive material, such as polysilicon, tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), platinum (Pt), other suitable conductive materials, or combinations (or alloys thereof). The active gate structure 16 may also include additional layers, such as an adhesive layer (or bonding layer), a capping layer, a barrier layer, other suitable layers, or combinations thereof.

[0115] Please refer to Figure 2 FST 10 includes an inner isolation layer 11 inserted along a first lateral direction between a portion of the active gate structure 16 and the source / drain features 14. FST 10 also includes gate spacers 17, each extending along a sidewall of the top portion of the active gate structure 16. The inner isolation layer 11 and the gate spacers 17 may each contain any dielectric material, such as silicon oxide, silicon nitride, silicon carbonitride, other suitable materials, or combinations thereof. The inner isolation layer 11 and the gate spacers 17 may each contain multiple layers of different dielectric materials. The inner isolation layer 11 and the gate spacers 17 may contain the same or different dielectric materials.

[0116] Please continue to refer to this. Figure 2The FST 10 also includes various contact features electrically coupled to at least one of the source feature 14S, drain feature 14D, and active gate structure 16 (e.g., its conductive fill layer). In the depicted embodiment, the FST 10 includes a source / drain contact 18 electrically coupled to at least one of the source / drain features 14. The source / drain contact 18 may include a conductive fill layer (not shown separately) having a conductive material, such as W, Cu, Co, Ru, Al, Ti, Ta, Au, Ag, Pt, other suitable conductive materials, or combinations thereof (or alloys). The source / drain contact 18 may include a barrier layer (not shown) separating the conductive fill layer from surrounding components. The barrier layer may include Ti, Ta, TiN, TaN, other suitable materials, or combinations thereof. The source / drain contact 18 may also include a metal silicide layer (not shown) disposed between the conductive fill layer and the underlying source / drain feature 14. The metal silicide layer may include, for example, NiSi.

[0117] Please also refer to Figure 1 and Figure 3 FSLs 15 include multiple dielectric layers (e.g., inter-metal dielectric (IMD) layers) embedding vertical conductive features (or interconnect conductive features) such as vias and horizontal conductive features such as metal (or conductive) lines. For example, FSLs 15 may include IMD layers 120, 122, 124, and 126 vertically stacked above IMD layer 117. FSLs 15 may include vias V0 and metal lines M0 embedded in IMD layer 120, wherein via V0 interconnects a portion of FST 10 to metal line M0. FSLs 15 may also include vias V1 and metal lines M1 embedded in IMD layer 122, wherein via V1 interconnects metal lines M0 to metal lines M1. In some embodiments, each of IMD layers 120-126 includes multiple dielectric layers, each dielectric layer encapsulating a via (e.g., vias V0, V1, etc.) or a metal line (e.g., metal lines M0, M1, etc.).

[0118] In various embodiments, at least one front-side memory element 80 (FSM), such as FSM1 and FSM2, is disposed above (or on) the front side 102F. Each FSM 80 is embedded and electrically coupled to a portion of the rear-side interconnect structure (BSLs) 20 along a vertical direction. For example, the bottom portion of the FSM 80 (e.g., located near the substrate 102) is electrically coupled to a first portion of the FSLs 15, and the top portion of the FSM 80 (e.g., located away from the substrate 102) is electrically coupled to a second portion of the FSLs 15, wherein the second portion is located above the first portion along a vertical direction.

[0119] Each front-side IMD layer and the corresponding conductive features embedded therein can be collectively referred to as a front-side metallization layer. For example, IMD layer 120, via V0, and metal line M0 can be collectively referred to as the zeroth front-side metallization layer; IMD layer 122, via V1, and metal line M1 can be collectively referred to as the first front-side metallization layer; and so on. (See reference) Figure 3 and Figure 7 For example, an additional front metallization layer containing conductive features such as VX+1, MX+1, VX+2, and MX+2 may be formed above the IMD layer 122 on the front side 102F and in the corresponding IMD layers 128 and 130.

[0120] ILD layer 117 and IMD layers 120-130 may each comprise an oxide of silicon oxide, a low-k dielectric material such as silicon phosphide glass (PSG), borosilicate glass (BSG), borosilicate phosphoglass (BPSG), undoped silicon glass (USG), other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layer 117 and IMD layers 120-130 comprise the same composition as isolation structure 108. Various conductive features V0, V1, M0, M1, etc., embedded in the corresponding ILD layer 117 and IMD layers 120-130 may each comprise a conductive filling layer (not depicted separately) having a conductive material such as W, Cu, Co, Ru, Al, Ti, Ta, Au, Ag, Pt, other suitable conductive materials, or combinations thereof (or alloys thereof). In some embodiments, each conductive feature comprises a barrier layer (not shown) separating the conductive filling layer from the surrounding ILD / IMD layers. The barrier layer may comprise Ti, Ta, TiN, TaN, other suitable materials, or combinations thereof.

[0121] Please refer to Figure 1 The device 100A also includes a plurality of rear-side interconnect structures 20 (BSLs) and at least one rear-side memory element 40 (BSM) above (or on) the rear side 102B. Each BSM 40 is embedded and electrically coupled to a portion of the BSLs 20 along a vertical direction. For example, the top portion of the BSM 40 (e.g., at a location close to the substrate 102) is electrically coupled to a first portion of the BSLs 20, while the bottom portion of the BSM 40 (e.g., at a location away from the substrate 102) is electrically coupled to a second portion of the BSLs 20, wherein the second portion is lower than the first portion.

[0122] Please also refer to Figure 1 and Figure 4The structure of BSLs 20 can be similar to that of FSLs 15. For example, BSLs 20 includes multiple IMD layers 140, 144, 148, and 152 stacked above (or on) the rear side 102B. In this regard, IMD layers 140-152 are positioned below FSTs 10 and vertically opposite FSLs 15. BSLs 20 may include vias BV0 and metal lines BM0 embedded in IMD layer 140, wherein vias BV0 interconnect a portion of the front-side components (e.g., drain feature 14D of one of FSTs 10) to metal lines BM0. BSLs 20 may include vias BV1 and metal lines BM1 embedded in IMD layer 144, wherein vias BV1 interconnect metal lines BM0 to metal lines BM1. Similarly, metal line BMX-1 can be embedded in IMD layer 148, and metal line BMX can be embedded in IMD layer 152, wherein via BVX interconnects metal line BMX-1 to metal line BMX. In some embodiments, each IMD layer 140-152 includes multiple dielectric layers, each dielectric layer encapsulating a via (e.g., vias BV0, BV1, and BVX, etc.) and a corresponding metal line (e.g., metal lines BMO, BM1, BMX-1, and BMX, etc.). Please refer to... Figure 4 An additional rear metallization layer may be formed above the IMD layer 152 on the rear side 102B. The additional rear metallization layer includes conductive features such as BVX+1, BMX+1, BVX+2 and BMX+2.

[0123] Each rear IMD layer and the corresponding conductive feature embedded therein are collectively referred to as a rear metallization layer. For example, IMD layer 140, via BV0, and metal line BM0 are collectively referred to as the zeroth rear metallization layer; IMD layer 144, via BV1, and metal line BM1 are collectively referred to as the first rear metallization layer; and so on. Please refer to [reference needed]. Figure 4 An additional rear metallization layer may be formed above the IMD layer 152 on the rear side 102B. The additional rear metallization layer contains conductive features, such as BVX+1, BMX+1, BVX+2, and BMX+2. In some embodiments, the IMD layers 140-152 may have the same structure and composition as the IMD layers 117 and 120-130 described herein, and the conductive features embedded in the IMD layers 140-152 (e.g., BV0, BMO, BV1, BMO, etc.) may have the same composition and structure as the conductive features embedded in the IMD layers 120-130 (e.g., V0, M0, V1, M1, etc.).

[0124] In some embodiments, please refer to Figure 1 and Figure 5The BSM 40 is configured as a capacitor having a metal-insulator-metal (MIM) structure. In this regard, the BSM 40 typically includes a bottom electrode 44 (e.g., a first metal layer), a top electrode 48 (e.g., a second metal layer), and a dielectric layer 46 (e.g., an insulating layer) sandwiched vertically between the bottom electrode 44 and the top electrode 48. The BSM 40 may also include a first via 50 and a second via 52, the first via 50 electrically coupling the bottom electrode 44 to the portion of the BSL 20 below the BSM 40, and the second via 52 electrically coupling the top electrode 48 to the portion of the BSL 20 above the BSM 40.

[0125] The bottom electrode 44 and the top electrode 48 may comprise iron (Fe), W, Cu, Co, Ru, Al, Ti, Ta, Au, Ag, Pt, other suitable conductive materials, or combinations (or alloys) thereof. In some embodiments, the bottom electrode 44 and the top electrode 48 may comprise metals doped with dopants (or impurities). The dielectric layer 46 may comprise any suitable dielectric material, such as silicon oxide, ZrO, TiO2, MgO, the high-k dielectric materials described herein, other suitable dielectric materials, or combinations thereof. Examples of high-k dielectric materials include, but are not limited to, zirconium oxide, hafnium oxide, zirconium silicate, hafnium silicate, etc. The first via 50 and the second via 52 may have the same composition and structure as the vias V0 and V1 described herein.

[0126] In some embodiments, the structure and composition of the FSM 80 are similar to those of the BSM 40. For example, please refer to... Figure 6 The FSM80 includes a MIM capacitor structure having a bottom electrode 84 (e.g., a first metal layer), a top electrode 88 (e.g., a second metal layer), and a dielectric layer 86 (e.g., an insulating layer) sandwiched between the bottom electrode 84 and the top electrode 88 along a vertical direction. The FSM80 may also include a first via 90 and a second via 92, the first via 90 electrically coupling the bottom electrode 84 to the portion of the FSLs 15 below the FSM80 (e.g., vias V0, V1, and VX-1 and metal lines M0, M1, and MX-1), and the second via 92 electrically coupling the top electrode 88 to the portion of the FSLs 15 above the FSM80 (e.g., metal line MX). In the depicted embodiment, the FSM80 is disposed in the IMD layer 82 inserted between the IMD layers 124 and 126.

[0127] In various embodiments, FSTs 10, FSMs 80, BSMs 40, and their corresponding interconnect structures form multiple components (e.g., an array) of memory cells (MCs), or single cells, in device 100A. For example, refer to... Figure 1The device 100A includes memory cells MC[0], MC[1], MC[2], and MC[3] sequentially spaced apart from each other along a first lateral direction. For example, memory cell MC[1] is arranged adjacent to memory cell MC[0], memory cell MC[2] is arranged adjacent to memory cell MC[1], memory cell MC[3] is arranged adjacent to memory cell MC[2], and so on. In some embodiments, MCs are configured to have the same cell size L1 along the first lateral direction. For example, in Figure 1 In the embodiment shown, the cell size L1 is essentially twice the size of FST 10, i.e., L1 = 2T, where T represents the size of FST 10 along the first lateral direction.

[0128] Each MC includes a transistor (e.g., one of the FSTs 10) electrically coupled in series to a memory element (or capacitor) (e.g., one of the BSMs 40 or one of the FSMs 80) via a portion of a corresponding interconnect structure (e.g., BSLs 20 or FSLs 15 respectively). For example, each memory cell MC[0] and memory cell MC[2] includes one of the FSTs 10 electrically coupled to FSM1 and FSM2 respectively via a portion of FSLs 15, while each memory cell MC[1] and memory cell MC[3] includes one of the FSTs 10 electrically coupled to BSM1 and BSM2 respectively via a portion of BSLs 20. Thus, the MCs provided herein are all configured to have a 1T1C structure, wherein the FSTs 10 are configured as 1T, or transistor components of the MC, and the memory elements (e.g., FSM 80 or BSM 40) are configured as 1C, or capacitor components of the MC. In some embodiments, the memory element serves as the memory cell of the MC, and the transistor FST 10 acts as a switch to allow access to the memory element in the MC (e.g., programming, reading, erasing, etc.).

[0129] In the depicted embodiments, based on the location of their respective memory elements, MCs having FSMs 80, such as MC[0] and MC[2], may be selectively referred to as front-side memory cells (FSMCs), while MCs having BSMs 40, such as memory cell MC[1] and memory cell MC[3], may be selectively referred to as rear-side memory cells (BSMCs). In some embodiments, the series connection between each FST 10 and its corresponding memory element (FSM or BSM) is established by electrically coupling one of the source / drain features 14 of the FST 10 (e.g., drain feature 14D) to one of the electrodes of the memory element. For example, for FSMCs, the front side of the drain feature 14D of the first FST 10 is electrically coupled to the bottom electrode 84 of the corresponding FSM 80 via a first via 90 and a portion of the FSLs 15.

[0130] Similarly, for BSMCs, the rear side of the drain feature 14D of the second FST 10 is electrically coupled to the top electrode 48 of the corresponding BSM 40 through the second via 52 and portions of the BSLs 20. The second via 52 and portions of the BSLs 20 include, for example, vias BV0, BV1, and BVX-1, and metal lines BM0 and BM1. In this regard, via BV0 extends vertically through the substrate 102 to directly contact the rear side of the drain feature 14D. In some embodiments, reference... Figure 1 FSMCs, such as memory cell MC[0] and memory cell MC[2], are formed in the same IMD layer, such as IMD layer 82, while BSMCs, such as memory cell MC[1] and memory cell MC[3], are formed in the same IMD layer, such as IMD layer 42.

[0131] Depending on the type of material used in the BSM 40 or FSM 80, MCs may include dynamic random access memory (DRAM) cells, magnetoresistive random access memory (MRAM) cells (also known as magnetic tunneling junction cells or MTJ cells), resistive random access memory (ReRAM) cells, ferroelectric random access memory (FeRAM) cells, or other suitable types of memory cells that have been, are being, or will be developed. In some embodiments, device 100A may include two or more identical or different types of MCs contained in FSMCs and / or BSMCs.

[0132] In embodiments where the MC includes an MRAM cell, the bottom electrode 44 and top electrode 48 (or bottom electrode 84 and top electrode 88) may each comprise a ferromagnetic material having, for example, Fe doped with cobalt (Co), boron (B), nickel (Ni), other suitable dopants, or combinations thereof, and the dielectric layer 46 (or dielectric layer 86) comprises, for example, magnesium oxide (MgO). In embodiments where the MC is an FeRAM cell, the dielectric layer 46 (or dielectric layer 86) comprises a ferroelectric material. Although not depicted herein, other capacitor configurations (e.g., MOS capacitors) may also be applicable to this embodiment of the BSM 40 or FSM 80.

[0133] In some embodiments, please refer to Figure 1 Each of the FSMs 80 and BSMs 40 can be configured to have a dimension D along a first lateral direction. In the prior art, where MCs are formed using only the front side of the substrate, the dimension D of the FSMs 80 in two adjacent MCs is limited to be smaller than the cell size L1 to ensure that the two MCs do not interfere with each other, thereby increasing the bit cell error rate in the memory device. As the unit cell area (e.g., cell size L1) continues to shrink to achieve higher storage density, the shortened dimension D may cause stability problems for the MCs. For example, in embodiments where the MCs are configured as MRAM cells, the shortened dimension D may cause undesirable variations in magnetoresistive effects and / or lead to a shorter memory device lifetime.

[0134] The embodiments disclosed herein provide embodiments of memory devices in which, in addition to FSMSs, the BSMC is formed by relying on side components (e.g., BSMs 40 and BSLs 20), relaxing (or in some cases eliminating) design rule restrictions on the front component size (e.g., cell size L1), thereby increasing the density of memory cells without sacrificing performance. In this regard, memory elements on both sides can be formed with a longer dimension (e.g., a dimension D increasing along the first lateral direction) without reducing the number of memory cells allowed on a given side (front or rear) of the memory device. Furthermore, the rear component can provide more flexible wiring options for the memory device, thereby improving the manufacture of more advanced memory devices. See below for reference. Figure 1 and Figures 7 to 13 As described in detail, some embodiments provide a memory device having memory elements formed on the front and back sides of a substrate. Alternatively or additionally, some embodiments provide a memory device having memory elements formed on the same side of a substrate in an alternating arrangement.

[0135] In some embodiments, please refer to Figure 1The device 100A includes FSMCs (e.g., memory cells MC[0] and MC[2]) and BSMCs (e.g., memory cells MC[1] and MC[3]). By arranging the FSMCs and BSMCs alternately along a first transverse direction, the FSMs 80 can each be formed to size D1 and the BSMs 40 can each be formed to size D2, wherein both sizes D1 and D2 are larger than the cell size L1. In this respect, the performance of the memory elements in two directly adjacent MCs can be maintained or improved without significantly sacrificing the number of MCs provided in the device 100A (i.e., memory density). In some embodiments, by forming MCs on both sides of the substrate 102, the dimensions of the FSMs 80 and BSMs 40 can be configured to optimize the performance of the MCs, without being limited by design rules. In some embodiments, such as Figure 1 As described, adjacent memory cells (MCs) may include memory elements that overlap each other when formed on opposite sides of substrate 102. In some embodiments, dimensions D1 and D2 may be substantially the same or different.

[0136] In some embodiments, please refer to Figure 7 According to some embodiments disclosed herein, Figure 7 This is a partial or overall cross-sectional view of an exemplary semiconductor device 100B (or memory device). The semiconductor device 100B (or simply "device") may be configured to have a structure similar to that of device 100A. For example, device 100B includes FSMCs and BSMCs, thereby allowing adjacent memory elements to be formed on opposite sides of substrate 102. Specifically, memory cells MC[0], MC[1], MC[2], MC[5], and MC[6] are configured as FSMCs, each FSMC including an FST 10 electrically coupled to a corresponding FSM 80 (e.g., FSM1, FSM2, FSM3, FSM4, and FSM5) located on the front side 102F, while memory cells MC[3] and MC[4] are configured as BSMCs, each BSMC including an FST 10 electrically coupled to a corresponding BSM 40 (e.g., BSM1 and BSM2) on the rear side 102B. Based on this arrangement, each FSMs 80 may include a dimension D3 along the first lateral direction, and each BSMs 40 may include a dimension D4 along the first lateral direction, which is larger than dimension D3. Both dimensions D3 and D4 are larger than the cell size L1 previously defined relative to the MCs in device 100A. Figure 1 The depicted embodiments are similar, in which the FSM and the BSM adjacent to each other along the first lateral direction can overlap each other.

[0137] To further relax design rules regarding the size (e.g., length) of memory elements in MCs, device 100B is configured to include MCs formed on the same side of substrate 102, which are staggered in the vertical direction. For example, in the FSMCs provided herein, an adjacent pair of FSMCs, such as corresponding memory cells MC[0] and MC[1], MC[1] and MC[2], and MC[5] and MC[6], include FSMs 80 formed in different IMD layers. Specifically, FSM1, FSM2, and FSM3, which are part of memory cells MC[0], MC[2], and MC[5] respectively, are formed in IMD layer 82, while FSM4 and FSM5, which are part of memory cells MC[1] and MC[6] respectively, are formed in IMD layer 83, which is located above IMD layer 82. Similarly, BSM1, which is part of memory cell MC[3], is formed in IMD layer 42, while BSM2, which is part of memory cell MC[4], is formed in IMD layer 43, which is located below IMD layer 42.

[0138] In some embodiments, please refer to Figure 8 According to some embodiments disclosed herein, Figure 8 This is a partial or overall cross-sectional view of an exemplary semiconductor device 100C (or memory device). The semiconductor device 100C (or simply "device") may be configured to have a structure similar to that of device 100A. For example, device 100C includes FSMCs and BSMCs, thereby allowing adjacent memory elements to be formed on opposite sides of substrate 102. Specifically, memory cells MC[0] and MC[2] are configured as FSMCs, each FSMC including an FST 10 electrically coupled to a corresponding FSM 80 (e.g., FSM1 and FSM2) located on the front side 102F, while memory cells MC[1] and MC[3] are configured as BSMCs, each BSMC including an FST 10 electrically coupled to a corresponding BSM 40 (e.g., BSM1 and BSM2) located on the rear side 102B. Specifically, the drain feature 14D of FST 10 in each of memory cells MC[1] and MC[3] is electrically coupled to the back side of BV0 of BSLs 20, and BSLs 20 is also electrically coupled to BSM 40 through its portion.

[0139] However, with Figure 1Unlike the device 100A depicted herein, device 100C includes two adjacent memory cells (MCs) configured to share a common source feature (e.g., source feature 14S) (e.g., memory cell MC[1] and memory cell MC[2] as depicted herein), thereby reducing the cell size of the MCs as measured by the front-side components and achieving a smaller device size along the first lateral direction. For example, the cell size L2 of the MCs in device 100C can be reduced to 1.5 times the size of FST 10 (i.e., L2 = 1.5T), which contrasts with the cell size L1, which in device 100A (and device 100B) is twice the size of FST 10 (L1 = 2T).

[0140] To accommodate the sharing of source characteristics, device 100C may further include a dummy gate structure 196 (or passive gate) disposed between the drain components (e.g., drain feature 14D) of the FSTs 10 of two adjacent MCs, wherein the dummy gate structure 196 is grounded (or electrically coupled to a 0V supply voltage). Therefore, the dummy gate structure 196 serves to electrically isolate the two adjacent MCs. The dummy gate structure 196 may have a similar structure and composition to the active gate structure 16, but is not electrically coupled to any signal line, as is the case with the active gate structure 16.

[0141] In some embodiments, please refer to Figure 9 According to some embodiments disclosed herein, Figure 9 This is a partial or overall cross-sectional view of an exemplary semiconductor device 100D (or memory device). The semiconductor device 100D (or simply "device") may be configured to have a structure similar to that of device 100C. For example, two adjacent MCs (e.g., memory cell MC[1] and memory cell MC[2] as depicted herein) are configured to share a common source feature, such as source feature 14S, such that the cell size L2 is reduced to 1.5T. Furthermore, device 100D includes a dummy gate structure 196 disposed between the drain features 14D of FSTs 10 in two directly adjacent MCs, wherein the dummy gate structure 196 is grounded.

[0142] However, unlike device 100C, all MCs in device 100D are configured as FSMCs, wherein FSMs 80 are arranged alternately along the vertical direction. For example, a pair of adjacent FSMCs, such as memory cell MC[0] and memory cell MC[1], memory cell MC[1] and memory cell MC[2], and memory cell MC[2] and memory cell MC[3], are contained in FSMs 80 formed in different IMD layers. Specifically, FSM1 and FSM2, which are parts of memory cell MC[0] and memory cell MC[2] respectively, are formed in IMD layer 82, while FSM3 and FSM4, which are parts of memory cell MC[1] and memory cell MC[3] respectively, are formed in IMD layer 83, which is located above IMD layer 82.

[0143] Furthermore, the FSMs 80 in device 100D have different dimensions. For example, each of FSM1 and FSM2 may have a dimension D5 along the first lateral direction, and each of FSM3 and FSM4 may have a dimension D6 along the first lateral direction, which is larger than dimension D5. Dimensions D5 and D6 may each be greater than, equal to, or less than cell size L2. In this regard, by staggering the FSMs 80 along the vertical direction, the design rules specifying the dimensions of the FSMs 80 along the first lateral direction can be relaxed to allow for size optimization for device performance without reducing the density of memory cells on the front side 102F.

[0144] In some embodiments, please refer to Figure 10 According to some embodiments disclosed herein, Figure 10 This is a cross-sectional view of a portion or the entirety of an exemplary semiconductor device 100E (or memory device). The semiconductor device 100E (or simply "device") may be configured to have a structure similar to that of device 100D. For example, the FSMs (e.g., FSM1, FSM2, FSM3, FSM4, and FSM5) of certain FSMCs (memory cells MC[0], MC[1], MC[2], MC[3], and MC[5]) are formed with different sizes, such as size D5 and size D6, on the front side 102F of device 100E and are staggered along the vertical direction. In addition, two directly adjacent MCs in device 100E (e.g., memory cells MC[1] and MC[2] as depicted herein) are configured to share a common source feature, such as source feature 14S. In addition, the device 100E includes a dummy gate structure 196 disposed between the drain features 14D of two directly adjacent MCs, wherein the dummy gate structure 196 is grounded to electrically isolate the MCs.

[0145] However, unlike device D, the memory elements of the additional MCs (e.g., memory cells MC[4] and MC[6]) are formed on the rear side 102B of device 100D, making them BSMCs. Furthermore, the BSMs 40 (e.g., BSM1 and BSM2) contained in memory cells MC[4] and MC[6] respectively are all formed with a size D7, which is larger than the cell size L2. In this respect, the rear side 102B is used to form the BSMs 40 with a longer size without interfering with the FSMs 80 of the adjacent FSMCs (e.g., memory cells MC[3] and MC[5]).

[0146] In some embodiments, please refer to Figure 11 According to some embodiments disclosed herein, Figure 11 This is a cross-sectional view of a portion or the entirety of an exemplary semiconductor device 100F (or memory device). The semiconductor device 100F (or simply "device") may be configured to have a structure similar to that of device 100C. For example, two adjacent MCs (e.g., memory cell MC[1] and memory cell MC[2] as depicted herein) are configured to share a common source feature, such as source feature 14S, such that the cell size L2 is reduced to 1.5T.

[0147] However, instead of forming a dummy gate structure 196 to isolate adjacent MCs, the device 100F includes a dielectric structure 198 (or isolation gate) inserted between the drain features 14D of the FSTs 10 of two adjacent MCs. In other words, the dielectric structure 198 is inserted between the active gate structures of the FSTs 10 of two adjacent MCs and extends parallel to them (along a second lateral direction, e.g., the X-axis). In some embodiments, the dielectric structure 198 may be formed as a cleaved polysilicon edge (CPODE) feature on a diffusion layer, which typically replaces the active gate structure 16 between the two adjacent FSTs 10 and drain features 14D of the two MCs. The dielectric structure 198 may include any dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric structure 198 may be formed to replace the active gate structures 16 after all the active gate structures 16 on the front side 102F have been formed. In some embodiments, the dielectric structure 198 and the dummy gate structure 196 each function to electrically isolate adjacent MCs. In some embodiments, the dielectric structure 198 and the dummy gate structure 196 can be used interchangeably.

[0148] In some embodiments, please refer to Figure 12 According to some embodiments disclosed herein, Figure 12This is a cross-sectional view of a portion or the entirety of an exemplary semiconductor device 100G (or memory device). The semiconductor device 100G (or simply "device") may be configured to have a structure similar to that of device 100D. For example, two adjacent MCs (e.g., memory cell MC[1] and memory cell MC[2] as depicted herein) are configured to share a common source feature. In addition, all MCs in device 100G include memory elements (e.g., FSM1, FSM2, FSM3 and FSM4) formed on the front side 102F in an alternating arrangement along the vertical direction. However, instead of relying on the dummy gate structure 196 for isolation, device 100G relies on the dielectric structure 198 described herein to provide isolation between two adjacent MCs.

[0149] In some embodiments, please refer to Figure 13 According to some embodiments disclosed herein, Figure 13 This is a cross-sectional view of part or all of an exemplary semiconductor device 100H (or memory device). Semiconductor device 100H (or simply "device") may be configured to have a structure similar to that of device 100E. For example, two adjacent MCs (e.g., memory cell MC[1] and memory cell MC[2] as depicted herein) are configured to share a common source feature. Additionally, some MCs in device 100F (e.g., memory cell MC[0], memory cell MC[1], memory cell MC[2], memory cell MC[3], and memory cell MC[5]) include memory elements (e.g., FSM1, FSM2, FSM3, FSM4, and FSM5) formed on the front side 102F in an alternating arrangement along the vertical direction, while some MCs (e.g., memory cell MC[4] and memory cell MC[6]) include memory elements (e.g., BSM1 and BSM2) formed on the rear side 102B of substrate 102. BSMs 40 may be formed to a size that is similar to that of the FSMs. The dimensions of 80 are different and larger than the cell size L2, as described herein with respect to device 100E. Furthermore, two adjacent MCs in device 100H (e.g., memory cell MC[1] and memory cell MC[2] as depicted herein) are configured to share a common source feature, such as source feature 14S. However, device 100F does not rely on the dummy gate structure 196 for isolation, but rather on the dielectric structure 198 described herein to provide isolation between the two adjacent MCs.

[0150] Figure 14 A flowchart of an exemplary method 200 for manufacturing a semiconductor device 300 (e.g., device 100A-100H) is illustrated according to some embodiments. It should be noted that method 200 is merely exemplary and not intended to limit the embodiments disclosed herein. Therefore, it should be understood that... Figure 14Additional steps / operations are provided before, during, and after method 200, and this document may only briefly describe some of these other operations. In some embodiments, one or more operations of method 200 are performed before... Figure 15 The flowchart shown is described in detail. The operation of method 200 can be compared with... Figures 16 to 27 The cross-sectional views of the semiconductor device 300 at various manufacturing stages shown are related and will be described in further detail below.

[0151] For a brief overview, please refer to [link / reference]. Figure 14 Method 200 proceeds to operation 202, which involves forming a first transistor and a second transistor (or front-side transistors, FSTs, such as FSTs 10, FSTs 1000) on the front side (or front side, such as 102F, 302F) of a substrate (e.g., substrate 102, substrate 302). The first transistor and the second transistor are spaced apart from each other along a first lateral direction. In some embodiments, the first transistor and the second transistor may be directly adjacent to each other. Method 200 proceeds to operation 204, which involves forming a first interconnect structure (or front-side interconnect structure, FSLs, such as FSLs 15, FSLs 1100) on the front side. Method 200 proceeds to operation 206, which involves forming a first memory element (or front-side memory element, FSM, such as FSM 80, 1200) on the front side. In some embodiments, the first memory element is series-coupled to the first transistor on a first side. Method 200 proceeds to operation 208, which involves flipping the substrate. Method 200 proceeds to operation 210, which involves polishing the rear side of the substrate to expose a portion of the second transistor (e.g., a drain feature, drain feature 14D). Next, method 200 proceeds to operation 212, where a second interconnect structure (or rear-side interconnect structure, BSLs, e.g., BSLs 20, BSLs 1300) is formed on the rear side (or second side, e.g., rear side 102B) opposite the front side of the substrate. Method 200 then proceeds to operation 214, where a second memory element (or rear-side memory element BSM, e.g., BSM 40, BSM 1400) is formed on the rear side. In this embodiment, the second memory element is electrically coupled in series to the second transistor on the second side.

[0152] Figure 16 A perspective view of a portion of a semiconductor device 300 (or simply "device") is illustrated, which, according to some embodiments, includes at least the exemplary front-side transistor 1000 (FST) depicted herein on the front side of the device 300. In some embodiments, via Figure 15 The flowchart shown describes in detail the manufacturing process of FST 1000 in operation 202 of method 200.

[0153] Device 300 includes a substrate 302 and a plurality of semiconductor layers 306 (e.g., nanostructures 13) above the substrate 302 (e.g., substrate 102). The semiconductor layers 306 can be selectively configured as nanosheets, nanopillars, nanowires, or other suitable nanostructures. The semiconductor layers 306 are perpendicularly separated from each other, collectively serving as channels for the FST 1000. An isolation region / isolation structure 504 (e.g., isolation structure 108) is formed on the sidewalls of a protrusion of the substrate 302, with the semiconductor layers 306 disposed above the protrusion. An active gate structure 900 (e.g., active gate structure 16) surrounds each semiconductor layer 306 (e.g., the entire periphery of each semiconductor layer 306). One of the source / drain features 802 (e.g., source / drain feature 14) is located in… Figure 16 As shown, source / drain features 802 are disposed on opposite sides of the active gate structure 900, with gate spacers 702 disposed therebetween. An interlayer dielectric (ILD) 806 is disposed above a portion of the source / drain features 802 and may extend below a portion of the source / drain features 802. Figure 16 The FST 1000 shown (i.e., device 300) is simplified; therefore, it should be understood that one or more features of the complete FST 1000 may not be present. Figure 16 As shown in the diagram. For example, another element in source / drain characteristic 802 is not shown in... Figure 16 As shown in the image. Additionally, it provides... Figure 15 For reference, to show multiple cross-sectional views of device 300 along line AA' in subsequent figures, line AA' extending in a first transverse direction.

[0154] For a brief overview, please refer to [link / reference]. Figure 15The FST 1000 can be formed by implementing sub-operations of operation 202. For example, operation 202 can begin with sub-operation 252, which provides a substrate 302 covered by a first semiconductor layer 304 and a second semiconductor layer 306. Next, operation 202 proceeds to sub-operation 254, which forms a fin structure 400. Operation 202 proceeds to sub-operation 256, which forms an isolation structure 504. Operation 202 proceeds to sub-operation 258, which forms a dummy gate structure 600 over the semiconductor fins. Operation 202 proceeds to sub-operation 260, which forms a gate spacer 702. Operation 202 proceeds to sub-operation 262, which forms a source feature and / or a drain feature 802 (collectively referred to as source / drain feature 802). Operation 202 proceeds to sub-operation 264, which removes the dummy gate structure 600 and the first semiconductor layer 304. Operation 202 proceeds to sub-operation 266, which forms an active gate structure 900. Operation 202 is selectively performed to sub-operation 268, which replaces some of the active gate structure 900 with dielectric structure 912. Operation 202 is performed to sub-operation 270, which forms contact features (e.g., source / drain contacts 902) of components electrically coupled to FST 1000.

[0155] Please refer to Figure 15 and Figure 17 According to various embodiments, in sub-operation 252, a plurality of first semiconductor layers 304 and a plurality of second semiconductor layers 306 are alternately formed above the front side 302F of the substrate 302. This alternating stack of first semiconductor layers 304 and second semiconductor layers 306 can be formed as a stack above the front side of the substrate 302. It should be understood that the FST 1000 may include any number of first semiconductor layers 304 (which are respectively used as sacrificial layers) and any number of second semiconductor layers 306 (which are respectively used as channel layers), wherein any one of them is the topmost layer, while still remaining within the scope of the embodiments disclosed herein.

[0156] In some embodiments, substrate 302 has substantially the same structure and composition as substrate 102 described herein. In some embodiments, substrate 302 includes an epitaxial layer. For example, substrate 302 may have an epitaxial layer of a cover material semiconductor. Furthermore, substrate 302 may include a semiconductor-on-insulator (SOI) structure. For example, substrate 302 may include a buried oxide (BOX) layer, which is formed by a process such as direct implantation of oxygen ions (SIMOX) or other suitable techniques such as wafer bonding and polishing.

[0157] Semiconductor layers 304 and 306 can have different thicknesses. The first semiconductor layer 304 can have varying thicknesses from one layer to another. The second semiconductor layer 306 can also have varying thicknesses from one layer to another. The first stacked layer can be thicker than the other semiconductor layers 304 and 306. Either the first semiconductor layer 304 or the second semiconductor layer 306 can be the top layer (or the layer furthest from the substrate 302). In one embodiment, the first semiconductor layer 304 can be the bottom layer (or the layer closest to the substrate 302).

[0158] Semiconductor layers 304 and 306 have different compositions. In various embodiments, semiconductor layers 304 and 306 have compositions that provide different oxidation rates and / or different etch selectivity between the layers. In one embodiment, the first semiconductor layer 304 comprises silicon germanium (Si1-xGex), while the second semiconductor layer 306 comprises silicon (Si). In some embodiments, the second semiconductor layer 306 has a composition substantially the same as that of the nanostructure 13 described herein. Either semiconductor layer 304 or semiconductor layer 306 may comprise other materials, such as compound semiconductors like silicon carbide, gallium arsenide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors like GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, any other suitable materials, or combinations thereof. The materials of semiconductor layers 304 and 306 may be selected to provide different oxidation rates and / or etch selectivity.

[0159] Semiconductor layers 304 and 306 can be grown from substrate 302. For example, each of semiconductor layers 304 and 306 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes such as metal-organic CVD (MOCVD), and / or other suitable growth processes. During epitaxial growth, the crystal structure of substrate 302 extends upward, resulting in semiconductor layers 304 and 306 having the same crystal orientation as substrate 302.

[0160] Please refer to Figure 15 and Figure 18 According to various embodiments, in sub-operation 254, fin structures 400A, 400B, and 400C (collectively referred to as fin structures 400) are formed in the stack of semiconductor layers 304 and 306. Each fin structure 400 extends along a first lateral direction and is spaced apart from each other along a second lateral direction perpendicular to the first lateral direction (e.g., the X-axis). Although in Figure 18 The illustrated embodiment (and the following figures) shows three fin structures, but it should be understood that the FST 1000 may include any number of fin structures while still remaining within the scope of the embodiments disclosed herein.

[0161] The fin structure 400 is formed by patterning the stack of semiconductor layers 304 and 306, as well as the top portion of the substrate 302, using techniques such as photolithography and etching. For example, a mask layer (which may include multiple layers, such as a pad oxide layer and a covering pad nitride layer) is formed over the topmost second semiconductor layer 306. For example, the pad oxide layer and the pad nitride layer can be formed using high-temperature oxidation, low-pressure chemical vapor deposition (LPCVD), or plasma-assisted chemical vapor deposition (PECVD).

[0162] The mask layer can then be patterned using photolithography. Generally, photolithography utilizes a photoresist material (not shown), which is deposited, irradiated (exposed), and developed to remove a portion of the photoresist. The remaining photoresist protects the underlying material (e.g., the mask layer in this example) from subsequent processing steps (e.g., etching). For example, the photoresist is used to pattern pad oxide and pad nitride layers to form a patterned photomask 402, such as... Figure 17 As shown. After the patterned mask layer, the photoresist material can be removed by a suitable method, such as plasma ashing or resist stripping.

[0163] Subsequently, a patterning mask 402 is used to pattern the exposed portions of semiconductor layers 304 and 306 and substrate 302 to form trenches (or openings) 410, thereby defining fin structures 400 between adjacent trenches 410, such as... Figure 18 As shown. Trench 410 continues to extend along the first lateral direction. When forming multiple fin structures, trench 410 can be disposed between any adjacent fin structures. In some embodiments, fin structures 400 are formed by etching trenches in semiconductor layers 304 and 306 and substrate 302 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), other suitable processes, or combinations thereof. The etching process can be anisotropic.

[0164] Please refer to Figure 15 and Figure 19 According to various embodiments, the isolation structure 504 (or isolation region 504) is in sub-operation 256. For example... Figure 19 As shown, the isolation structure 504 can be formed between adjacent fin structures 400 and is partially embedded in or around the lower part of the adjacent fin structure 400.

[0165] In some embodiments, the isolation structure 504 has substantially the same composition as the isolation structure 108. The insulating material 504 can be formed by depositing an insulating material using high-density plasma chemical vapor deposition (HDP-CVD), flow-through CVD (FCVD) (e.g., a CVD-based material deposition process in a remote plasma system followed by post-curing to transform it into another material, such as an oxide), other suitable methods, or combinations thereof. Once the insulating material is formed, an annealing process can be performed. A planarization process, such as chemical mechanical polishing (CMP) or any other suitable process, can remove any excess insulating material and form a coplanar top surface of the insulating material and a top surface of the patterned mask 402 (not shown). In some other embodiments, the patterned mask 402 can be removed by a planarization process. Subsequently, the insulating material is recessed to form the isolation structure 504, sometimes referred to as shallow trench isolation (STI). The recess in the isolation structure 504 causes the fin structure 400 to protrude from between adjacent isolation structures 504. The isolation structure 504 can be recessed to a position where the top surface of the isolation structure 504 is located below the substrate 302. The isolation structure 504 can be recessed using an acceptable etching process (e.g., an etching process selective for the material of the isolation structure 504). For example, dry etching or wet etching using dilute hydrofluoric acid (DHF) can be performed to recess the isolation structure 504.

[0166] Please refer to Figure 15 and Figure 20 According to various embodiments, in sub-operation 258, a plurality of dummy gate structures 600 are formed above the fin structure 400. Each of the dummy gate structures 600 extends continuously along a second lateral direction and is positioned where an active (e.g., metal) gate structure can be formed later. Figure 20 Three dummy gate structures 600 are shown, but it should be understood that any number of dummy gate structures 600 can be formed above the fin structure 400.

[0167] Before forming the dummy gate structure 600, an etch stop layer 602 may be formed above the top surface of the fin structure 400. The etch stop layer 602 may comprise silicon oxide or any other suitable material and may be formed by a deposition process such as CVD, ALD, other suitable processes, or combinations thereof. Next, a dummy gate electrode layer (not shown), for example comprising polysilicon, may be deposited over the etch stop layer 602 as a blanket layer. In some embodiments, a hard mask 604 is deposited over the dummy gate electrode layer. Then, using the photolithography process described herein, the hard mask 604 is first patterned, and the patterned hard mask 604 is used as an etch mask to etch the dummy gate electrode layer to form the dummy gate electrode layer.

[0168] In some embodiments, although not shown, each dummy gate structure 600 further includes a dummy gate dielectric layer (not shown) disposed between the etch stop layer 602 and the dummy gate electrode layer. The dummy gate dielectric layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, multilayers thereof, other suitable dielectric materials, or combinations thereof, and may be formed by high-temperature oxidation, chemical oxidation, CVD, ALD, other suitable methods, or combinations thereof.

[0169] Please refer to Figure 15 and Figure 21 According to various embodiments, in sub-operation 260, gate spacers 702 are formed on opposite sidewalls of the dummy gate structure 600. Gate spacers 702 may include any suitable dielectric material as described herein with respect to gate spacer 17. In some embodiments, gate spacers 702 comprise multiple layers of different dielectric materials. Gate spacers 702 can be formed by first uniformly depositing one or more dielectric materials over the dummy gate structure 600. Any suitable deposition method can be used to deposit the dielectric material, such as high-temperature oxidation, chemical oxidation, CVD, ALD, other suitable methods, or combinations thereof. The dielectric material can then be etched using a suitable etching process (such as anisotropic dry etching) to form gate spacers 702 along opposite sidewalls of the dummy gate structure 600.

[0170] Please refer to Figure 15 and Figure 21 According to various embodiments, in sub-operation 262, source / drain elements 802 are formed in each fin structure 400 on a corresponding side of the dummy gate structure 600. The source / drain features 802 can be formed by performing an etching process to remove portions of the fin structure 400 not covered by the dummy gate structure 600 and the gate spacer 702. The etching process may include anisotropic etching using the dummy gate structure 600 as an etching mask, but any other suitable etching process may also be used. When portions of the fin structure 400 are removed, source / drain recesses 706 are formed.

[0171] During or after the formation of the source / drain recesses 706, the corresponding end portions of each first semiconductor layer 304 can be removed or etched. A "retraction" process can be used to pull the first semiconductor layer 304 an initial retraction distance to remove the end portions of the first semiconductor layer 304, such that the end portions of the first semiconductor layer 304 terminate below (e.g., aligned with) the gate spacer 702. It should be understood that the retraction distance (i.e., the degree to which each semiconductor layer 304 is etched or retracted) can be arbitrarily increased or decreased. Due to the etch selectivity between the first semiconductor layer 304 and the second semiconductor layer 306, the second semiconductor layer 306 remains substantially intact during this etch process.

[0172] Next, an inner isolation layer 704 is formed on the exposed end portion of the first semiconductor layer 304 in the source / drain trench 706. The inner isolation layer 704 may include any suitable dielectric material as described herein with respect to the inner isolation layer 11. The inner isolation layer 704 may be formed by depositing one or more layers of dielectric material over the exposed end portion of the first semiconductor layer 304 by CVD, ALD, physical vapor deposition (PVD), other suitable methods, or combinations thereof. The dielectric material may then be etched by isotropic or anisotropic etching processes to remove excess dielectric material from the sidewalls of the second semiconductor layer 306 and the top surface of the substrate 302.

[0173] Subsequently, source / drain features 802 are formed in source / drain recesses 706 above the inner isolation layer 704. Source / drain features 802 may include any suitable semiconductor material as described herein with respect to source / drain features 14. In some embodiments, source / drain features 802 are aligned with the end portions of the inner isolation layer 704 and the second semiconductor layer 306. Source / drain features 802 may be formed on the exposed ends of each second semiconductor layer 306 using epitaxial layer growth processes. For example, growth processes may include selective region epitaxial growth (SEG) processes, CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial processes, or combinations thereof. In some other embodiments, the bottom surface of the source / drain features 802 may be lower than the top surface of the isolation structure 504.

[0174] In-situ doping (ISD) can be applied to form the doped source / drain features 802, thereby creating the junction of the FST 1000. For example, when the FST 1000 is configured as an n-type device, the source / drain features 802 may comprise Si doped with the n-type dopant described herein. When the FST 1000 is configured as a p-type device, the source / drain features 802 may comprise SiGe doped with the p-type dopant described herein.

[0175] Please refer to Figure 15 and Figure 22According to various embodiments, in sub-operation 264, the dummy gate structure 600 is replaced with an active gate structure 900. Replacing the dummy gate structure 600 includes an ILD layer 806 first forming source / drain features 802. In some embodiments, the ILD layer 806 comprises substantially the same composition as the ILD layer 117 described herein. The ILD layer 806 can be deposited by any suitable method, such as CVD, PECVD, FCVD, other suitable methods, or combinations thereof. A planarization process, such as CMP, can then be performed to form a horizontal top surface of the ILD layer 806. CMP can also remove the hard mask 604. After performing the planarization process, the top surface of the ILD layer 806 can be substantially flush with or coplanar with the top surface of the dummy gate structure 600.

[0176] Then, please continue to refer to Figure 22 The dummy gate structure 600, etch stop layer 602, pattern mask 402 (if still present), and first semiconductor layer 304 are sequentially removed from device 300 using one or more suitable etching processes (e.g., wet etching, dry etching, RIE, chemical oxide removal (COR), other suitable processes, or combinations thereof). After removing the dummy gate structure 600, etch stop layer 602, and pattern mask 402 to form a gate trench (not shown), the top surface of each fin structure 400 (e.g., the top surface of the topmost semiconductor layer 306) is exposed. In addition to the top surface, the sidewalls of each fin structure 400 are also exposed. Next, the first semiconductor layer 304 is removed from each fin structure 400 by applying selective etching (e.g., hydrochloric acid (HCl)) to form an opening, while leaving a substantially intact second semiconductor layer 306. After removing the first semiconductor layer 304, the respective bottom and top surfaces of each second semiconductor layer 306 are exposed in the opening.

[0177] Please continue to refer to this. Figure 15 and Figure 22 According to some embodiments, in sub-operation 266, an active gate structure 900 is formed in an opening between a gate trench and a second semiconductor layer 306. Each active gate structure 900 has substantially the same structure and composition as the active gate structure 16 described herein. In various embodiments, the active gate structure 900 may be formed in an exposed cavity including a gate trench and an opening between the dummy gate structure 600 and the second semiconductor layer 306 left by the first semiconductor layer 304. In some embodiments, each of the active gate structures 900 includes a top portion disposed above the second semiconductor layer 306 and a bottom portion interleaved with or covering each of the second semiconductor layers 306.

[0178] The gate dielectric layer (not depicted separately) of the active gate structure 900 can be deposited using any suitable method, such as high-temperature oxidation, chemical oxidation, CVD, ALD, PVD, other suitable methods, or combinations thereof. The gate metal may comprise a stack of various metallic materials, such as work function metals and conductive fill layers, each of which can be formed by CVD, ALD, PVD, other suitable methods, or combinations thereof.

[0179] Then, please refer to Figure 15 , Figure 23A , Figure 23B , Figure 24A and Figure 24B In sub-operation 268, a subset (e.g., one or more) of the active gate structures 900 can be replaced with a dielectric structure 912, wherein the dielectric structure 912 is substantially similar to the dielectric structure 198 described herein. In some embodiments, sub-operation 268 is selective, and all active gate structures 900 remain in device 300. Please refer to... Figure 23A , Figure 23B , Figure 24A and Figure 24B It describes the process for forming the dielectric structure 912, in which Figure 23B and Figure 24B Depicting each Figure 23A and Figure 24A The corresponding top view.

[0180] In some embodiments, please refer to Figure 23A and Figure 23B First, a subset of the active gate structure 900 is removed through a series of photolithography and etching processes to form the trench 910. Then, please refer to... Figure 24A and Figure 24B The trench is then filled with one or more dielectric materials as described herein with respect to dielectric structure 198. In some embodiments, trench 910 extends vertically below the front side 302F and into substrate 302. A planarization process (e.g., CMP process) may then be performed to planarize the top surface of the dielectric structure with the top surface of the remaining active gate structure 900. As described above, dielectric structure 912 is configured to electrically isolate adjacent MCs that share a common source feature (see devices 100F, 100G, and 100H).

[0181] Please refer to Figure 15 and Figure 25According to some embodiments, various contact features, such as source / drain contacts 902 and gate contacts (not shown), are formed in sub-operation 270. The source / drain contacts 902 are at least disposed in the ILD layer 806 and configured to electrically couple the corresponding source / drain features 802 to the front-side interconnect structure 1100 (FSLs). The structure and composition of each source / drain contact 902 may be substantially the same as the structure and composition of the source / drain contact 18 described herein.

[0182] The source / drain contacts 902 can be formed by first patterning an ILD layer 806 disposed above the source / drain feature 802 to form contact trenches, and then depositing one or more conductive materials to form the source / drain contacts 902. A barrier layer (not shown) can be formed in the trenches before depositing the conductive material. The layers of the source / drain contacts 902 can be formed by PVD, CVD, ALD, electroplating (e.g., electroplating, electroless plating, etc.), other suitable methods, or combinations thereof. In some embodiments, each source / drain contact 902 further includes a silicide layer disposed above the corresponding source / drain feature 802. A planarization process (e.g., CMP process) can then be performed to planarize the top surface of the source / drain contacts 902 with the top surface of the active gate structure 900. Although not depicted, gate contacts can also be formed above the active gate structure 900 to electrically couple the active gate structure 900 to the FSLs 1100.

[0183] When execution Figure 15 During sub-operation 270, the manufacturing of FST 1000 in operation 202 of method 200 can be completed (see...). Figure 14 Next, method 200 proceeds to operation 204, which forms FSLs 1100 electrically coupled to FSTs 1000.

[0184] Please refer to Figure 14 and Figure 25According to various embodiments, FSLs 1100 has a structure substantially similar to that of FSLs 15 described herein, including multiple conductive features (e.g., vias and metal lines) 1002, 1004, 1006, and 1008 embedded in the corresponding IMD layers 1001, 1003, 1005, and 1007, respectively. Conductive features 1002 and 1006 can be configured as vias resembling vias V0 and V1, respectively, and conductive features 1004 and 1008 can be configured as metal lines resembling metal lines M0 and M1, respectively. The structure and composition of IMD layers 1001-1007 can be substantially the same as those of IMD layers 120-130 described herein, and can be formed by any suitable method, such as CVD, PECVD, or FCVD. It should be noted that conductive features 1002, 1004, 1006 and 1008, and IMD layers 1001, 1003, 1005 and 1007 are representative structures of FSLs 1100 and are not intended to limit FSLs 1100 to any particular configuration.

[0185] The conductive features 1002-1008 of the FSLs 1100 (and any conductive features subsequently formed thereon) can be formed by at least some of the following processes. As a representative example, a groove can be formed in one of the IMDs by an etching process (e.g., dry etching, wet etching, RIE, other suitable etching processes, or combinations thereof). The groove is then filled with a conductive material, followed by a CMP process to remove any excess conductive material, so that the top surface of the conductive features 1002-1008 is planarized with the top surface of the corresponding IMD layer. In some embodiments, the conductive features 1002-1008 can be formed in the corresponding IMD layers 1001-1007 by a damascene process (e.g., dual damascene process, single damascene process, etc.). The resulting conductive features embedded or encapsulated in their corresponding IMD layers are collectively referred to as metallization layers in the FSLs 1100.

[0186] As described above, conductive features 1002-1008 of the FSLs 1100 are formed to electrically couple the FSTs 1000 to other front-side elements. Although only conductive features 1002-1008 are shown connected to the source / drain features 802 of each FST 1000, it should be understood that at least one conductive feature of the FSLs 1100 may be connected to any active gate structure 900 of the FSTs 1000, all within the scope of the embodiments disclosed herein.

[0187] Please refer to Figure 14 and Figure 26According to some embodiments, after forming a portion of the FSLs 1100 (e.g., an assembly adjacent to substrate 302), at least one FSM 1200 is formed in operation 206 to be electrically coupled to the FSLs 1100 in a vertical direction. For simplicity, in Figure 26 and Figure 27 Two representative memory units, MC[0] and MC[1], are shown in the references to this paper. Figure 1 The memory unit MC[0] of the device 100A is similar to the memory unit MC[1].

[0188] In some embodiments, the FSM 1200 has substantially the same structure and composition as the FSM 80 described herein. In some embodiments, the FSM 1200 is configured as a capacitor having a MIM structure, which includes a bottom electrode 1019 (or a first metal layer), a top electrode 1021 (or a second metal layer), and a dielectric layer 1023 (e.g., an insulating layer) interposed therebetween.

[0189] In some embodiments, the FSM 1200 is formed compatiblely with conductive features 1002-1008 in the FSLs 1100. For example, each of the bottom electrode 1019, dielectric layer 1023, and top electrode 1021 can be formed by patterning the IMD layer 1009 to form a trench (not shown), and the bottom electrode 1019, dielectric layer 1023, and top electrode 1021 are sequentially formed in the trench by CVD, ALD, PVD, electroplating, other suitable processes, or combinations thereof. In the depicted embodiment, the FSM 1200 is formed in the IMD layer 1009. After the FSM 1200 is formed, additional portions of the FSLs 1100 are formed in the device 300, which may include conductive features 1026 in the IMD layer 1025 and vias 1022 and 1024 in the IMD layer 1009. Through-holes 1022 and 1024 electrically couple the bottom electrode 1019 and the top electrode 1021 to portions of the FSLs 1100, respectively.

[0190] Please refer to Figure 14 and Figure 27 According to some embodiments, in operation 208, the substrate 302 is flipped and further processed. For example, after forming the topmost metallization layer of FSLs 1100 on the front side 302F of the substrate 302, a carrier substrate (not shown) can be attached to the topmost metallization layer, and after flipping the substrate 302, a partially completed device 300 is formed thereon.

[0191] After flipping substrate 302, please continue to refer to... Figure 14 and Figure 27According to some embodiments, in operation 210, a polishing process (e.g., CMP process) is performed on the rear side 302B to expose a portion of one or more FSTs 1000. In some embodiments, by performing the polishing process on the rear side 302B, the drain feature 802 of one or more FSTs 1000 is exposed.

[0192] Please refer to Figure 14 and Figure 27 Continuing with method 200, according to some embodiments, in operation 212, BSLs 1300 are formed on the back surface 302B of device 300. The structure, composition, and manufacturing method of BSLs 1300 may be substantially similar to or identical to the structure, composition, and manufacturing method of FSLs 1100. For example, BSLs 1300 includes multiple representative IMD layers 1101, 1103, 1105, 1107, 1135, and 1137, as... Figure 27 As shown. BSLs 1300 also include several representative conductive features embedded in the respective IMD layers 1103, 1107 and 1137, such as vias 1102 and 1106 and metal lines 1104, 1108, 1142 and 1150. In this embodiment, via 1102 extends vertically through the substrate 302 and electrically couples metal line 1104 to the rear side of the drain feature 802 of the memory cell MC[1].

[0193] Please continue to refer to this. Figure 14 and Figure 27 According to some embodiments, in operation 214, BSM 1400 is formed on the rear side 302B. The structure and composition of BSM 1400 may be substantially the same as those of BSM 40 described herein. For example, BSM 1400 is configured as a capacitor having a MIM structure formed in IMD layer 1135. BSM 1400 may include a bottom electrode 1141, a top electrode 1143, and a dielectric layer 145 sandwiched between the bottom electrode 1141 and the top electrode 1143. BSM 1400 may be formed in IMD layer 1135 in a manner similar to that of FSM 1200 described herein. In the depicted embodiments, similar to the embodiments of device 100A, for example, by forming BSM 1400 as part of memory cell MC[1], at least one of FSM 1200 and BSM 1400 may be formed with a size D1 larger than the cell size L1 of each of memory cell MC[0] and memory cell MC[1].

[0194] After the back-end components, including BSLs 1300 and BSM 1400, are formed, additional operations can be performed. For example, the carrier wafer can be removed from device 300, thereby completing the formation of device 300.

[0195] Therefore, this disclosure provides embodiments in which memory elements of a first subset of memory cells of a semiconductor device are formed on the front side of a substrate, and memory elements of a second subset of memory cells are formed on the rear side of a substrate opposite the semiconductor device. In some embodiments, the memory elements formed on the front side are formed in different IMD layers. In this way, various design rules followed by the memory cells can be relaxed compared to when all memory elements are formed on a given side (e.g., the front side) or in the same IMD layer on a given side, allowing memory elements to be formed in various sizes without significantly affecting the performance of the memory device. The rear-side components provided herein advantageously allow memory devices to continue to scale down while providing flexible wiring options, resulting in advancements in device architecture.

[0196] In one aspect of the embodiments disclosed herein, a semiconductor device is disclosed. This semiconductor device includes a first transistor disposed on a first side of a substrate, the first transistor including a pair of first source / drain features. This semiconductor device includes a plurality of first interconnect structures disposed on a second side of the substrate opposite to the first side. This semiconductor device includes a first memory element disposed on the second side, wherein the first memory element includes a first capacitor. The first memory element is electrically coupled to one of the pair of first source / drain features through the plurality of first interconnect structures.

[0197] In some embodiments described herein, a semiconductor device is provided. The first capacitor includes a dielectric layer sandwiched between a bottom electrode and a top electrode.

[0198] In some embodiments described herein, a semiconductor device is provided, wherein both the bottom electrode and the top electrode comprise ferromagnetic materials.

[0199] In some embodiments described herein, a semiconductor device is provided. The dielectric layer comprises a ferromagnetic material.

[0200] In some embodiments described herein, a semiconductor device is provided. A first transistor includes a plurality of nanostructures, with first source / drain features laterally coupled to one end of each of the plurality of nanostructures. The first transistor includes a gate structure surrounding each of the plurality of nanostructures.

[0201] In some embodiments described herein, a semiconductor device is provided. The semiconductor device further includes a second transistor disposed on a first side adjacent to a first crystal along a first lateral direction, the second transistor including a pair of second source / drain features. The semiconductor device further includes a plurality of second interconnect structures disposed above the second transistor on the first side. The semiconductor device further includes a second memory element disposed on the first side, the second memory element including a second capacitor, wherein the second memory element is electrically coupled to one of the pair of second source / drain features through the plurality of second interconnect structures.

[0202] In some embodiments described herein, a semiconductor device is provided. A first transistor and a first memory element are configured to form a first memory cell having a first dimension along a lateral direction and a second dimension along a lateral direction, the second dimension being larger than the first dimension.

[0203] In one aspect of the embodiments disclosed herein, a memory device is disclosed. This memory device includes a first memory cell and a second memory cell adjacent to the first memory cell along a first lateral direction. The first memory cell includes a first transistor disposed on a front side of a substrate. The first memory cell includes a plurality of first interconnect structures disposed above the first transistor on the front side. The first memory cell includes a first memory element disposed on the front side, wherein the first memory element is electrically coupled in series to the first transistor through the plurality of first interconnect structures. The second memory cell includes a second transistor disposed on the front side and spaced apart from the first transistor along the first lateral direction. The second memory cell includes a plurality of second interconnect structures disposed on a rear side of the substrate opposite to the front side. The second memory cell includes a second memory element disposed on the rear side, wherein the second memory element is electrically coupled in series to the second transistor through the plurality of second interconnect structures.

[0204] In some embodiments, some of the embodiments described herein provide a memory device. Each of the first transistor and the second transistor includes a plurality of semiconductor layers stacked along a vertical direction. Each of the first transistor and the second transistor includes a source feature and a drain feature disposed adjacent to the plurality of semiconductor layers along a first lateral direction. Each of the first transistor and the second transistor includes an active gate that is interleaved with the plurality of semiconductor layers.

[0205] In some embodiments described herein, a memory device is provided. A first memory element is series-coupled to the front side of a drain feature of a first transistor, and a second memory element is series-coupled to the rear side of a drain feature of a second transistor.

[0206] In some embodiments described herein, a memory device is provided. Each of the first memory element and the second memory element includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode.

[0207] In some embodiments described herein, a memory device is provided. At least one of a first memory cell and a second memory cell includes a magnetoresistive random access memory (MRAM) cell, wherein the top and bottom electrodes of the MRAM cell both contain iron doped with at least one of cobalt, boron, or nickel, and wherein the dielectric layer comprises magnesium oxide.

[0208] In some embodiments described herein, a memory device is provided. At least one of a first memory cell and a second memory cell includes a ferroelectric random access memory (FeRAM) cell, and the dielectric layer comprises a ferroelectric material.

[0209] In some embodiments described herein, a memory device is provided, wherein a first transistor and a second transistor share a common source characteristic.

[0210] In some embodiments described herein, a memory device is provided. The drain feature of a first transistor is separated from the drain feature of a second transistor along a first lateral direction by an electrically grounded dummy gate structure.

[0211] In some embodiments described herein, a memory device is provided. A first transistor includes a first active gate structure extending along a second lateral direction perpendicular to the first lateral direction. A second transistor includes a second active gate structure extending parallel to the first active gate structure. The memory device further includes a dielectric structure disposed between the first and second active gate structures and extending parallel to both structures.

[0212] In some embodiments described herein, a memory device is provided. A first memory cell has a first dimension along a first lateral direction, and a first memory element has a second dimension along the first lateral direction, the second dimension being larger than the first dimension. A second memory cell has a third dimension along the first lateral direction, and a second memory element has a fourth dimension along the first lateral direction, the fourth dimension being larger than the third dimension.

[0213] In another aspect of the embodiments disclosed herein, a method for manufacturing a semiconductor device is disclosed. The method includes forming a first transistor and a second transistor on a front side of a substrate, wherein the first transistor and the second transistor are spaced apart from each other along a first direction. The method includes forming a plurality of first interconnect structures over the first transistor on the front side. The method includes forming a first memory element on the front side, wherein the first memory element is electrically coupled in series to the first transistor through the plurality of first interconnect structures. The method includes forming a plurality of second interconnect structures on a rear side of the substrate opposite the front side. The method includes forming a second memory element over the plurality of second interconnect structures on the rear side, wherein the second memory element is electrically coupled in series to the rear side of the second transistor through the plurality of second interconnect structures.

[0214] In some embodiments, as described herein, forming the first transistor and the second transistor includes forming a stack on the front side consisting of alternating plurality of first semiconductor layers and plurality of second semiconductor layers; defining a fin structure in the stack extending along a first direction; forming a first dummy gate structure and a second dummy gate structure, the first dummy gate structure and the second dummy gate structure being spaced apart along the first direction and extending along a second direction perpendicular to the first direction; forming a first source feature and a first drain feature adjacent to the first dummy gate structure, and a second source feature and a drain feature adjacent to the second dummy gate structure, respectively; removing the plurality of first semiconductor layers, the first dummy gate structure and the second dummy gate structure to form a plurality of cavities; and forming a first active gate structure and a second active gate structure in the plurality of cavities, thereby generating the first transistor and the second transistor, respectively.

[0215] In some embodiments, as described herein, forming the plurality of second interconnect structures includes flipping the substrate, polishing the back side to expose the drain features of the second transistor, and forming the plurality of second interconnect structures including a portion electrically coupled to the drain features.

[0216] In one aspect of the embodiments disclosed herein, a semiconductor device is disclosed. This semiconductor device includes a first transistor disposed on a first side of a substrate, the first transistor including a pair of first source / drain features. This semiconductor device includes a plurality of first interconnect structures disposed on a second side of the substrate opposite to the first side. This semiconductor device includes a first memory element disposed on the second side, wherein the first memory element includes a first capacitor. The first memory element is electrically coupled to one of the pair of first source / drain features through the plurality of first interconnect structures. The first transistor and the first memory element are configured to form a first memory cell having a first dimension in a lateral direction and a second dimension in the lateral direction, the second dimension being larger than the first dimension.

[0217] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of the embodiments disclosed herein. Those skilled in the art should understand that the embodiments disclosed herein can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments disclosed herein, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the embodiments disclosed herein.

Claims

1. A semiconductor device, characterized in that, Include: A first transistor is disposed on a first side of a substrate, the first transistor including a pair of first source / drain features; Multiple first interconnect structures are disposed on a second side of the substrate opposite to the first side; and A first memory element is disposed on the second side, the first memory element including a first capacitor, wherein the first memory element is electrically coupled to one of the pair of first source / drain features through the plurality of first interconnect structures.

2. The semiconductor device as claimed in claim 1, characterized in that, The first capacitor includes a dielectric layer sandwiched between a bottom electrode and a top electrode.

3. The semiconductor device as claimed in claim 2, characterized in that, Both the bottom electrode and the top electrode contain a ferromagnetic material.

4. The semiconductor device as claimed in claim 2, characterized in that, The dielectric layer contains a ferromagnetic material.

5. The semiconductor device as claimed in claim 1, characterized in that, The first transistor includes: Multiple nanostructures, wherein the first source / drain feature is laterally coupled to one end of the multiple nanostructures, and A gate structure surrounds each of the plurality of nanostructures.

6. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A second transistor is disposed on the first side adjacent to the first transistor along a first lateral direction, the second transistor including a pair of second source / drain features; Multiple second interconnect structures are disposed above the second transistor on the first side; and A second memory element is disposed on the first side, the second memory element including a second capacitor, wherein the second memory element is electrically coupled to one of the pair of second source / drain features through the plurality of second interconnect structures.

7. The semiconductor device as claimed in claim 1, characterized in that, The first transistor and the first memory element are configured to form a first memory cell, the first memory cell having a first dimension along a lateral direction and a second dimension along the lateral direction, the second dimension being larger than the first dimension.

8. A memory device, characterized in that, Include: The first memory unit contains: A first transistor is disposed on a front side of a substrate. Multiple first interconnect structures are disposed above the first transistor on the front side, and A first memory element is disposed on the front side, wherein the first memory element is electrically coupled to the first transistor in series through the plurality of first interconnect structures; and A second memory unit, adjacent to the first memory unit along a first lateral direction, includes: A second transistor is disposed on the front side and spaced apart from the first transistor along the first lateral direction. Multiple second interconnect structures are disposed on a rear side of the substrate opposite to the front side, and A second memory element is disposed on the rear side, wherein the second memory element is electrically coupled to the second transistor in series through the plurality of second interconnect structures.

9. The memory device as claimed in claim 8, characterized in that, Each of the first transistor and the second transistor includes: Multiple semiconductor layers are stacked along a vertical direction. A source feature and a drain feature are respectively disposed adjacent to the plurality of semiconductor layers along the first lateral direction, and An active gate is interleaved with the plurality of semiconductor layers.

10. A semiconductor device, characterized in that, Include: A first transistor is disposed on a first side of a substrate, the first transistor including a pair of first source / drain features; Multiple first interconnect structures are disposed on a second side of the substrate opposite to the first side; and A first memory element is disposed on the second side, the first memory element includes a first capacitor, wherein the first memory element is electrically coupled to one of the pair of first source / drain features through the plurality of first interconnect structures, and wherein the first transistor and the first memory element are configured to form a first memory cell, the first memory cell having a first dimension along a lateral direction, and the first memory cell having a second dimension along the lateral direction, the second dimension being larger than the first dimension.

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