Capacitor device and semiconductor device

Abstract

A capacitor device and a semiconductor device are provided. The capacitor device includes a substrate, a well, and a plurality of trenches. The well is located in the substrate, wherein the well is to serve as a first electrode of the capacitor device. The trenches are surrounded by the well in a layout view, wherein a first trench of the trenches has two rounded ends along a first direction in the layout view, wherein two adjacent ones of the trenches are separated from each other by a first distance, wherein the trenches are to serve as a second electrode of the capacitor device.

Description

Technical Field

[0001] This disclosure relates to a capacitor device and a semiconductor device, and more particularly to a capacitor device and a semiconductor device having a trench. Background Technology

[0002] Some applications, such as buck converters, use external voltages, typically multilayer ceramic capacitors (MLCCs). These external MLCCs can lead to high bill of materials costs and large form factors in system integration. The large parasitic inductance and resistance of these external MLCCs cause inductor-capacitor (LC) resonance and charge loss, making them unsuitable for high-frequency applications and limiting power density and performance. Furthermore, the temperature coefficient of capacitance (TCC) and voltage coefficient of capacitance (VCC) of MLCCs are not suitable for high-power applications. Therefore, suitable on-chip solutions are needed to overcome these problems. Utility Model Content

[0003] Some embodiments disclosed herein provide a capacitor device. The capacitor device includes a substrate, a well, and a plurality of trenches. The well is located in the substrate, wherein the well serves as a first electrode of the capacitor device. The trenches are surrounded by the well in a layout view, wherein a first trench among the trenches has two rounded ends along a first direction in the layout view, wherein adjacent trenches are separated from each other by a first distance, wherein the trenches serve as a second electrode of the capacitor device.

[0004] Some embodiments disclosed herein provide a semiconductor device including an integrated circuit and a capacitor. The capacitor is coupled to the integrated circuit, wherein the capacitor and the integrated circuit are located within a wafer. The capacitor includes a well and a plurality of trenches. The well serves as a first electrode of the capacitor. In a layout view, the trenches are arranged in a plurality of rows and surrounded by the well. The trenches of adjacent rows are staggered. The first trench among these trenches has two rounded ends along a first direction in the layout view. These trenches serve as a second electrode of the capacitor.

[0005] Some embodiments disclosed herein provide a capacitor device. The capacitor device includes a substrate, a well, a plurality of trenches, and a deep well. The well is located in the substrate, wherein the well serves as the cathode of the capacitor device. The trenches are surrounded by the well in a layout view, wherein a first trench in the layout view has two rounded ends along a first direction, wherein adjacent trenches are separated from each other by a first distance, and wherein the trenches serve as the anode of the capacitor device. The deep well is located below the well in the substrate, wherein the trenches are surrounded by the deep well in the layout view. Attached Figure Description

[0006] The embodiments of this case will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figure 1 This is a schematic diagram of a system according to some embodiments of the present disclosure;

[0008] Figure 2 Illustrations based on some embodiments of this disclosure Figure 1 An example layout view of the system;

[0009] Figure 3 A layout view of an example capacitor is illustrated according to some embodiments of this disclosure;

[0010] Figure 4 Some embodiments illustrated in this disclosure Figure 3 An example layout view of a capacitor;

[0011] Figure 5 Cross-sectional views of capacitors are shown according to some embodiments of this disclosure;

[0012] Figure 6 Based on some embodiments illustrated in this disclosure, for Figure 5 An example capacitor shown in a cross-sectional view;

[0013] Figure 7 Some embodiments illustrated in this disclosure Figure 5 An example capacitor shown in a cross-sectional view;

[0014] Figure 8 Some embodiments illustrated in this disclosure Figure 5 An example capacitor shown in a cross-sectional view;

[0015] Figure 9 Examples of capacitors connected in parallel are illustrated according to some embodiments of this disclosure;

[0016] Figure 10 Examples of capacitors connected in series are illustrated according to some embodiments of this disclosure;

[0017] Figure 11 Based on some embodiments illustrated in this disclosure, a corresponding [structure / form] is formed. Figures 1 to 10 A cross-sectional view of one stage of the system's process;

[0018] Figure 12 Some embodiments illustrated in this disclosure Figure 11 A cross-sectional view of a stage of the process that forms the system, following the previous stage;

[0019] Figure 13 Some embodiments illustrated in this disclosure Figure 12 A cross-sectional view of a stage of the process that forms the system, following the previous stage;

[0020] Figure 14 Some embodiments illustrated in this disclosure Figure 13 A cross-sectional view of a stage of the process that forms the system, following the previous stage;

[0021] Figure 15 Some embodiments illustrated in this disclosure Figure 14 A cross-sectional view of a stage of the process that forms the system, following the previous stage;

[0022] Figure 16 Some embodiments illustrated in this disclosure Figure 15 A cross-sectional view of a stage of the process that forms the system, following the previous stage;

[0023] Figure 17 Some embodiments illustrated in this disclosure Figure 16 A cross-sectional view of a stage of the process that forms the system, following the previous stage;

[0024] Figure 18 Some embodiments illustrated in this disclosure Figure 17 A cross-sectional view of a stage of the process that forms the system, following the previous stage;

[0025] Figure 19 Manufacturing according to some embodiments of this disclosure, such as Figures 1 to 18 A flowchart of the system and capacitor method shown;

[0026] Figure 20 This is a block diagram of an electronic design automation system for designing integrated circuit layouts according to some embodiments of this disclosure;

[0027] Figure 21 This is a block diagram of an integrated circuit manufacturing system and an associated integrated circuit manufacturing process according to some embodiments of this disclosure.

[0028] [Symbol Explanation]

[0029] 10: System

[0030] 11: Integrated Circuits

[0031] 100: Capacitor

[0032] 20: Method

[0033] 200: Circuit

[0034] 2000: System

[0035] 201: Driver

[0036] 2010: I / O Interface

[0037] 202: Driver

[0038] 2020: Processor

[0039] 203: Load

[0040] 2030: Network Interface

[0041] 204: Capacitor

[0042] 2040: Network

[0043] 2050: Bus

[0044] 2060: Storage Media

[0045] 2061: Instruction

[0046] 2062: Library

[0047] 2063: User Interface

[0048] 2070: Manufacturing Tools

[0049] 21: Steps

[0050] 210: High-side switching circuit

[0051] 2100: Manufacturing System

[0052] 211: Transistor

[0053] 2110: Design Company

[0054] 2111: Layout Diagram

[0055] 2120: Mask Company

[0056] 2121: Data Preparation

[0057] 2122: Masking Creation

[0058] 2123: Mask

[0059] 2130: Production Company

[0060] 2131: Wafer Fabrication

[0061] 2132: Wafer

[0062] 2140: IC device

[0063] 22: Steps

[0064] 220: Low-side switching circuit

[0065] 221: Transistor

[0066] 23: Steps

[0067] 230: High-voltage level converter and front drive circuit

[0068] 24: Steps

[0069] 240: Input / Output and Analog Circuits

[0070] 25: Steps

[0071] 250: Logic Circuits

[0072] 26: Steps

[0073] 300: Capacitor

[0074] 300a: Capacitor

[0075] 300b: Capacitor

[0076] 300c: Capacitor

[0077] 301: Base

[0078] 310: Trench

[0079] 601: Metal Wire

[0080] 610:n-type planting area

[0081] 620: High K value lining

[0082] A: Anode

[0083] A1~A3: Anode

[0084] AA' : line segment

[0085] C: Cathode

[0086] C1~C3: Cathode

[0087] d: depth

[0088] D1: Diode

[0089] GND: Earth

[0090] h: height

[0091] j: Angle

[0092] L: Length

[0093] L1: Inductor

[0094] N1: Node

[0095] r: radius

[0096] R1~R5: Rows

[0097] s: distance

[0098] Vcc: Voltage

[0099] Vin: Voltage

[0100] Vout: Voltage

[0101] w: width

[0102] x: direction

[0103] y: direction

[0104] z: Direction Detailed Implementation

[0105] The following disclosure provides various implementations or examples to achieve different features of the subject matter. To simplify this disclosure, examples of specific elements, materials, values, steps, layouts, or similar items are described below. These are merely examples and are not intended to be limiting. Other elements, materials, values, steps, layouts, or similar items are also within the scope of the embodiments disclosed herein. For example, when a first feature is formed on or above a second feature in the following description, it may include implementations where the first and second features are in direct contact, or implementations where other features are formed between the first and second features, such that the first and second features are not necessarily in direct contact.

[0106] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0107] The terminology used in this disclosure generally has its ordinary meaning as clearly established in the art or in the specific context in which it is used. Those skilled in the art will understand that elements or processes may be referred to by different names. The numerous different embodiments detailed herein are merely illustrative and are in no way intended to limit the scope and spirit of this disclosure or any of the exemplary terminology.

[0108] The terms “comprising,” “including,” “having,” “containing,” etc., as used herein are open-ended, meaning they include but are not limited to the content described. In this document, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0109] In this text, "approximately," "about," "approximately," or "substantially" generally means within 20%, 10%, or 5% of a given value or range. All numerical values ​​mentioned herein are approximate, meaning that the meaning of the terms "approximately," "about," "approximately," or "substantially" can be inferred even if not explicitly stated. Those skilled in the art will understand that dimensions can vary at different process nodes. They will also recognize that dimensions depend on factors such as the specific device type, process generation, and minimum feature size. Therefore, this terminology should be interpreted within the context of the assessed technology.

[0110] In some circuits, especially those involving high-side switches, such as buck converters, boost circuits, load switches, and low dropout regulators (LDOs), external capacitors are often used.

[0111] External capacitors are often implemented using relatively large components, such as multi-layer ceramic capacitors (MLCCs). These relatively large components can increase printed circuit board (PCB) area and bill of materials costs, posing a challenge for small devices like wearable devices.

[0112] External capacitors often result in large parasitic inductance and resistance values, which may cause inductor-capacitor (LC) resonance and charge loss, thus limiting the performance of high-frequency applications and hindering the improvement of power density and efficiency.

[0113] In addition, external capacitors require additional pins on the chip, which may increase the pin count and consume the electrostatic discharge (ESD) protection area on the chip.

[0114] Even though some capacitors, such as metal-insulator-metal (MIM) capacitors and poly-insulator-poly (PIP) capacitors, have relatively small sizes, their capacitance values ​​are typically in the femtofarad range. This is far smaller than the nanofarad values ​​required for applications such as high-side switches.

[0115] Some embodiments disclosed herein provide on-chip capacitors that are highly area-efficient and provide sufficiently large capacitance values, effectively solving the aforementioned problems.

[0116] Some embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals and / or letters will be used in all drawings to refer to the same or similar parts.

[0117] Please refer to Figure 1 . Figure 1 This is a schematic diagram of a system 10 according to some embodiments of the present disclosure. In some embodiments, system 10 is a semiconductor device. In some embodiments, system 10 is an integrated circuit.

[0118] like Figure 1 As shown, system 10 includes capacitor 100 and circuitry 200 coupled to capacitor 100. According to some embodiments, circuitry 200 may be logic circuitry, memory circuitry, circuitry with high-side switching (e.g., buck converter, boost circuitry, load switch, and low-dropout regulator), etc. Capacitor 100 is used to perform functions for circuitry 200 such as providing an appropriate voltage level and maintaining voltage stability.

[0119] According to different embodiments, capacitor 100 can be used as a bootstrap capacitor, de-ripple capacitor, decoupling capacitor or other type of capacitor in circuit 200.

[0120] In some embodiments, capacitor 100 is an on-chip capacitor. Specifically, capacitor 100 and circuit 200 are located on the same chip.

[0121] In some embodiments, circuit 200 is a power supply circuit. In some embodiments, circuit 200 is a switch-mode power supply (SMPS), such as a buck converter.

[0122] In other words, Figure 1 The illustrated circuit 200 is an example of a buck converter. Figure 1As shown, in some embodiments, circuit 200 includes diode D1, driver 201, driver 202, high-side switching circuit 210, low-side switching circuit 220, inductor L1, capacitor 204 and load 203.

[0123] like Figure 1 As shown, diode D1 is coupled between voltage Vcc and the anode A of capacitor 100. The cathode C of capacitor 100 is coupled to node N1. High-side switching circuit 210 is coupled between voltage Vin and node N1. Low-side switching circuit 220 is coupled between node N1 and ground GND.

[0124] Driver 201 is coupled to high-side switching circuit 210. Driver 202 is coupled to low-side switching circuit 220. Inductor L1 is coupled to node N1. Capacitor 204 is coupled between inductor L1 and ground GND.

[0125] In some embodiments, the high-side switching circuit 210 includes transistor 211. The low-side switching circuit 220 includes transistor 221. In some embodiments, transistors 211 and 221 are n-type metal-oxide-semiconductor transistors (NMOS).

[0126] Transistor 211 is coupled between voltage Vin and node N1. The gate of transistor 211 is coupled to driver 201. Transistor 221 is coupled between node N1 and ground GND. The gate of transistor 221 is coupled to driver 202.

[0127] In some embodiments, drivers 201 and 202 are used to provide gate voltages to transistors 211 and 221, respectively. By controlling the conductivity of transistors 211 and 221 through drivers 201 and 202, circuit 200 generates a voltage Vout with an appropriate voltage level for load 203 based on voltage Vin.

[0128] In some embodiments, capacitor 100 operates as a bootstrap capacitor for circuit 200. Specifically, capacitor 100 stores and supplies the necessary electrical charge to provide a stable high-side drive voltage above voltage Vcc to the gate of transistor 211, enabling transistor 211 to be fully turned on in the on state of high-side switching circuit 210.

[0129] Please refer to Figure 2 . Figure 2 Illustrations based on some embodiments of this disclosure Figure 1 This is an example layout view of System 10. For the sake of brevity, the specific operations of similar components, which have been discussed in detail in previous paragraphs, are omitted in this article.

[0130] like Figure 2 As shown, system 10 includes integrated circuit 11. In some embodiments, integrated circuit 11 is a chip.

[0131] In some embodiments, integrated circuit 11 includes capacitor 100 and circuit 200 (in... Figure 2 (Not shown in the image). Circuit 200 also includes a high-voltage level-shifter and pre-drive circuit 230, input / output and analog circuitry 240, and logic circuitry 250.

[0132] In some embodiments, from a layout view (top-to-bottom view), logic circuitry 250 is located within input / output and analog circuitry 240. High-voltage level converter and front-drive circuitry 230 are adjacent to input / output and analog circuitry 240 along direction x. Capacitor 100, high-side switching circuitry 210, and low-side switching circuitry 220 are adjacent to high-voltage level converter and front-drive circuitry 230 along direction x.

[0133] Capacitor 100 is adjacent to high-side switching circuit 210 along direction y, which is perpendicular to direction x. High-side switching circuit 210 is adjacent to low-side switching circuit 220 along direction y.

[0134] According to some embodiments, such as Figure 2 The configuration shown is beneficial for efficient use of space.

[0135] In some embodiments, capacitor 100 is a silicon capacitor, compatible with process technologies such as Complementary Metal-Oxide-Semiconductor (CMOS) and Bipolar-CMOS-DMOS (BCD). In some embodiments, this silicon capacitor is a high-density deep trench capacitor, which, compared to some other methods, helps to increase the operating voltage of technologies such as high voltage (HV) and BCD. Specific details regarding silicon capacitors will be provided in the following paragraphs.

[0136] Please refer to Figure 3 . Figure 3 A layout view of an example capacitor 300 is illustrated according to some embodiments of this disclosure.

[0137] like Figure 3As shown, capacitor 300 includes a substrate 301 and one or more trenches 310. In some embodiments, substrate 301 is a silicon substrate. In some embodiments, substrate 301 is shared by circuit 200. For example, circuit 200 is disposed on substrate 301. It should be understood that, herein, trench refers to a structure comprising trench regions and material (e.g., semiconductor) filling the trench regions.

[0138] In some embodiments, in a layout view of capacitor 300, trench 310 is within substrate 301. For simplicity, some elements of capacitor 300, such as isolation structures, are not shown.

[0139] In some embodiments, substrate 301 includes a well (not shown) that surrounds trench 310 in a layout view. In some embodiments, trench 310 serves as a first electrode of capacitor 300, while the well serves as a second electrode of capacitor 300. The first electrode and the second electrode have different polarities.

[0140] In some embodiments, trench 310 is an n-type semiconductor. Substrate 301 is a p-type substrate. Well is an n-type well. In some embodiments, depending on the equivalent series resistance of capacitor 300, the n-type well may be a POCl3 glass-doped or n-type well-doped n-type semiconductor compatible with standard HV or BCD processes.

[0141] In some embodiments, the trenches 310 are arranged in multiple rows (e.g., rows R1 to R5).

[0142] In some embodiments, the grooves 310 in a row and the grooves 310 in adjacent rows are staggered. For example, in the y-direction, the grooves 310 in row R1 are not directly aligned with the grooves 310 in the adjacent row R2.

[0143] In some embodiments, the grooves 310 in the odd-numbered rows are aligned with each other along the y-direction. For example, as Figure 3 As shown, the groove 310 in row R1 is aligned with the groove 310 in row R3 along the y-direction.

[0144] Similarly, in some embodiments, the grooves 310 in even-numbered rows are aligned with each other along the y-direction. For example, as... Figure 3 As shown, the groove 310 in row R2 is aligned with the groove 310 in row R4 along the y-direction.

[0145] like Figure 3As shown in the layout view, the trench 310 is shaped as a line segment with rounded ends. According to different embodiments, the rounded ends provide good uniformity in physical thickness and electric field distribution around the surface of the trench 310, which helps to reduce the fringing effect.

[0146] In some embodiments, the two ends of the groove 310 are identical curves. In some embodiments, the two ends of the groove 310 are conic curves. In some embodiments, the two ends of the groove 310 are circular curves (arcs). In some embodiments, the radius of curvature of the curves at both ends of the groove 310 is half the width of the line segment. In other words, one end of the groove 310 is a semicircle with a radius r, where the radius r is equal to half the width w of the line segment.

[0147] In some embodiments, there is a trench spacing specification of distance s. Specifically, each trench 310 and its adjacent trenches 310 are separated by a distance greater than distance s. In some embodiments, for all trenches 310, the shortest distance between two adjacent trenches 310 is distance s.

[0148] Please refer to Figure 4 , Figure 4 Some embodiments illustrated in this disclosure Figure 3 An example layout view of capacitor 300.

[0149] like Figure 4 As shown, in some embodiments, the groove 310 in the layout view is circular. In other words, the length of the line segment portion of the groove 310 is zero, and therefore its shape is circular.

[0150] Please refer to Figure 5 . Figure 5 A cross-sectional view of capacitor 300 is shown according to some embodiments of this disclosure.

[0151] Figure 5 Draw along Figure 4 The diagram shows a cross-sectional view of line segment AA'. Line segment AA' is the centerline of a row of grooves 310 along the x-direction. It should be understood that the number of grooves 310 is exemplary. The number of grooves 310 in a row may not be four.

[0152] In some embodiments, each trench 310 has a depth d. In some embodiments, the capacitance of capacitor 300 is the trench surface area multiplied by this depth and the number of trenches. For example, the capacitance of capacitor 300 can be expressed as the equation: C total =2π×r×d×N.

[0153] In the equation, C totalThis represents the total capacitance value within a specific area in the layout view. r represents the radius of trench 310 in the layout view. d represents the depth of trench 310. N represents the number of trenches 310 within this specific area. The number N varies according to the trench spacing specification at a distance s.

[0154] Please refer to Figure 6 . Figure 6 Based on some embodiments illustrated in this disclosure, for Figure 5 An example of capacitor 300a is shown in the cross-sectional view.

[0155] In some embodiments, capacitor 300a includes metal wires 601, which serve as either the anode (denoted as A) or the cathode (denoted as C) of capacitor 300a. In some embodiments, the metal wires 601 of the anode and the metal wires 601 of the cathode are staggered along the x-direction.

[0156] In some embodiments, trench 310 is used as the anode of capacitor 300a. The metal wire 601 of the anode is coupled to trench 310 via a contact structure.

[0157] In some embodiments, the top portion of trench 310 is doped to become an N+ doped region. The metal line 601 of the anode is coupled to trench 310 through a coupling contact structure and the N+ doped region.

[0158] In some embodiments, trench 310 is surrounded by an n-type well. In some embodiments, trench 310 is further surrounded by a deep n-type well (DNW) or an n-type buried layer (NBL) below the n-type well.

[0159] In some embodiments, such as Figure 6 As shown, the lower part of the trench 310 extends from the n-type trap and DNW / NBL.

[0160] In some embodiments, the trench 310 is surrounded by an n-shaped implantation region 610. Specifically, in the substrate 301, the n-shaped implantation region 610 forms a shell-like structure surrounding the trench 310.

[0161] In some embodiments, the n-type planting region 610, the n-type well, and the DNW / NBL are used as cathodes. The metal wire 601 of the cathode is coupled to the planting region 610 and / or the n-type well through a contact structure.

[0162] In some embodiments, the top portion of the n-type implanted region 610 and / or the n-type well is doped with an N+ doped region. The cathode metal line 601 is coupled to the implanted region 610 or the n-type well through a contact structure and the N+ doped region.

[0163] like Figure 6 As shown, the N+ doped regions are separated by shallow trench isolation (STI). Specifically, in some embodiments, the N+ doped regions of the anode and the N+ doped regions of the cathode are separated by STI to avoid mismatched capacitors and leakage current caused by damage during HV and BCD processes.

[0164] In some embodiments, the trench 310 and the n-type planting area 610 are separated by a high-K liner 620. The high-K liner 620 serves as the dielectric layer of the capacitor 300a.

[0165] In some embodiments, capacitor 300a has five parameters: length L, distance s, depth d, height h, and angle j.

[0166] The length L is the length of the groove 310 along the direction x. In some embodiments, the length L is the length of the top surface of the groove 310 along the direction x.

[0167] Distance s is as follows Figure 3 and Figure 4 The distance between the trenches 310 shown. In some embodiments, the distance s is the distance between the top surfaces of the trenches 310.

[0168] Depth d is the depth of trench 310. Specifically, depth d is the distance from the top surface of trench 310 to the bottom of trench 310.

[0169] The capacitance of capacitor 300a is determined by the length L, distance s, and depth d. In some embodiments, the capacitance of capacitor 300a is proportional to the depth d and inversely proportional to the length L and distance s.

[0170] The length L and distance s are limited by the minimum contact structure and STI specifications. According to some embodiments, for process nodes from 90 nm to 0.25 μm, the length L and distance s are approximately 0.8 to 1.5 μm.

[0171] The depth d is limited by the aspect ratio of the trench 310. In some embodiments, the aspect ratio of the trench 310 is approximately 5 to 20 to achieve a balance between capacitance requirements and process capability. For example, the length L is approximately 1 μm and the depth d is approximately 5 to 20 μm.

[0172] like Figure 6 As shown, in some embodiments, the bottom of the trench 310 is a sphere cap structure. The height h is the height of the sphere cap structure. In some embodiments, the height h is less than half the length L and greater than one-quarter of the length L to reduce edge effects.

[0173] like Figure 6 As shown, angle j is the angle of the sidewall of groove 310. Specifically, angle j is the angle between the portion of groove 310 above the spherical cap structure and the horizontal plane.

[0174] A smaller angle j makes it more difficult to fill the high-K value liner 620 and the trench 310 electrode. A larger angle j results in a smaller distance s. In some embodiments, the angle j is greater than 90 degrees (e.g., about 91 to 93 degrees). In other words, the sidewalls of the trench 310 are inclined at an angle greater than zero from the vertical plane.

[0175] Please refer to Figure 7 , Figure 7 Some embodiments illustrated in this disclosure Figure 5 An example of capacitor 300b is shown in the cross-sectional view of capacitor 300.

[0176] Figure 7 300b capacitor and Figure 6 The configuration of the 300A capacitor is similar. Figure 7 300b capacitor and Figure 6 The difference between capacitor 300a and capacitor 300b is that the depth d of the trench 310 in capacitor 300b is less than the depth of the n-type well and DNW / NBL. Therefore, capacitor 300b does not have an n-type planting area 610.

[0177] Please refer to Figure 8 . Figure 8 Some embodiments illustrated in this disclosure Figure 5 An example of capacitor 300c is shown in the cross-sectional view.

[0178] Figure 8 The capacitor 300c in Figure 6 The configuration of the 300A capacitor is similar. Figure 8 300c capacitor and Figure 6 The difference between capacitor 300a and capacitor 300c is that only the top surface of the outermost n-type planting area 610 is coupled to the metal line 601.

[0179] Please refer to Figure 9 . Figure 9 Examples of parallel capacitors 300, 300a, 300b, or 300c are illustrated according to some embodiments of this disclosure.

[0180] In some embodiments, blocks of a plurality of capacitors 300 (or capacitors 300a to 300c) are connected in parallel to form capacitor 100.

[0181] For example, blocks of two capacitors 300 are arranged in the substrate 301 along the x-direction. The trenches 310 of these capacitors 300 are jointly coupled to the anode. The n-type implanted regions 610 and n-type wells of these capacitors 300 are jointly coupled to the cathode. Specifically, the N+ doped regions of the trenches 310 are coupled to the metal lines 601 of the anode. These anode metal lines 601 are coupled together. The N+ doped regions of the trenches 310 are coupled to the metal lines 601 of the cathode. These cathode metal lines 601 are coupled together.

[0182] Please refer to Figure 10 . Figure 10 Examples of capacitors 300, 300a, 300b, or 300c connected in series are illustrated according to some embodiments of this disclosure.

[0183] In some embodiments, blocks of multiple capacitors 300 (or capacitors 300a to 300c) are connected in series to form capacitor 100 to provide a larger operating voltage (e.g., about 15V).

[0184] For example, the first capacitor 300 has an anode A1 and a cathode C1. The cathode C1 is coupled to the anode A2 of the second capacitor 300. The cathode C2 of the second capacitor 300 is coupled to the anode A3 of the third capacitor 300.

[0185] It should be noted that Figure 9 and Figure 10 The number of capacitor blocks shown is merely an example. Any number of capacitor blocks connected in series or parallel is within the scope of this disclosure.

[0186] Please refer to Figure 11 . Figure 11 Based on some embodiments illustrated in this disclosure, a corresponding [structure / form] is formed. Figures 1 to 10 A cross-sectional view of a stage of the process of system 10. In some embodiments, this process is an HV and / or BCD process.

[0187] Figure 11 The areas of capacitor 100 and circuit 200 are shown. The area of ​​circuit 200 includes the areas of low-voltage (LV) CMOS circuitry (e.g., input / output and analog circuitry 240) and high-voltage (HV) devices (e.g., high-voltage level converters and pre-drive circuitry 230).

[0188] Capacitor 100 can be as follows Figures 3 to 10 The capacitors 300, 300a, 300b, 300c shown, and any of the blocks connected in series or in parallel.

[0189] exist Figure 11In this stage, an NBL is formed in a p-type substrate (e.g., substrate 301) by ion implantation. Then, an epitaxial layer (EPI) is formed on the substrate and the NBL.

[0190] Please refer to Figure 12 . Figure 12 Some embodiments illustrated in this disclosure Figure 11 A cross-sectional view of one stage of the process that forms system 10 after the previous stage.

[0191] exist Figure 12 During this stage, a hard mask is formed on the EPI layer, which is patterned using a photolithography process. The hard mask serves as an etching mask for the substrate (e.g., substrate 310). The material of the hard mask can be silicon oxide, silicon carbide, titanium nitride, amorphous carbon, etc.

[0192] Next, a trench etching operation is performed to remove the EPI, NBL, and exposed parts of the substrate, creating the trench region (the space that forms the trench).

[0193] In some embodiments, the trench etching operation comprises two steps. First, anisotropic etching is performed to control the depth of the trench. Then, isotropic etching is performed to arcuate the bottom.

[0194] In some embodiments, the hard mask pull-back operation is performed after the trench etching operation.

[0195] Please refer to Figure 13 . Figure 13 Some embodiments illustrated in this disclosure Figure 12 A cross-sectional view of one stage of the process that forms system 10 after the previous stage.

[0196] exist Figure 13 During this phase, an n-shaped implantation region (e.g., n-shaped implantation region 610) is formed through an implantation operation. In some embodiments, the implantation operation is an n-shaped gradient implantation operation. In some embodiments, the implantation operation has a tilt angle of about 7 to 30 degrees and about 2 to 4 rotations to provide better uniformity.

[0197] According to different embodiments, a gradient implantation operation is performed to increase the breakdown voltage from the bottom electrode to the substrate and reduce the parasitic PN junction capacitance between the n-type implantation region and the substrate so that the capacitance value of capacitor 100 is more accurate.

[0198] Next, the drive-in operation of the n-type planting area is performed. In some embodiments, the drive-in operation is performed at a temperature of about 1000°C or higher. In some embodiments, the drive-in operation is performed for about 2 to 4 hours.

[0199] In some embodiments, after the drive-in operation, a sacrificial oxide layer growth and removal operation is performed on the n-type implanted region. In some embodiments, the sacrificial oxide layer growth operation is performed at a temperature of about 950°C or greater, and at a growth depth of about 200 angstroms or greater.

[0200] Please refer to Figure 14 . Figure 14 Some embodiments illustrated in this disclosure Figure 13 A cross-sectional view of one stage of the process that forms system 10 after the previous stage.

[0201] exist Figure 14 During the phase, a high-K value liner (e.g., high-K value liner 620) is formed on the hard mask and n-type planting area.

[0202] High-k linings can be SiON, oxide-nitride-oxide (ONO), or HfO. x ZrO x Materials or structures, etc.

[0203] In one example where the high-K liner is ONO, the oxide formation and annealing of the bottom liner are performed on the hard mask and n-type planting areas to form a bottom oxide layer.

[0204] In some embodiments, the oxide generation of the bottom liner is performed using a CMOS standard gate oxide process or an in-situ steam generation (ISSG) oxide process.

[0205] In the case of a high-K value liner with ONO, a nitride layer is formed on the bottom oxide layer after the oxide formation and annealing operation of the bottom liner.

[0206] In some embodiments, the nitride layer is deposited using low-pressure chemical vapor deposition (LPCVD). In some embodiments, the LPCVD is performed at a temperature of approximately greater than 600°C.

[0207] The operating voltage (rated voltage) of capacitor 100 is based on the thickness of the nitride layer. Specifically, the operating voltage is inversely proportional to the trench capacitance. Therefore, the operating voltage is directly proportional to the thickness of the nitride layer. For example, capacitor 100 has an operating voltage of 5V, and the thickness of the nitride layer is approximately 80 to 150 angstroms.

[0208] In some embodiments, the thickness of the bottom oxide layer is approximately 0.5 to 1.5 times the thickness of the nitride layer.

[0209] In examples where the high-k liner is ONO, a top oxide layer is formed on top of the nitride layer after the nitride layer is formed. In some embodiments, the top oxide layer is formed using a wet oxidation process or an ISSG oxide process. In some embodiments, the top oxide process has a thickness of approximately 20 angstroms to alleviate stress between the nitride layer and the anode.

[0210] After the high-k substrate is formed, an n-type semiconductor is disposed on the high-k substrate. The n-type semiconductor can be n-type doped polysilicon (poly). In some embodiments, depending on process compatibility, the n-type semiconductor can be such as TiN / WSi. x The material was replaced.

[0211] Please refer to Figure 15 . Figure 15 Some embodiments illustrated in this disclosure Figure 14 A cross-sectional view of one stage of the process that forms system 10 after the previous stage.

[0212] exist Figure 15 During this phase, chemical-mechanical planarization (CMP) of the polysilicon, etching back of the n-type polysilicon, and / or polishing are performed. Next, the hard mask is removed to form trenches (e.g., trench 310).

[0213] Please refer to Figure 16 . Figure 16 Some embodiments illustrated in this disclosure Figure 15 A cross-sectional view of one stage of the process that forms system 10 after the previous stage.

[0214] exist Figure 16 During the stage, STI is formed for capacitor 100 and circuit 200.

[0215] Please refer to Figure 17 . Figure 17 Some embodiments illustrated in this disclosure Figure 16 A cross-sectional view of one stage of the process that forms system 10 after the previous stage.

[0216] In the stage shown in Figure 17, an N-type trap is formed on the NBL.

[0217] Please refer to Figure 18 . Figure 18 Some embodiments illustrated in this disclosure Figure 17 A cross-sectional view of one stage of the process that forms system 10 after the previous stage.

[0218] exist Figure 18 In the laterally diffused metal-oxide semiconductor for high-voltage devices, a high-voltage p-type body (HVPB) and a deep p-type well (DPW) are formed.

[0219] Next, N+ doped and P+ doped regions are formed. The gate of the LV CMOS is formed. The gate of the LDMOS is formed. Metal (e.g., metal line 601) and contact structures are formed to couple to the cathode or anode.

[0220] In some embodiments, Figure 18 During the process, gate oxide, polysilicon, sidewall, source, drain, silicide, etc. are formed.

[0221] Please refer to Figure 19 . Figure 19 Manufacturing according to some embodiments of this disclosure, such as Figures 1 to 18 A flowchart of method 20 for system 10 and capacitors 100, 300, 300a to 300c is shown. It should be understood that... Figure 19 Additional operations may be added before, between, and after the steps shown, and some steps described below may be replaced or removed for other embodiments of method 20. The order of the steps may be interchanged. Some steps may be performed synchronously. Method 20 includes steps 21 to 26, which will be referred to below. Figures 1 to 18 The system 10 and capacitors 100, 300, 300a to 300c are discussed.

[0222] In step 21, the hard mask is grown on the substrate, or on an EPI layer on the substrate. The hard mask has the following characteristics in the layout view: Figure 3 and Figure 4 The pattern shown is a groove shape (e.g., circular). Specifically, the uncovered areas on the substrate or EPI layer correspond to... Figure 3and Figure 4 The groove shown.

[0223] In step 22, an etching operation on the substrate or EPI layer is performed with a hard mask to form a trench region (e.g., the region of trench 310). In some embodiments, the etching operation includes two steps: performing anisotropic etching to control the depth of the trench region, and performing isotropic etching to round the bottom of the trench region.

[0224] In step 23, a gradient planting operation is performed on the trench region to form a planting region (e.g., an n-type planting region 610). In some embodiments, the gradient planting includes a first planting and a second planting. The first planting has a first planting concentration, which is greater than the second planting concentration of the second planting. The first planting has a first planting thickness, which is less than the second planting thickness of the second planting.

[0225] In step 24, as Figure 14 The high K-value lining shown is formed in the groove area.

[0226] In step 25, as Figure 14 The diagram shows a doped semiconductor used to fill the trench region.

[0227] In step 26, the hard mask is removed to form a capacitor (e.g., corresponding to...). Figures 1 to 18 Capacitors 100, 300, 300A to 300C).

[0228] Please refer to Figure 20 . Figure 20 This is a block diagram of an electronic design automation (EDA) system 2000 for designing integrated circuit layouts according to some embodiments disclosed herein. The EDA system 2000 is used to implement, for example... Figure 19 One or more steps of method 20 shown and Figures 2 to 4 The layout design shown.

[0229] In some embodiments, the EDA system 2000 is a general-purpose computing device including a hardware processor 2020 and a non-transitory computer-readable storage medium 2060. The storage medium 2060, etc., is encoded (i.e. stored) with (i.e., stored) instructions (computer program code) 1506, i.e., a set of executable instructions. The hardware processor 2020's execution of the instructions 2061 represents (at least partially) implementing, for example, method 20 and implementing, as... Figures 2 to 4 Some or all of the layout design methods of EDA tools.

[0230] Processor 2020 is electrically coupled to computer-readable storage medium 2060 via bus 2050. Processor 2020 is also electrically coupled to I / O interface 2010 via bus 2050. Network interface 2030 is also electrically connected to processor 2020 via bus 2050. Network interface 2030 is connected to network 2040, enabling processor 2020 and storage medium 2060 to be connected to external components via network 2040. Processor 2020 is used to execute instructions 2061 encoded in storage medium 2060 so that EDA system 2000 can be used to perform some or all of the described processes and / or methods. In one or more embodiments, processor 2020 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0231] In one or more embodiments, storage medium 2060 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, storage medium 2060 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), and hard disk and / or optical disk. In one or more embodiments using optical disk, storage medium 2060 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0232] In one or more embodiments, storage medium 2060 stores instructions 2061, which cause EDA system 2000 (where the execution representation (at least partially) EDA tool) to perform some or all of the said processes and / or methods. In one or more embodiments, storage medium 2060 also stores information facilitating the execution of some or all of the said processes and / or methods. In one or more embodiments, storage medium 2060 stores a library 2062 of standard units, including standard units such as those disclosed herein, for example... Figures 3 to 8 The capacitor block shown.

[0233] EDA system 2000 includes I / O interface 2010. I / O interface 2010 is coupled to external circuitry. In one or more embodiments, I / O interface 2010 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or directional keys for transmitting information and commands to processor 2020.

[0234] EDA system 2000 also includes a network interface 2030 coupled to processor 2020. Network interface 2030 allows EDA system 2000 to communicate with network 2040, to which one or more other computer systems are connected. Network interface 2030 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more EDA systems 2000.

[0235] The EDA system 2000 receives information via I / O interface 2010. The information received via I / O interface 2010 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 2020. The information is transmitted to processor 2020 via bus 2050. The EDA system 2000 also receives information related to the user interface (UI) via I / O interface 2010. This information is stored in computer-readable storage medium 2060, which serves as the user interface 2063.

[0236] In some embodiments, some or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the processes and / or methods are implemented as a software application that is part of another software application. In some embodiments, some or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the processes and / or methods are implemented as a software application used by an EDA system 2000. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGNSYSTEMS, or another suitable layout generation tool.

[0237] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs, RAMs, memory cards), and one or more of the like.

[0238] Figure 21This is a block diagram of an integrated circuit (IC) manufacturing system 2100 and associated IC manufacturing processes according to some embodiments of this disclosure. In some embodiments, based on the layout diagram, the manufacturing system 2100 is used to fabricate at least one of the following: (A) one or more semiconductor masks; or (B) at least one component in a layer of a semiconductor integrated circuit.

[0239] exist Figure 21 In this IC manufacturing system 2100, multiple entities, such as design company 2110, masking company 2120, and IC manufacturing company / fabrication company 2130, interact with each other during the design, development, and manufacturing cycle and / or in services related to the manufacture of IC device 2140. The entities in IC manufacturing system 2100 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is multiple different networks, such as an intranet and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design company 2110, masking company 2120, and IC manufacturing company 2130 are owned by a single larger company. In some embodiments, two or more of design company 2110, masking company 2120, and IC manufacturing company 2130 coexist in a common facility and use common resources.

[0240] The design company (or design team) 2110 produces the IC design layout 2111. The IC design layout 2111 includes, for example, Figures 2 to 4 The diagram illustrates various geometric patterns in the IC layout design. These geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers that make up the various components of the IC device 2140 to be fabricated. Various layers are combined to form various IC features. For example, a portion of the IC design layout 2111 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer) and various metal layers deposited on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads. The design company 2110 implements an appropriate design process to form the IC design layout 2111. This design process includes one or more of logic design, physical design, or placement and routing. The IC design layout 2111 is presented in one or more data files containing information about the geometric patterns. For example, the IC design layout 2111 may be expressed in GDSII or DFII file format.

[0241] Masking company 2120 includes data preparation 2121 and mask fabrication 2122. Masking company 2120 uses an IC design layout 2111 to fabricate one or more masks 2123 for use in fabricating various layers of an IC device 2140 according to the IC design layout 2111. Masking company 2120 performs mask data preparation 2121, in which the IC design layout 2111 is converted into a representative data file (RDF). Mask data preparation 2121 provides this RDF to mask fabrication 2122. Mask fabrication 2122 includes a mask writer. The mask writer converts the RDF into an image on a substrate (such as a mask (photomask) 2123 or a semiconductor wafer 2132). The design layout 2111 is manipulated by mask data preparation 2121 to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication company 2130. Figure 21 In this embodiment, mask data preparation 2121 and mask fabrication 2122 are shown as separate elements. In some embodiments, mask data preparation 2121 and mask fabrication 2122 may be collectively referred to as mask data preparation.

[0242] In some embodiments, mask data preparation 2121 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may arise from diffraction, interference, other process effects, and the like. OPC adjustment IC design layout diagram 2111. In some embodiments, mask data preparation 2121 includes other resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution aids, phase-shift masking, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0243] In some embodiments, mask data preparation 2121 includes a mask rule checker (MRC) that checks the IC design layout 2111, which has undergone processing in the OPC, using a set of mask generation rules. These rules contain certain geometric and / or connectivity constraints to ensure sufficient tolerance, account for variations in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 2111 to compensate for constraints during mask fabrication 2122, which may undo some modifications performed by the OPC to satisfy the mask generation rules.

[0244] In some embodiments, mask data preparation 2121 includes lithography process checking (LPC), which simulates the process performed by IC manufacturing company 2130 to fabricate IC device 2140. LPC simulates this process based on IC design layout 2111 to produce a simulated manufactured device, such as IC device 2140. Processing parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and similar or combinations thereof. In some embodiments, after LPC has produced a simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 2111.

[0245] It should be understood that, for clarity, the above description of mask data preparation 2121 has been simplified. In some embodiments, data preparation 2121 includes additional features, such as logic operations (LOPs) for modifying the IC design layout 2111 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 2111 during data preparation 2121 can be performed in various different sequences.

[0246] After mask data preparation 2121 and during mask fabrication 2122, a mask 2123 or a set of masks 2123 is fabricated based on the modified IC design layout 2111. In some embodiments, mask fabrication 2122 includes performing one or more lithography exposures based on the IC design layout 2111. In some embodiments, an electron beam (e-beam) or multiple e-beams mechanism is used to form a pattern on the mask (photomask or photomask) 2123 based on the modified IC design layout 2111. Various techniques can be used to form the mask 2123. In some embodiments, a binary technique is used to form the mask 2123. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose image-sensitive material layers (e.g., photoresist) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 2123 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, a phase-shifting technique is used to form mask 2123. In a phase-shift mask (PSM) version of mask 2123, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shift mask may be a decaying PSM or an alternating PSM. The mask produced by mask fabrication 2122 is used in various processes. For example, the mask(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 2132, in etching processes to form various etched regions in semiconductor wafer 2132, and / or in other suitable processes.

[0247] IC manufacturing company 2130 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing company 2130 is a semiconductor factory. For example, there may be a manufacturing facility for front-end-of-line (FEOL) fabrication of multiple IC products, a second manufacturing facility that provides back-end-of-line (BEOL) fabrication for interconnection and packaging of IC products, and a third manufacturing facility that provides other services for factory operations.

[0248] IC manufacturing company 2130 uses a mask 2123 fabricated by mask company 2120 to fabricate IC device 2140. Therefore, IC manufacturing company 2130 uses IC design layout 2111 at least indirectly to fabricate IC device 2140. In some embodiments, IC manufacturing company 2130 uses mask 2123 to fabricate semiconductor wafer 2132 to form IC device 2140. In some embodiments, IC fabrication includes performing one or more photolithography exposures at least indirectly based on IC design layout 2111. Semiconductor wafer 2132 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 2132 further includes one or more of the following: various doped regions, dielectric features, multilayer interconnects, and the like (formed in subsequent manufacturing steps).

[0249] In summary, the embodiments disclosed herein provide a capacitor system, a semiconductor device, and a method for forming the system and the semiconductor device. The system and semiconductor device can be fabricated with general CMOS and have a high operating voltage (e.g., greater than approximately 2V). The system and semiconductor device have less parasitic inductance and resistance, thus improving performance at high frequencies. By improving performance at high frequencies, voltage ripple is reduced and PCB area is saved. Furthermore, due to better VCC and TCC, the system and semiconductor device offer better power accuracy compared to some other methods.

[0250] In some embodiments, a capacitor device is provided. The capacitor device includes a substrate, a well, and a plurality of trenches. The well is located in the substrate, wherein the well serves as a first electrode of the capacitor device. The trenches are surrounded by the well in a layout view, wherein a first trench among the trenches has two rounded ends along a first direction in the layout view, wherein adjacent trenches are separated from each other by a first distance, and wherein the trenches serve as a second electrode of the capacitor device.

[0251] In some embodiments, the first electrode is a cathode of the capacitor device, and the second electrode is an anode of the capacitor device.

[0252] In some embodiments, the capacitor device further includes a deep well located below the well in the substrate, wherein the trenches are surrounded by the deep well in a layout view.

[0253] In some embodiments, the capacitor device further includes a plurality of isolation structures disposed between a plurality of top surfaces of the trenches along a first direction.

[0254] In some embodiments, the capacitor device further includes a planting region. The planting region surrounds a trench in a substrate, wherein the planting region and the well have the same conductivity type.

[0255] In some embodiments, the capacitor device further includes a plurality of N+ doped regions located on a plurality of top surfaces of the implanted regions, wherein the implanted regions are coupled to a plurality of metal lines of the first electrode through these N+ doped regions.

[0256] In some embodiments, the capacitor device further includes a plurality of high-K liners disposed between the planting area and the trenches, wherein the high-K liners serve as a plurality of dielectric layers between the first electrode and the second electrode of the capacitor device.

[0257] In some embodiments, the first trench extends in a vertical direction in the substrate, and the first trench has a rounded bottom in the vertical direction.

[0258] In some embodiments, one sidewall of the first trench in the substrate is tilted at an angle greater than zero from vertical.

[0259] In some embodiments, the capacitor device further includes a plurality of metal wires coupled to the trenches, wherein the metal wires are coupled together as the second electrode.

[0260] In some embodiments, a semiconductor device is provided, including an integrated circuit and a capacitor. The capacitor is coupled to the integrated circuit, wherein the capacitor and the integrated circuit are located within a wafer. The capacitor includes a well and a plurality of trenches. The well serves as a first electrode of the capacitor. In a layout view, the trenches are arranged in a plurality of rows and surrounded by the well. The trenches of adjacent rows are staggered. The first trench among these trenches has two rounded ends along a first direction in the layout view. These trenches serve as a second electrode of the capacitor.

[0261] In some embodiments, the grooves of the odd-numbered rows are aligned along a second direction perpendicular to the first direction, while the grooves of the even-numbered rows are aligned along the second direction.

[0262] In some embodiments, these grooves are circular in the layout view.

[0263] In some embodiments, in a layout view, each of these trenches is a line segment along the first direction, and each end of the line segment is a curve.

[0264] In some embodiments, the first electrode is a cathode of a capacitor, and the second electrode is an anode of a capacitor.

[0265] In some embodiments, the wells and trenches are n-type semiconductors.

[0266] In some embodiments, the semiconductor device further includes a placement region and a plurality of shallow trench isolation structures. The placement region surrounds the trenches in a well. The shallow trench isolation structures are disposed along a first direction between a plurality of top portions of the placement region and a plurality of top portions of the trenches.

[0267] In some embodiments, the top portions of the implanted regions are doped with a plurality of N+ doped regions, wherein these N+ doped regions are coupled together as a first electrode.

[0268] In some embodiments, a method for forming a capacitor is provided. The method includes forming a hard mask on a substrate, wherein the hard mask has a plurality of circular patterns. The method further includes etching the substrate with the hard mask to form a plurality of trenches. The method further includes performing a gradient planting operation on the trenches. The method further includes forming a plurality of high-k liner on the trenches. The method further includes depositing a doped semiconductor to fill the trenches. The method further includes removing the hard mask to form the capacitor.

[0269] In some embodiments, the etching operation includes performing an anisotropic etching to control a depth of the trenches; and performing an isotropic etching to round the bottoms of the trenches.

[0270] In some embodiments, a capacitor device is provided. The capacitor device includes a substrate, a well, a plurality of trenches, and a deep well. The well is located in the substrate, wherein the well serves as the cathode of the capacitor device. The trenches are surrounded by the well in a layout view, wherein a first trench has two rounded ends along a first direction in the layout view, wherein adjacent trenches are separated from each other by a first distance, and wherein the trenches serve as the anode of the capacitor device. The deep well is located below the well in the substrate, wherein the trenches are surrounded by the deep well in the layout view.

[0271] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the nature of one embodiment of this application. Those skilled in the art should understand that one embodiment of this application can be used as the basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of one embodiment of this application, and that various changes, substitutions, and modifications can be made to one embodiment of this application without departing from the spirit and scope of that application.

Claims

1. A capacitor device, characterized in that, Include: One base; A well is located in the substrate, wherein the well is used as a first electrode of the capacitor device; as well as Multiple trenches, wherein the multiple trenches are surrounded by the well in a layout view, wherein a first trench of the multiple trenches has two rounded ends along a first direction in the layout view, wherein adjacent trenches are separated from each other by a first distance, wherein the multiple trenches are used as a second electrode of the capacitor device.

2. The capacitor device as claimed in claim 1, characterized in that, Also includes: Multiple isolation structures are disposed between multiple top surfaces of the multiple trenches along the first direction.

3. The capacitor device as claimed in claim 1, characterized in that, Also includes: An implantation area surrounding the trench in the substrate, wherein the implantation area and the well have the same electrical conductivity type.

4. The capacitor device as claimed in claim 3, characterized in that, Also includes: Multiple N+ doped regions are located on multiple top surfaces of the implanted region, wherein the implanted region is coupled to multiple metal lines of the first electrode through the multiple N+ doped regions.

5. The capacitor device as claimed in claim 3, characterized in that, Also includes: Multiple high-K value liners are disposed between the planting area and the multiple trenches, wherein the multiple high-K value liners serve as multiple dielectric layers between the first electrode and the second electrode of the capacitor device.

6. The capacitor device as claimed in claim 1, characterized in that, The first groove extends in the substrate in a vertical direction and has a rounded bottom along the vertical direction.

7. The capacitor device as claimed in claim 1, characterized in that, The first groove has one side wall in the substrate tilted at an angle greater than zero from vertical.

8. A semiconductor device, characterized in that, Include: An integrated circuit; and A capacitor is coupled to the integrated circuit, wherein the capacitor and the integrated circuit are located on a single chip. The capacitor includes: A trap is used as a first electrode of the capacitor; as well as Multiple trenches, wherein, in a layout view, the multiple trenches are arranged in multiple rows and surrounded by the well. The grooves of adjacent rows in the plurality of rows are staggered. One of the plurality of trenches, in this layout view, along a first direction, has two rounded ends. The plurality of trenches are used as a second electrode of the capacitor.

9. The semiconductor device as claimed in claim 8, characterized in that, The plurality of grooves in the odd-numbered rows are aligned along a second direction perpendicular to the first direction. The grooves of the even-numbered rows are aligned along the second direction.

10. A capacitor device, characterized in that, Include: One base; A trap, located in the substrate, wherein the trap serves as a cathode of the capacitor device; Multiple trenches, wherein the multiple trenches are surrounded by the well in a layout view, wherein a first trench of the multiple trenches has two rounded ends along a first direction in the layout view, wherein adjacent trenches are separated from each other by a first distance, wherein the multiple trenches are used as an anode of the capacitor device. as well as A deep well is located beneath the well in the substrate, wherein the plurality of trenches are surrounded by the deep well in the layout view.

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