Stacked capacitor and semiconductor device

Abstract

The application provides a stacked capacitor and a semiconductor device. In the stacked capacitor, a capacitor body is located on a base dielectric layer and includes a plurality of layers of stacked conductive layers and spacer dielectric layers; the plurality of layers of conductive layers include odd layers of conductive layers and even layers of conductive layers alternately in sequence; each conductive layer is flat; the material of the odd layers of conductive layers is different from that of the even layers of conductive layers; a top dielectric layer is located on the capacitor body; the capacitor body and the top dielectric layer are provided with a first opening and a second opening penetrating through the capacitor body and the top dielectric layer; each odd layer of conductive layers is provided with a first annular hole surrounding the first opening; each even layer of conductive layers is provided with a second annular hole surrounding the second opening; each first annular hole is filled with a first filling dielectric layer; each second annular hole is filled with a second filling dielectric layer; a first conductive column is located in the first opening and in contact with the side surface of the even layers of conductive layers; and a second conductive column is located in the second opening and in contact with the side surface of each odd layer of conductive layers.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a stacked capacitor and semiconductor device. Background Technology

[0002] Capacitors are common and important passive electronic components in integrated circuits. Metal-insulator-metal (MIM) capacitors are typically formed on metal interconnect structures in the back-end of line (BEOL) process. This increases the distance between the MIM capacitor and the silicon substrate, thereby reducing the parasitic capacitance between the MIM capacitor and the silicon substrate. Furthermore, the performance of MIM capacitors is less affected by frequency and temperature. In addition, MIM capacitors are formed during the metal interconnect process, making the MIM formation process compatible with existing integrated circuit technologies. Therefore, MIM capacitors are gradually becoming the mainstream type of passive capacitor.

[0003] As Moore's Law continues to evolve, the requirements for capacitor density in integrated circuits are becoming increasingly stringent. This is particularly evident in high-performance chips such as CPUs, GPUs, and FPGAs; mobile chips including 5G modems, system-on-a-chip (SoC), power management chips (PMICs), and 2.5D / 3D chiplets, where there is a significant demand for high-density capacitors. Currently, a major mainstream structure for achieving high-density capacitors is stacked capacitors. Improving the performance of stacked capacitors has become a major focus. Utility Model Content

[0004] A first aspect of this application provides a stacked capacitor, the stacked capacitor comprising: Base dielectric layer; A capacitor body is located on the base dielectric layer; the capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between any two adjacent conductive layers; in the direction from the base dielectric layer to the capacitor body, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers; each conductive layer is flat; the material of the odd-numbered conductive layers is different from the material of the even-numbered conductive layers; The top dielectric layer is located on the side of the capacitor body away from the base dielectric layer; the capacitor body and the top dielectric layer are provided with a first opening and a second opening penetrating the capacitor body and the top dielectric layer, each of the odd-numbered conductive layers is provided with a first annular hole surrounding the first opening and communicating with the first opening, and each of the even-numbered conductive layers is provided with a second annular hole surrounding the second opening and communicating with the second opening. A first filling dielectric layer, wherein each of the first annular holes is filled by the first filling dielectric layer; The second filling dielectric layer, each of the second annular holes is filled by the second filling dielectric layer; The first conductive post is located inside the first opening and is in contact with the side surface of the even-numbered conductive layer exposed by the first opening. The second conductive post is located inside the second opening and is in contact with the side surface of each of the odd-numbered conductive layers exposed by the second opening.

[0005] In one embodiment, the width of the first annular hole in the direction parallel to the surface of the base dielectric layer toward the capacitor body is greater than or equal to the thickness of the spacer dielectric layer, and less than or equal to three times the thickness of the odd-numbered conductive layer in which the first annular hole is located.

[0006] In one embodiment, the width of the second annular hole in the direction parallel to the surface of the base dielectric layer toward the capacitor body is greater than or equal to the thickness of the spacer dielectric layer, and less than or equal to three times the thickness of the even-numbered conductive layer in which the second annular hole is located.

[0007] In one embodiment, one of the odd-numbered conductive layers and the even-numbered conductive layers is made of aluminum and the other of tungsten; or, one of the odd-numbered conductive layers and the even-numbered conductive layers is made of copper and the other of tungsten; or, one of the odd-numbered conductive layers and the even-numbered conductive layers is made of chromium and the other of copper; or, one of the odd-numbered conductive layers and the even-numbered conductive layers is made of aluminum and the other of molybdenum.

[0008] In one embodiment, the capacitor body comprises a plurality of spaced sub-capacitor bodies, each of which has at least one first opening and at least one second opening.

[0009] In one embodiment, each of the sub-capacitor bodies is provided with a plurality of first openings and a plurality of second openings.

[0010] In one embodiment, the first opening penetrates a portion of the thickness of the base dielectric layer; the second opening penetrates a portion of the thickness of the base dielectric layer.

[0011] In one embodiment, the thickness of the conductive layer ranges from 10 nm to 100 nm; the thickness of the spacer dielectric layer ranges from 5 nm to 50 nm.

[0012] A second aspect of this application provides a semiconductor device comprising the stacked capacitors described above.

[0013] In one embodiment, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the surface of the chip or inside the chip.

[0014] The main technical effects achieved by the embodiments of this application are: The stacked capacitor provided in this application embodiment has the following advantages: since each conductive layer is flat, there is no height difference between different areas of the same conductive layer, that is, no steps are formed. This avoids the problem of conductive layer breakage caused by height differences between different areas of the conductive layer, thus improving the reliability of the stacked capacitor. Since the conductive layer is flat, the thickness of the spacer dielectric layer between adjacent conductive layers is uniform. This avoids the problem of electric field concentration caused by the thinner spacer dielectric layer at the step when there are steps in the conductive layer, thus effectively improving the breakdown characteristics of the stacked capacitor. Except for the first opening, the second opening, the first annular hole, and the second annular hole, the areas opposite the odd-numbered conductive layers to the even-numbered conductive layers are all effective capacitor areas, which can increase the area of ​​the effective capacitor area and thus help improve the performance of the stacked capacitor. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating a method for fabricating a stacked capacitor according to an exemplary embodiment of this application; Figures 2 to 25 This is a schematic diagram of different process steps in the fabrication method of stacked capacitors provided by an exemplary embodiment of this application. Detailed Implementation

[0016] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0017] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture; if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0018] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0019] Please refer to Figure 1 This application provides a method for preparing a stacked capacitor, the method comprising the following steps: forming a host layer on a base dielectric layer.

[0020] like Figure 1 As shown, the steps for forming the main body layer include the following steps S10 to S40.

[0021] In step S10, a base dielectric layer is provided.

[0022] In step S20, a capacitor body is formed on the base dielectric layer; the capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between any two adjacent conductive layers; in the direction from the base dielectric layer to the capacitor body, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers; each conductive layer is flat; the material of the odd-numbered conductive layers is different from the material of the even-numbered conductive layers.

[0023] In step S30, a top dielectric layer is formed on the side of the capacitor body away from the base dielectric layer.

[0024] In step S40, a first opening is formed penetrating the capacitor body and the top dielectric layer. Each odd-numbered conductive layer is etched through the first opening to form a first annular hole surrounding and communicating with the first opening. A first filling dielectric layer is formed within each of the first annular holes. A first conductive pillar is formed located in the first opening and in contact with the side surface of each even-numbered conductive layer exposed by the first opening. A second opening is formed penetrating the capacitor body and the top dielectric layer. Each even-numbered conductive layer is etched through the second opening to form a second annular hole surrounding and communicating with the second opening. A second filling dielectric layer is formed within each of the second annular holes. A second conductive pillar is formed located in the second opening and in contact with the side surface of each odd-numbered conductive layer exposed by the second opening.

[0025] The method for fabricating stacked capacitors provided in this application has several advantages. Firstly, because each conductive layer is flat, there is no height difference between different regions of the same conductive layer, meaning no steps are formed. This avoids the problem of conductive layer breakage caused by height differences between different regions of the conductive layer, thus improving the reliability of the stacked capacitor. Secondly, because the conductive layers are flat, the thickness of the dielectric layer between adjacent conductive layers is uniform, avoiding the problem of electric field concentration caused by a smaller dielectric layer at the step when steps exist, effectively improving the breakdown characteristics of the stacked capacitor. Thirdly, except for the first opening, the second opening, the first annular hole, and the second annular hole, the areas opposite the odd-numbered conductive layers to the even-numbered conductive layers are all effective capacitor areas, increasing the area of ​​the effective capacitor area and thus helping to improve the performance of the stacked capacitor.

[0026] The following will combine Figures 2 to 25The following provides a detailed description of steps S10 to S40. The accompanying drawings use a configuration of 6 conductive layers as an example. It is understood that the number of conductive layers can be different from 6, for example, 3, 4, 5, 7, or 8 layers.

[0027] In step S10, a base dielectric layer 10 is provided.

[0028] In one embodiment, the base dielectric layer 10 may be made of a low-k dielectric material (a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride. The base dielectric layer 10 provides a platform for the subsequent fabrication of the capacitor body 20. The base dielectric layer 10 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods. In embodiments where the stacked capacitors are formed within the chip or on the chip surface, the base dielectric layer 10 may also be used to isolate the preceding metal interconnect structure in the back-end of line (BEOL) process, i.e., electrically isolate the stacked capacitors from the chip.

[0029] like Figure 2 As shown, in step S20, a capacitor body 20 is formed on the base dielectric layer 10; the capacitor body 20 includes multiple stacked conductive layers 21 and spacer dielectric layers 22 located between any two adjacent conductive layers 21; in the direction from the base dielectric layer 10 to the capacitor body 20, the multiple conductive layers 21 include alternating odd-numbered conductive layers 201 and even-numbered conductive layers 202; each conductive layer 21 is flat; the material of the odd-numbered conductive layers 201 is different from the material of the even-numbered conductive layers 202.

[0030] Combination Figure 2 and Figure 3As shown, the conductive layer 21 of the capacitor body 20 includes a multi-layered stacked first conductive layer 211, a second conductive layer 212, a third conductive layer 213, a fourth conductive layer 214, a fifth conductive layer 215, and a sixth conductive layer 216. The spacer dielectric layer 22 includes a first spacer dielectric layer 221 located between the first conductive layer 211 and the second conductive layer 212, a second spacer dielectric layer 222 located between the second conductive layer 212 and the third conductive layer 213, a third spacer dielectric layer 223 located between the third conductive layer 213 and the fourth conductive layer 214, a fourth spacer dielectric layer 224 located between the fourth conductive layer 214 and the fifth conductive layer 215, and a fifth spacer dielectric layer 225 located between the fifth conductive layer 215 and the sixth conductive layer 216. The first conductive layer 211, the third conductive layer 213 and the fifth conductive layer 215 are all odd-numbered conductive layers 201, while the second conductive layer 212, the fourth conductive layer 214 and the sixth conductive layer 216 are all even-numbered conductive layers 202.

[0031] In one embodiment, each conductive layer 21 can be formed by depositing a conductive material layer, such as through chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The material of each conductive layer 21 can be a metallic material, such as aluminum. Of course, in other embodiments, the material of the conductive layer can also be, but is not limited to, etchable metals such as titanium nitride, titanium, aluminum, chromium, nickel, tungsten, ruthenium, citriium, molybdenum, and hafnium. The thickness of each conductive layer 21 can range from 10 nm to 100 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, and 100 nm. The thickness of each conductive layer 21 can be the same or different. The orthogonal projection of each conductive layer 21 onto the base dielectric layer 10 covers the base dielectric layer 10.

[0032] In one embodiment, each spacer dielectric layer 22 can be formed by depositing a dielectric material, such as through chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The thickness of the spacer dielectric layers 22 is uniform in all regions. The material of each spacer dielectric layer 22 can be any one or a mixture of materials including, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN. The thickness of each spacer dielectric layer 22 can range from 5nm to 50nm, such as 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, and 50nm. The thickness of each spacer dielectric layer 22 can be the same or different. The material of each spacer dielectric layer 22 can be the same or different. The orthographic projection of each spacer dielectric layer 22 onto the base dielectric layer 10 covers the base dielectric layer 10.

[0033] like Figure 3 and Figure 4 As shown, in step S30, a top dielectric layer 30 is formed on the side of the capacitor body 20 away from the base dielectric layer 10.

[0034] The top dielectric layer 30 is made of a low-k dielectric material (a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, or silicon oxynitride. The top dielectric layer 30 is relatively thick, at least greater than the thickness of the spacer dielectric layer 22. The thickness of the top dielectric layer 30 may be greater than the thickness of the conductive layer 21.

[0035] like Figures 5 to 24 As shown, in step S40, a first opening 301 is formed penetrating the capacitor body 20 and the top dielectric layer 30. Each odd-numbered conductive layer 201 is etched through the first opening 301, forming a first annular hole 2011 surrounding and communicating with the first opening 301. A first filling dielectric layer 41 is formed filling each of the first annular holes 2011. A first filling dielectric layer 41 is formed located in the first opening 301 and contacts the side surface of each even-numbered conductive layer 202 exposed by the first opening 301. Conductive post 51; forming a second opening 302 through the capacitor body 20 and the top dielectric layer 30, etching each even-numbered conductive layer 202 through the second opening 302, so that each even-numbered conductive layer 202 forms a second annular hole 2021 surrounding and communicating with the second opening 302, forming a second filling dielectric layer 42 filling each second annular hole 2021, and forming a second conductive post 52 located in the second opening 302 and in contact with the side surface of each odd-numbered conductive layer 201 exposed by the second opening 302.

[0036] In one embodiment, the first opening 301, the first annular opening 2011, the first filling dielectric layer 41, and the first conductive pillar 51 can be formed first, followed by the formation of the second opening 302, the second annular opening 2021, the second filling dielectric layer 42, and the second conductive pillar 52. Alternatively, the second opening 302, the second annular opening 2021, the second filling dielectric layer 42, and the second conductive pillar 52 can be formed first, followed by the formation of the first opening 301, the first annular opening 2011, the first filling dielectric layer 41, and the first conductive pillar 51. The following description, with reference to the accompanying drawings, uses the example of forming the first opening 301, the first annular opening 2011, the first filling dielectric layer 41, and the first conductive pillar 51 first.

[0037] like Figure 5 and Figure 6As shown, multiple first openings 301 are formed, each first opening 301 penetrating the capacitor body 20 and the top dielectric layer 30. The multiple first openings 301 can be divided into multiple groups, with the multiple first openings 301 in each group arranged adjacent to each other. The width of the first opening 301 is approximately several hundred nanometers. Only one group of first openings is shown in the figure.

[0038] In one embodiment, a dry etching method can be used to etch the capacitor body 20 and the top dielectric layer 30. Dry etching can be, for example, chemical physical etching or physical etching. When using a chemical physical etching method, chlorine (Cl) gas can be used for etching, for example.

[0039] In one embodiment, such as Figure 6 As shown, when the first opening 301 is formed, a portion of the thickness of the base dielectric layer 10 is etched away. This ensures that the capacitor body 20 is etched through.

[0040] like Figure 7 and Figure 8 As shown, each odd-numbered conductive layer 201 is etched through each of the first openings 301, so that each odd-numbered conductive layer 201 forms a first annular opening 2011 surrounding the first opening 301.

[0041] The first annular opening 2011 and the second annular opening 2021 can be formed using either a wet etching process or a dry etching process. When using a wet etching process, two different etching solutions are used: one etching solution etches only the odd-numbered conductive layers 201, and the other etching solution etches only the even-numbered conductive layers 202. When using a dry etching process, two different etching gases are used: one etching gas etches only the odd-numbered conductive layers 201, and the other etching gas etches only the even-numbered conductive layers 202.

[0042] In one embodiment, the width of the first annular hole 2011 in the direction parallel to the surface of the base dielectric layer 10 toward the capacitor body 20 is greater than or equal to the thickness of the spacer dielectric layer 22, and less than or equal to three times the thickness of the odd-numbered conductive layer 201 where the first annular hole 2011 is located. This configuration avoids the possibility of the first annular hole 2011 being too narrow, leading to potential breakdown; it also avoids the situation where the first annular hole 2011 is too wide, making it impossible to fill during the subsequent formation of the first filling dielectric layer 41. Preferably, the width of the first annular hole 2011 in the direction parallel to the surface of the base dielectric layer 10 toward the capacitor body 20 is twice the thickness of the odd-numbered conductive layer 201 where the first annular hole 2011 is located. The width of the first annular hole 2011 can be substantially the same at all points.

[0043] like Figure 9and Figure 10 As shown, a first filling dielectric layer 41 is formed. The first filling dielectric layer 41 partially fills each of the first annular holes 2011 and partially covers the side of the first opening 301, covering the side of each even-numbered conductive layer 202 and the spacer dielectric layer 22 exposed by the first opening 301. The first filling dielectric layer 41 also covers the surface of the top dielectric layer 30 away from the base dielectric layer 10.

[0044] The material of the first filled dielectric layer 41 can be any one or a mixture of materials selected from, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN. The first filled dielectric layer 41 can be formed using an ALD process.

[0045] like Figure 11 As shown, the portion of the first filling dielectric layer 41 covering the side surface of the first opening 301 is removed, exposing each of the even-numbered dielectric layers 202 surrounding the side surface of the first opening 301, while also exposing each of the spacer dielectric layers 22 surrounding the side surface of the first opening 301. The portion of the first filling dielectric layer 41 located on the side of the capacitor body 20 away from the base dielectric layer 10 is simultaneously removed.

[0046] In this step, a dry etching process can be used, selecting an etching process capable of etching away the portion of the first filling dielectric layer 41 covering the side of the first opening 301. For example, atomic layer etching (ALE) can be selected, thus ensuring the uniformity of etching.

[0047] like Figure 12 As shown, a first seed layer 511 is formed, which covers the bottom surface, side surface, and the surface of the top dielectric layer 30 away from the base dielectric layer 10 of each first opening 301. The first seed layer 511 is a continuous film layer.

[0048] In this step, the first seed layer 511 can be formed using the ALD process. The first seed layer 511 serves as both an adhesion layer and a barrier layer. The material of the first seed layer 511 can be a material with good adhesion, such as Ti, TiN, Ta, or TaN.

[0049] like Figure 13 and Figure 14 As shown, a first conductive portion 512 is formed by electroplating metal material in each first opening 301 using an electroplating process. Then, chemical mechanical polishing (CMP) is performed to remove the portion of the first seed layer 511 and the first conductive portion 512 that extends beyond the top dielectric layer 30, resulting in a first conductive pillar 51 including the first seed layer 511 and the first conductive portion 512.

[0050] like Figure 15 and Figure 16 As shown, multiple second openings 302 are formed, each second opening 302 penetrating the capacitor body 20 and the top dielectric layer 30. The multiple second openings 302 can be divided into multiple groups, and multiple first openings 301 in each group are arranged adjacent to each other.

[0051] The width of the second opening 302 is approximately several hundred nanometers.

[0052] In one embodiment, a dry etching method can be used to etch the capacitor body 20 and the top dielectric layer 30. Dry etching can be, for example, chemical physical etching or physical etching. When using a chemical physical etching method, chlorine gas can be used, for example.

[0053] In one embodiment, such as Figure 16 As shown, when forming the second opening 302, a portion of the thickness of the base dielectric layer 10 is etched away. This ensures that the capacitor body 20 is etched through.

[0054] like Figure 17 and Figure 18 As shown, each even-numbered conductive layer 202 is etched through each of the second openings 302, so that each even-numbered conductive layer 202 forms a second annular opening 2021 surrounding the second opening 302.

[0055] In one embodiment, one of the odd-numbered conductive layer 201 and the even-numbered conductive layer 202 is made of aluminum, and the other is made of tungsten. When forming the first annular opening 2011 and the second annular opening 2021, the etching solution used for the aluminum conductive layer is a dilute sulfuric acid solution or a sodium hydroxide solution, and the etching solution used for the tungsten conductive layer is a hydrogen peroxide-based tungsten etching solution. The hydrogen peroxide-based tungsten etching solution may contain hydrogen peroxide, inorganic acids, organic bases, metal ion masking agents, etc.

[0056] Alternatively, one of the odd-numbered conductive layers 201 and the even-numbered conductive layers 202 may be made of copper, and the other may be made of tungsten. When forming the first annular opening 2011 and the second annular opening 2021, the etching solution used for the copper conductive layer is an acidic copper chloride etching solution, and the etching solution used for the tungsten conductive layer is a tungsten etching solution including potassium hydroxide and potassium ferric chloride.

[0057] Alternatively, one of the odd-numbered conductive layers 201 and the even-numbered conductive layers 202 may be made of chromium, and the other of copper; when forming the first annular opening 2011 and the second annular opening 2021, a chromium etching solution may be used for the conductive layer made of chromium, and a copper etching solution may be used for the conductive layer made of copper. A copper protectant may be added to the chromium etching solution.

[0058] Alternatively, one of the odd-numbered conductive layers 201 and the even-numbered conductive layers 202 may be made of aluminum, and the other may be made of molybdenum; when forming the first annular opening 2011 and the second annular opening 2021, a bromine gas may be used for the conductive layer made of aluminum, and a fluorine gas may be used for the conductive layer made of copper.

[0059] In one embodiment, the width of the second annular opening 2021 in the direction parallel to the surface of the base dielectric layer 10 toward the capacitor body 20 is greater than or equal to the thickness of the spacer dielectric layer 22, and less than or equal to three times the thickness of the even-numbered conductive layer 202 where the second annular opening 2021 is located. This configuration avoids the possibility of the second annular opening 2021 being too narrow, leading to potential breakdown; it also avoids the situation where the second annular opening 2021 is too wide, making it impossible to fill completely when forming the second filling dielectric layer 42. Preferably, the width of the second annular opening 2021 in the direction parallel to the surface of the base dielectric layer 10 toward the capacitor body 20 is twice the thickness of the even-numbered conductive layer 202 where the second annular opening 2021 is located. The width of the second annular opening 2021 can be substantially the same at all points.

[0060] like Figure 19 and Figure 20 As shown, a second filling dielectric layer 42 is formed, which partially fills each of the second annular holes 2021 and partially covers the side of the second opening 302, covering the even-numbered conductive layers 202 and the spacer dielectric layers 22 exposed on the side of the second opening 302. The second filling dielectric layer 42 also covers the surface of the top dielectric layer 30 away from the base dielectric layer 10.

[0061] The material of the second filled dielectric layer 42 can be any one or a mixture of materials selected from, but not limited to, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN. The second filled dielectric layer 42 can be formed using an ALD process.

[0062] like Figure 21 As shown, the portion of the second filling dielectric layer 42 covering the side surface of the second opening 302 is removed, exposing each of the even-numbered dielectric layers 202 surrounding the side surface of the second opening 302, while also exposing each of the spacer dielectric layers 22 surrounding the side surface of the second opening 302. The portion of the second filling dielectric layer 42 located on the side of the capacitor body 20 away from the base dielectric layer 10 is simultaneously removed.

[0063] In this step, dry etching can be used, selecting an etching process capable of etching away the portion of the second filling dielectric layer 42 covering the side of the second opening 302. For example, atomic layer etching (ALE) can be selected, thus ensuring the uniformity of etching.

[0064] like Figure 22 As shown, a second seed layer 521 is formed, which covers the bottom surface, side surface, and the surface of the top dielectric layer 30 away from the base dielectric layer 10 of each second opening 302. The second seed layer 521 is a continuous film layer.

[0065] In this step, an ALD process can be used to form a second seed layer 521. The second seed layer 521 serves as both an adhesion layer and a barrier layer. The material of the second seed layer 521 can be a material with good adhesion, such as Ti, TiN, Ta, or TaN.

[0066] like Figure 23 and Figure 24 As shown, a second conductive portion 522 is formed by electroplating metal material into each second opening 302 using an electroplating process. Then, chemical mechanical polishing (CMP) is performed to remove the portion of the second seed layer 521 and the second conductive portion 522 that extends beyond the top dielectric layer 30, resulting in a second conductive pillar 52 including the second seed layer 521 and the second conductive portion 522. The material of the second conductive portion 522 can be Cu, W, etc.

[0067] In other embodiments, in step S40, a first opening 301 and a first annular hole 2011 are first formed; then photoresist is used to protect the first opening 301 and the first annular hole 2011; then a second opening 302 and a second annular hole 2021 are formed; then the photoresist is removed; then a first filling dielectric layer 41 and a second filling dielectric layer 42 are formed simultaneously; then a first conductive pillar 51 and a second conductive pillar 52 are formed simultaneously.

[0068] Alternatively, in step S40, the first opening 301, the first annular hole 2011, and the first filling dielectric layer 41 are first formed; then photoresist is used to protect the first opening 301 and the first filling dielectric layer 41; then the second opening 302, the second annular hole 2021, and the second filling dielectric layer 42 are formed; then the photoresist is removed; then the first conductive pillar 51 and the second conductive pillar 52 are formed simultaneously.

[0069] Alternatively, in step S40, the second opening 302 and the second annular hole 2021 are first formed; then photoresist is used to protect the second opening 302 and the second annular hole 2021; then the first opening 301 and the first annular hole 2011 are formed; then the photoresist is removed; then the first filling dielectric layer 41 and the second filling dielectric layer 42 are formed simultaneously; then the first conductive pillar 51 and the second conductive pillar 52 are formed simultaneously.

[0070] Alternatively, in step S40, the second opening 302, the second annular hole 2021, and the second filling dielectric layer 42 are first formed; then photoresist is used to protect the second opening 302 and the second filling dielectric layer 42; then the first opening 301, the first annular hole 2011, and the first filling dielectric layer 41 are formed; then the photoresist is removed; then the first conductive pillar 51 and the second conductive pillar 52 are formed simultaneously.

[0071] like Figure 25 As shown, the capacitor body 20 has a plurality of first openings 301 and a plurality of second openings 302. After the step of forming the first conductive pillars 51 and the second conductive pillars 52, the preparation method further includes the following step: performing patterning processing on the capacitor body 20 to obtain a plurality of spaced sub-capacitor bodies 210, each of the sub-capacitor bodies 210 having a plurality of first openings 301 and a plurality of second openings 302. Each sub-capacitor body 210 is a capacitor. By setting each sub-capacitor body 210 to have a plurality of first openings 301 and a plurality of second openings 302, the total contact area between the first conductive pillars 51 and the even-numbered conductive layers 201 can be increased, the total contact area between the second conductive pillars 52 and the odd-numbered conductive layers 202 can be increased, and the contact resistance can be reduced.

[0072] In one embodiment, a dry etching method can be used to etch the capacitor body 20 and the top dielectric layer 30 to achieve patterning of the capacitor body 20. Dry etching can be, for example, chemical physical etching or physical etching. When using a chemical physical etching method, chlorine-based gases can be used, for example.

[0073] It should be noted that, Figures 2 to 25 This is a partial schematic diagram of the corresponding structure.

[0074] The method for fabricating stacked capacitors provided in this application requires only three photolithography processes, regardless of the number of conductive layers: a photolithography process for forming the first aperture 301, a photolithography process for forming the second aperture 302, and a photolithography process for patterning the capacitor body 20. When the number of conductive layers is large, this method reduces process costs and improves fabrication efficiency compared to performing a photolithography process for each conductive layer.

[0075] This application also provides a stacked capacitor in its embodiments. For example... Figure 24 and Figure 25 As shown, the stacked capacitor includes a base dielectric layer 10, a capacitor body 20, a top dielectric layer 30, a first fill dielectric layer 41, a second fill dielectric layer 42, a first conductive pillar 51, and a second conductive pillar 52.

[0076] The capacitor body 20 is located on the base dielectric layer 10; the capacitor body 20 includes multiple stacked conductive layers 21 and spacer dielectric layers 22 located between any two adjacent conductive layers 21; in the direction from the base dielectric layer 10 to the capacitor body 20, the multiple conductive layers 21 include alternating odd-numbered conductive layers 201 and even-numbered conductive layers 202; each conductive layer 21 is flat; the material of the odd-numbered conductive layers 201 is different from the material of the even-numbered conductive layers 202. The top dielectric layer 30 is located on the side of the capacitor body 20 away from the base dielectric layer 10. The capacitor body 20 and the top dielectric layer 30 are provided with a first opening 301 and a second opening 302 penetrating the capacitor body 20 and the top dielectric layer 30. Each odd-numbered conductive layer 201 is provided with a first annular hole 2011 surrounding and communicating with the first opening 301. Each even-numbered conductive layer 202 is provided with a second annular hole 2021 surrounding and communicating with the second opening 302. Each first annular hole 2011 is filled by the first filling dielectric layer 41. Each second annular hole 2021 is filled by the second filling dielectric layer 42. The first conductive post 51 is located within the first opening 301 and contacts the side surface of the even-numbered conductive layer 202 exposed by the first opening 301. The second conductive post 52 is located within the second opening 302 and is in contact with the side surface of each of the odd-numbered conductive layers 201 exposed by the second opening 302.

[0077] In one embodiment, the width of the first annular hole 2011 in the direction parallel to the surface of the base dielectric layer 10 toward the capacitor body 20 is greater than or equal to the thickness of the spacer dielectric layer 22, and less than or equal to three times the thickness of the odd-numbered conductive layer 201 in which the first annular hole 2011 is located.

[0078] In one embodiment, the width of the second annular hole 2021 in the direction parallel to the surface of the base dielectric layer 10 toward the capacitor body 20 is greater than or equal to the thickness of the spacer dielectric layer 22, and less than or equal to three times the thickness of the even-numbered conductive layer 202 in which the second annular hole 2021 is located.

[0079] In one embodiment, one of the odd-numbered conductive layer 201 and the even-numbered conductive layer 202 is made of aluminum and the other is made of tungsten; or, one of the odd-numbered conductive layer and the even-numbered conductive layer is made of copper and the other is made of tungsten; or, one of the odd-numbered conductive layer 201 and the even-numbered conductive layer 202 is made of chromium and the other is made of copper; or, one of the odd-numbered conductive layer 201 and the even-numbered conductive layer 202 is made of aluminum and the other is made of molybdenum.

[0080] In one embodiment, the capacitor body 20 has a plurality of spaced sub-capacitor bodies 210, each of the sub-capacitor bodies 210 having a set of first openings 301 and a set of second openings 302. The set of first openings 301 includes at least one first opening 301, and the set of second openings 302 includes at least one second opening 302.

[0081] Furthermore, each of the sub-capacitor bodies 210 is provided with a plurality of first openings 301 and a plurality of second openings 302.

[0082] The embodiments of stacked capacitors provided in this application and the embodiments of the method for preparing stacked capacitors belong to the same inventive concept. The relevant details and beneficial effects can be referred to each other and will not be repeated here.

[0083] This application also provides a semiconductor device. The semiconductor device includes stacked capacitors as described above.

[0084] In some embodiments, the semiconductor device further includes a chip, and the stacked capacitors are disposed outside the surface of the chip or inside the chip.

[0085] The chips mentioned include, but are not limited to, high-performance chips such as CPU chips, GPU chips, FPGA chips, 5G modem chips, system-on-a-chip (SoC), power management chips (PMIC), and 2.5D / 3D chiplets.

[0086] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A stacked capacitor, characterized in that, The stacked capacitors include: Base dielectric layer; A capacitor body is located on the base dielectric layer; the capacitor body includes multiple stacked conductive layers and spacer dielectric layers located between any two adjacent conductive layers; in the direction from the base dielectric layer to the capacitor body, the multiple conductive layers include alternating odd-numbered conductive layers and even-numbered conductive layers; each conductive layer is flat; the material of the odd-numbered conductive layers is different from the material of the even-numbered conductive layers; The top dielectric layer is located on the side of the capacitor body away from the base dielectric layer; the capacitor body and the top dielectric layer are provided with a first opening and a second opening penetrating the capacitor body and the top dielectric layer, each of the odd-numbered conductive layers is provided with a first annular hole surrounding the first opening and communicating with the first opening, and each of the even-numbered conductive layers is provided with a second annular hole surrounding the second opening and communicating with the second opening. A first filling dielectric layer, wherein each of the first annular holes is filled by the first filling dielectric layer; The second filling dielectric layer, each of the second annular holes is filled by the second filling dielectric layer; The first conductive post is located inside the first opening and is in contact with the side surface of the even-numbered conductive layer exposed by the first opening. The second conductive post is located inside the second opening and is in contact with the side surface of each of the odd-numbered conductive layers exposed by the second opening.

2. The stacked capacitor as described in claim 1, characterized in that, The width of the first annular hole in the direction parallel to the surface of the base dielectric layer toward the capacitor body is greater than or equal to the thickness of the spacer dielectric layer, and less than or equal to three times the thickness of the odd-numbered conductive layer in which the first annular hole is located.

3. The stacked capacitor as described in claim 1, characterized in that, The width of the second annular hole in the direction parallel to the surface of the base dielectric layer toward the capacitor body is greater than or equal to the thickness of the spacer dielectric layer, and less than or equal to three times the thickness of the even-numbered conductive layer in which the second annular hole is located.

4. The stacked capacitor as described in claim 1, characterized in that, The odd-numbered conductive layer and the even-numbered conductive layer are made of aluminum and tungsten, respectively; or, one of the odd-numbered conductive layers and the even-numbered conductive layer are made of copper and the other of tungsten, respectively; or, one of the odd-numbered conductive layers and the even-numbered conductive layer are made of chromium and the other of copper, respectively; or, one of the odd-numbered conductive layers and the even-numbered conductive layer are made of aluminum and the other of molybdenum, respectively.

5. The stacked capacitor as described in claim 1, characterized in that, The capacitor body has multiple spaced sub-capacitor bodies, and each sub-capacitor body has at least one first opening and at least one second opening.

6. The stacked capacitor as described in claim 5, characterized in that, Each of the sub-capacitor bodies is provided with a plurality of first openings and a plurality of second openings.

7. The stacked capacitor as described in claim 1, characterized in that, The first opening penetrates a base dielectric layer of a thickness of a portion; the second opening penetrates a base dielectric layer of a thickness of a portion.

8. The stacked capacitor as described in claim 1, characterized in that, The thickness of the conductive layer ranges from 10 nm to 100 nm; the thickness of the spacer dielectric layer ranges from 5 nm to 50 nm.

9. A semiconductor device, characterized in that, The semiconductor device includes the stacked capacitor as described in any one of claims 1 to 8.

10. The semiconductor device as claimed in claim 9, characterized in that, The semiconductor device further includes a chip, and the stacked capacitor is disposed outside the surface of the chip or inside the chip.

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