5kv high-reliability trench gate silicon carbide vdmos

Abstract

The utility model provides a kind of 5KV high-reliability trench gate silicon carbide VDMOS, comprising: buffer layer is connected to silicon carbide substrate;Drift layer is connected to buffer layer, and protruding part is equipped on drift layer;P type area is connected to buffer layer and drift layer;P+ area is connected to P type area;P type well area is connected to drift layer and protruding part;N type area is connected to P+ area and P type well area;Shielding layer is connected to N type area;N type source area connects P type well area, shielding layer and P+ area;Insulating medium layer is connected shielding layer, N type area, P type well area and protruding part respectively;Insulating medium layer is equipped with groove;Gate metal layer is located in groove;Source metal layer is connected P+ area and N type source area respectively;Drain metal layer is connected to the lower side of silicon carbide substrate, by constructing L type gate control structure, the multilayer P type protection structure of drain to source is formed, the protection of source and gate is realized, and double conduction channel guarantees the low resistance characteristic of device.

Description

Technical Field

[0001] This utility model relates to a 5KV high-reliability trench gate silicon carbide VDMOS. Background Technology

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally have higher voltage withstand capability compared to Si VDMOS devices. However, as the voltage withstand requirements for VDMOS devices become increasingly stringent, the reliability of the devices under high voltage and high current conditions has become a key factor restricting their application. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a 5KV high-reliability trench gate silicon carbide VDMOS. By constructing an L-type gate control structure, a multi-layer P-type protection structure from drain to source is formed, which realizes the protection of the source and gate. The dual conductive channels ensure the low resistance characteristics of the device.

[0004] This utility model provides a 5KV high-reliability trench-gate silicon carbide VDMOS, characterized in that it includes: silicon carbide substrate, A buffer layer, wherein the lower side of the buffer layer is connected to the upper side of the silicon carbide substrate; A drift layer, the lower side of which is connected to the upper side of a buffer layer, and the drift layer is provided with protrusions; The P-shaped region has its lower side connected to the upper side of the buffer layer and its inner side connected to the outer side of the drift layer. The lower side of the P+ region is connected to the upper side of the P-shaped region; The lower side of the P-type well region is connected to the upper side of the drift layer, and the inner side of the P-type well region is connected to the outer side of the protrusion. The N-type region has its outer side connected to the P+ region and its lower side connected to the P-type well region. Shielding layer, the shielding layer being connected to the N-type region; The N-type source region has a lower side connected to a P-type well region and a shielding layer, and an outer side connected to a P+ region. An insulating dielectric layer, the lower side of which is connected to a shielding layer, an N-type region, a P-type well region, and the upper side of a protrusion; the insulating dielectric layer has grooves inside; A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the P+ region and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

[0005] The advantages of this utility model are: I. This utility model constructs an L-shaped gate control structure, forming two conductive channels from the source metal layer to the JFET region: source metal layer-N-type source region-gate control region-N-type region-P-type well region and source metal layer-N-type region-P-type well region. The shielding layer between the two conductive channels can protect the gate corner of the device when the device is reverse withstand voltage, thereby improving the gate reliability of the device. II. The drain-to-source structure of this utility model includes: (1) silicon carbide substrate-buffer layer-drift layer-P-type well region-N-type region-N-type source region-source metal layer; (2) silicon carbide substrate-buffer layer-drift layer-P-type well region-N-type region-shielding layer-N-type source region-source metal layer; (3) P-type region-P+ region-source metal layer; wherein, the P-type doped structure of (2) and (3) can effectively ensure the reverse breakdown voltage capability of the device, and the close proximity of the P+ region and the N-type region can ensure the reverse breakdown voltage capability of (1), thereby improving the reliability of the device; Third, the cell boundaries of the device of this utility model are P-type regions and P+ regions, which can ensure the shielding between device cells, thereby achieving decoupling between cells and avoiding the influence of the degradation of the characteristics of a single cell on the other cells due to the parallel connection of cells. Attached Figure Description

[0006] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0007] Figure 1 This is a schematic diagram of a 5KV high-reliability trench gate silicon carbide VDMOS according to this utility model.

[0008] Figure 2 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 1 .

[0009] Figure 3 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 2 .

[0010] Figure 4 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 3 .

[0011] Figure 5 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 4 .

[0012] Figure 6 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 5 .

[0013] Figure 7 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 6 .

[0014] Figure 8 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 7 .

[0015] Figure 9 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 8 .

[0016] Figure 10 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 9 .

[0017] Figure 11 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 .

[0018] Figure 12 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 one.

[0019] Figure 13 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 two.

[0020] Figure 14 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 three.

[0021] Figure 15 This is a cross-sectional view of the process of a 5KV high-reliability trench-gate silicon carbide VDMOS according to this utility model. Figure 10 Four. Detailed Implementation

[0022] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0024] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0025] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0026] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0027] like Figure 1 As shown, this application embodiment provides a 5KV high-reliability trench-gate silicon carbide VDMOS, comprising: Silicon carbide substrate 101, A buffer layer 102, the lower side of which is connected to the upper side of the silicon carbide substrate 101; A drift layer 103, the lower side of which is connected to the upper side of the buffer layer 102, and a protrusion 1031 is provided on the drift layer 103; P-type region 104, the lower side of the P-type region 104 is connected to the upper side of the buffer layer 102, and the inner side of the P-type region 104 is connected to the outer side of the drift layer 103; P+ region 105, the lower side of which is connected to the upper side of P-type region 104; P-type well region 106, the lower side of the P-type well region 106 is connected to the upper side of the drift layer 103, and the inner side of the P-type well region 106 is connected to the outer side of the protrusion 1031. N-type region 107, the outer side of N-type region 107 is connected to P+ region 105, and the lower side of N-type region 107 is connected to P-type well region 106; Shielding layer 108, the shielding layer 108 being connected to the N-type region 107; N-type source region 109, the lower side of which is connected to P-type well region 106 and shielding layer 108, and the outer side of which is connected to P+ region 105; An insulating dielectric layer 110 is provided, the lower side of which is connected to a shielding layer 108, an N-type region 107, a P-type well region 106, and the upper side of a protrusion 1031; a groove 1101 is provided in the insulating dielectric layer 110. A gate metal layer 111 is disposed within the trench 1101; Source metal layer 112, which is connected to the P+ region 105 and the N-type source region 109 respectively; And a drain metal layer 113, which is connected to the lower side of the silicon carbide substrate 101.

[0028] In this embodiment, preferably, the silicon carbide substrate 101, buffer layer 102, and drift layer 103 are all N-type, and the shielding layer 108 is P-type.

[0029] In this embodiment, preferably, the width of the P-type well region 106 is greater than the width of the N-type region 107.

[0030] In this embodiment, preferably, the width of the N-type region 107 is greater than the width of the shielding layer 108.

[0031] In this embodiment, preferably, the doping concentration of the buffer layer 102 is greater than the doping concentration of the drift layer 103, and the doping concentration of the buffer layer 102 is less than the doping concentration of the silicon carbide substrate 101.

[0032] In this embodiment, preferably, the doping concentration of the P-type region 104 is greater than the doping concentration of the drift layer 103, and the doping concentration of the P+ region 105 is greater than the doping concentration of the P-type region 104.

[0033] In this embodiment, preferably, the doping concentration of the shielding layer 108 is greater than the doping concentration of the N-type region 107, and the doping concentration of the N-type region 107 is greater than the doping concentration of the P-type well region 106.

[0034] In this embodiment, preferably, the doping concentration of the N-type source region 109 is greater than the doping concentration of the masking layer 108.

[0035] like Figures 1 to 15 As shown, the above-mentioned method for fabricating VDMOS includes the following steps: Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 113; epitaxially grow buffer layer 102 on the upper side of silicon carbide substrate 101. Step 2: Epitaxial growth is performed on the buffer layer 102 to form the drift layer 103; Step 3: Form a barrier layer 114 above the drift layer 103, etch the barrier layer 114 to form a via, and implant ions to form a P-type region 104; Step 4: Remove the blocking layer 114 from step 3, and epitaxially grow on the drift layer 103 to form an epitaxial layer 115; Step 5: Form a barrier layer 114 above the epitaxial layer 115, etch the barrier layer 114 to form a via, and implant ions to form a P+ region 105. Step 6: Ion implantation to form a P-type well region 106; Step 7: Ion implantation to form N-type region 107; Step 8: Ion implantation to form a P-type shielding layer 108; Step 9: Ion implantation to form an N-type source region 109; Step 10: Etch epitaxial layer 115, masking layer 108 and N-type region 107 to form groove 116 and protrusion 1031, and then oxidize to form insulating dielectric layer 110, wherein the insulating dielectric layer 110 is provided with trench 1101. Step 11: Deposit metal to form gate metal layer 111; Step 12: Etch the N-type source region 109 and the P+ region 105, then deposit metal to form the source metal layer 112, remove the barrier layer 114, and complete the fabrication. Before steps 6 to 12, the barrier layer 114 from the previous step must be removed, the barrier layer 114 must be reformed, and the barrier layer 114 must be etched to form a through hole.

[0036] In another embodiment of this invention, the doping concentration of the silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of the N-type buffer layer 102 is 6-10e17cm. -3 The doping concentration of the N-type drift layer 103 is 1-5e17cm. -3 The doping concentration of the P-type region 104 is 6-10e17cm. -3 The doping concentration of P+ region 105 is 1-5e18cm. -3 The doping concentration of the P-type well region 106 is 1-5e16cm. -3 The doping concentration of the N-type region 107 is 6-8e16cm. -3 The doping concentration of the P-type shielding layer 108 is 6-8e17cm. -3 The doping concentration of the N-type source region 109 is 2-8e18cm. -3 The insulating dielectric layer can be made of silicon dioxide. The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 113, reducing the overall on-resistance of the device. The buffer layer 102 is to form a buffer structure with a gradually changing doping concentration between the N-type silicon carbide substrate 101 and the N-type drift layer 103, thereby improving the quality at the device interface and suppressing reliability issues caused by interface defects during high-voltage applications. The doping concentration of the N-type drift layer 103 and the P-type region 104 represents a trade-off between the reverse breakdown voltage and on-resistance of the device. Their concentration relationship ensures the lateral and longitudinal diffusion relationship of the space charge region of the pn junction, realizing the superjunction structure of the device. The doping concentration of the P+ region 105 is to ensure low-resistance contact with the source metal layer 112, thereby reducing the parasitic diode conduction loss of the device, and to form a wrapping around the source metal layer 112, thereby improving the protection against drain voltage overshoot and improving device reliability. The doping concentration of the P-type well region 106 takes into account the gate control capability and drive loss of the device after considering the gate protection effect of the internal P-type shielding layer 108. Reducing the doping concentration can reduce drive loss, while increasing the concentration can increase gate control capability and reduce off-state leakage current. The doping concentration design of the P-type shielding layer 108 serves two purposes: first, to protect the reliability of the gate and source structures of the device; and second, to form a conductive channel for the device under gate control conditions, thereby enhancing the device's gate control capability. The N-type region 107 is used to increase the conductivity of the device from the N-type source region 109 to the P-type well region 106 and reduce the on-resistance of the device. The thickness of the N-type silicon carbide substrate 101 is 1 μm, which is to ensure support during the device fabrication process. The thickness of the N-type buffer layer 102 is 500 nm, and the thickness of the N-type drift layer 103 is 50~60 μm. This is a trade-off between the device and the doping concentration on the on-resistance and epitaxial thickness. The P-type region 104 has a width of 2 μm and a thickness of 45-55 μm. This is to form the superjunction structure of the device and ensure the isolation between cells. The P+ region 105 is distributed on the outer side of the device gate structure, on the outermost side of the device cell structure. Its maximum width is 2μm and its thickness is 5μm. Its bottom is in direct contact with the P-type region 104, and together with the P-type region 104, they form a protective and isolation structure for the cell. The top width of the P-type region 104 is 1μm. This is to form a low-resistance, large-area contact with the source metal, thereby increasing the freewheeling capability of the parasitic diode of the device. The source metal layer 112 has a width of 3μm and a thickness of 300nm. This is to ensure low-resistance contact between the device and the P+ region 105 and the N-type source region 109, and to ensure the device's current capability. The N-type source region 109 has a thickness of 300 nm and a width of 2 μm. This is to form a reliable low-resistance conductive channel for the device and reduce the on-resistance of the device. The P-type shielding layer 108 has a maximum width of 1.5 μm, a minimum width of 1 μm, a maximum thickness of 600 nm, and a minimum thickness of 300 nm. This is to ensure that the P-type shielding layer 108 fully covers the corner of the device gate, thereby protecting the corner of the device gate structure and improving the reliability of the device. Since the P-type shielding layer 108 is distributed at the corner of the device gate, a conductive channel is formed on the P-type shielding layer 108 near the gate when the device is turned on (positive voltage is applied to the gate metal layer 111). The maximum width of the N-type region 107 is 2.8 μm, the width to the left of the P-type shielding layer 108 is 1 μm, the width directly below the P-type shielding layer 108 is 1.5 μm, and the width to the right of the P-type shielding layer is 300 nm. The maximum thickness is 900 nm, the minimum thickness is 300 nm, and the thickness to the right of the P-type shielding layer 108 is 600 nm. The N-type region 107 forms a conductive channel from the N-type source region 109 to the gate-controlled P-type well region 106 in the device gate control region. This channel has a low doping concentration and forms a common conductive channel with the P-type shielding layer 108, ensuring the conductivity of the device. The P-type well region 106 has a maximum width of 2.8 μm, a minimum width of 800 nm, a minimum thickness of 600 nm, and a maximum thickness of 1200 nm. This is to form a complete enclosure of the N-type region 107, thereby achieving the breakdown voltage structure and gate control structure of the device. The insulating dielectric layer 110 has a bottom thickness of 80 nm and a thickness of 40 nm on the left and right sides. This is to ensure the gate control capability of the device. The gate of the device needs to simultaneously control the inverse conduction of the P-type shielding layers 108 on both sides and the P-type well region 106 at the bottom. The maximum width of the insulating dielectric layer 110 is 5 μm, and the contact width between the bottom and the protrusion 1031 is 1.4 μm. This is to minimize the direct overlap area between the gate and drain while ensuring the reliability of the device, thereby reducing the gate-drain capacitance of the device.

[0037] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A 5KV high-reliability trench-gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate, A buffer layer, wherein the lower side of the buffer layer is connected to the upper side of the silicon carbide substrate; A drift layer, the lower side of which is connected to the upper side of a buffer layer, and the drift layer is provided with protrusions; The P-shaped region has its lower side connected to the upper side of the buffer layer and its inner side connected to the outer side of the drift layer. The lower side of the P+ region is connected to the upper side of the P-shaped region; The lower side of the P-type well region is connected to the upper side of the drift layer, and the inner side of the P-type well region is connected to the outer side of the protrusion. The N-type region has its outer side connected to the P+ region and its lower side connected to the P-type well region. Shielding layer, the shielding layer being connected to the N-type region; The N-type source region has a lower side connected to a P-type well region and a shielding layer, and an outer side connected to a P+ region. An insulating dielectric layer, wherein the lower side of the insulating dielectric layer is respectively connected to a shielding layer, an N-type region, a P-type well region, and the upper side of the protrusion; The insulating dielectric layer has grooves inside; A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the P+ region and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. The 5KV high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The silicon carbide substrate, buffer layer, and drift layer are all N-type, and the shielding layer is P-type.

3. The 5KV high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the P-type well region is greater than the width of the N-type region.

4. The 5KV high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the N-type region is greater than the width of the shielding layer.

5. A 5KV high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the buffer layer is greater than that of the drift layer, and the doping concentration of the buffer layer is less than that of the silicon carbide substrate.

6. A 5KV high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type region is greater than that of the drift layer, and the doping concentration of the P+ region is greater than that of the P-type region.

7. A 5KV high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the shielding layer is greater than the doping concentration of the N-type region, and the doping concentration of the N-type region is greater than the doping concentration of the P-type well region.

8. A 5KV high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the N-type source region is greater than the doping concentration of the masking layer.

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