5kv super junction silicon carbide vdmos
Patent Information
- Application Number
- CN202522321767.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-03
- Publication Date
- 2026-09-22
- Estimated Expiration
- 2035-11-03
AI Technical Summary
[0002]碳化硅VDMOS器件由于其宽禁带特性，相比碳化硅VDMOS器件天然具备高耐压的特点，但是受限于氧化层质量，沟槽碳化硅VDMOS器件的可靠性一直存在问题，平面栅碳化硅VDMOS器件的导通电阻相比沟槽栅碳化硅VDMOS器件的导通电阻要大
一、本实用新型的栅极结构综合了平面栅的高可靠特性和纵向导电沟道控制的低电阻率的特点；
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Figure CN224791001U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a 5kV superjunction silicon carbide VDMOS. Background Technology
[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally have higher voltage withstand capability compared to other silicon carbide VDMOS devices. However, due to limitations in oxide layer quality, the reliability of trench silicon carbide VDMOS devices has always been a problem. The on-resistance of planar gate silicon carbide VDMOS devices is larger than that of trench gate silicon carbide VDMOS devices. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a 5kV superjunction silicon carbide VDMOS, which achieves both high gate reliability and low on-resistance through the design of a combined planar gate and trench gate structure.
[0004] This invention provides a 5kV superjunction silicon carbide VDMOS, comprising: silicon carbide substrate, A drift layer is provided, the lower side of which is connected to the upper side of the silicon carbide substrate. The drift layer contains a first isolation layer, a second isolation layer, and a shielding layer. The second isolation layer is located directly below the shielding layer. The lower sides of both the first and second isolation layers are connected to the upper side of the silicon carbide substrate. A low-resistivity region, the lower side of which is connected to the drift layer and the first isolation layer; The lower side of the P-type well region is connected to the low-resistivity region; The lower side of the P-type source region is connected to the P-type well region; The N-type source region has its lower side connected to the P-type well region, and its inner side connected to the outer side of the N-type source region. An insulating dielectric layer is provided, the lower side of which is connected to a shielding layer, and the outer side of which is connected to the inner side of the low-resistivity region, the inner side of the P-type well region, and the inner side of the N-type source region, respectively; the insulating dielectric layer is provided with trenches. A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the P-type source region and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0005] The advantages of this utility model are: I. The gate structure of this utility model combines the high reliability of a planar gate with the low resistivity of a longitudinal conductive channel. Second, this utility model constructs a first isolation layer to achieve isolation between cells and within cells of conductive channels, avoid current crosstalk within and between cells, avoid reverse isolation inside the device, and improve the reliability of the device. Third, the second isolation layer and the superjunction structure of this utility model share the same potential transfer, which ensures the superjunction structure of the device and can effectively improve the device's withstand voltage capability. Fourth, the shielding layer of this utility model achieves isolation between the gate and drain capacitances, effectively reduces Miller capacitance, reduces the drive loss of the device, and improves the switching speed of the device. Attached Figure Description
[0006] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0007] Figure 1 This is a schematic diagram of a 5kV superjunction silicon carbide VDMOS according to this utility model.
[0008] Figure 2 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 1 .
[0009] Figure 3 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 2 .
[0010] Figure 4 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 3 .
[0011] Figure 5 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 4 .
[0012] Figure 6 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 5 .
[0013] Figure 7 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 6 .
[0014] Figure 8 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 7 .
[0015] Figure 9 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 8 .
[0016] Figure 10 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 9 .
[0017] Figure 11 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 10 .
[0018] Figure 12 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 10 one.
[0019] Figure 13 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 10 two.
[0020] Figure 14 This is a cross-sectional view of the process of a 5kV superjunction silicon carbide VDMOS according to this utility model. Figure 10 three. Detailed Implementation
[0021] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0024] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0025] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0026] like Figure 1 As shown, this application embodiment provides a 5kV superjunction silicon carbide VDMOS, comprising: Silicon carbide substrate 101, A drift layer 102 is provided, the lower side of which is connected to the upper side of the silicon carbide substrate 101. The drift layer 102 contains a first isolation layer 1021, a second isolation layer 1022, and a shielding layer 1023. The second isolation layer 1022 is located directly below the shielding layer 1023. The lower sides of both the first isolation layer 1021 and the second isolation layer 1022 are connected to the upper side of the silicon carbide substrate 101. Low-resistivity region 103, the lower side of which is connected to the drift layer 102 and the first isolation layer 1021; P-type well region 104, the lower side of which is connected to the low-resistivity region 103; P-type source region 105, the lower side of which is connected to P-type well region 104; N-type source region 106, the lower side of N-type source region 106 is connected to P-type well region 104, and the inner side of P-type source region 105 is connected to the outer side of N-type source region 106; An insulating dielectric layer 107 is provided, the lower side of which is connected to a shielding layer 1023, and the outer side of which is connected to the inner side of the low-resistivity region 103, the inner side of the P-type well region 104, and the inner side of the N-type source region 106, respectively; a trench 1071 is provided in the insulating dielectric layer 107. A gate metal layer 108 is disposed within the trench 1071; Source metal layer 109, which is connected to the P-type source region 105 and the N-type source region 106 respectively; And a drain metal layer 110, which is connected to the lower side of the silicon carbide substrate 101.
[0027] In this embodiment, preferably, the doping concentration of the shielding layer 1023 is greater than the doping concentration of the drift layer 102, and the doping concentration of the shielding layer 1023 is greater than the doping concentration of the second isolation layer 1022.
[0028] In this embodiment, preferably, the doping concentration of the low-resistivity region 103 is greater than the doping concentration of the first isolation layer 1021, and the doping concentration of the low-resistivity region 103 is greater than the doping concentration of the drift layer 102.
[0029] In this embodiment, preferably, the width of the shielding layer 1023 is greater than the width of the second isolation layer 1022.
[0030] In this embodiment, preferably, the width of the insulating dielectric layer 107 is equal to the width of the shielding layer 1023.
[0031] like Figures 1 to 14As shown, the above-mentioned method for fabricating VDMOS includes the following steps: Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 110; grow epitaxially on the upper side of silicon carbide substrate 101 to obtain drift layer 102; Step 2: Form a barrier layer 200 above the drift layer 102, etch the barrier layer 200 to form a via, and implant ions to form a first isolation layer 1021 and a second isolation layer 1022; the drift layer 102, the first isolation layer 1021 and the second isolation layer 1022 in steps 1 and 2 can be formed in two steps, that is, a part is formed first and then the other part is formed. Step 3: Ion implantation to form shielding layer 1023; Step 4: Deposition to form the first insulating dielectric region 1072; Step 5: Deposit to form the gate metal layer 108; Step 6: Deposit to form a second insulating dielectric region 1073. The insulating dielectric layer 107 includes a first insulating dielectric region 1072 and a second insulating dielectric region 1073. Step 7: Deposition to form low-resistivity region 103; Step 8: Deposition to form P-type well region 104; Step 9: Deposition to form N-type source region 106; Step 10: Deposition to form P-type source region 105; Step 11: Deposit metal to form source metal layer 109, remove barrier layer 200, and complete the preparation; Before steps 3 to 7 and 9 to 11, the barrier layer 200 from the previous step needs to be removed, the barrier layer 200 needs to be re-formed, and the barrier layer 200 needs to be etched to form a via. The low-resistivity region 103, the P-type well region 104, the N-type source region 106, and the P-type source region 105 can also be formed by epitaxially forming an epitaxial layer on the drift layer 102, and then ion implantation is performed respectively.
[0032] In another embodiment of this invention, the silicon carbide substrate, drift layer, and low-resistivity region are all N-type; the first isolation layer, second isolation layer, and shielding layer are all P-type; and the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 102 is 1-5e17cm. -3 The doping concentration of the first isolation layer 1021 and the second isolation layer 1022 is 1-5e17cm. -3 The doping concentration of the P-type shielding layer 1023 is 1-5e18cm. -3 The doping concentration of the N-type low-resistivity region 103 is 6-10e17cm. -3 The doping concentration of the P-type well region 104 is 6-10e16cm.-3 The doping concentration of the N-type source region 106 is 2-8e18cm. -3 The doping concentration of the P-type source region 105 is 2-8e19cm. -3 The insulating dielectric layer 107 can be made of silicon dioxide, and the gate metal layer 108 and the source metal layer 109 can be made of one or more alloys of copper, nickel, and aluminum. The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 110, reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 is mainly to comprehensively consider the device's breakdown voltage and on-resistance. The doping concentration of the first isolation layer 1021 is to achieve isolation between and within device cells. Its doping concentration is a trade-off between the degree of isolation and improving the doping concentration and breakdown voltage of the device's drift region; the higher the doping concentration, the better. The second isolation layer 1022 forms a superjunction structure with the N-type drift layer 102. The doping concentration of the P-type shielding layer 1023 is to shield the capacitance from the device's gate to the drain and protect the device's gate structure. The doping concentration of the P-type well region 104 is to comprehensively ensure low gate charge, reduce device switching losses, and improve device switching speed. The N-type silicon carbide substrate 101 of the device is 1 μm thick to ensure support during the device fabrication process. The N-type drift layer 102 is 50 μm thick, which is a trade-off between the doping concentration of the superjunction structure device and the on-resistance and epitaxial thickness. The width of the P-type source region 105 of the device cell is 1μm and the thickness is 200nm. This is because the device adopts a deposition process, and the structural thickness is controllable. Therefore, the thickness is designed to be 200nm to reduce the thickness while ensuring the structural capability of the device, so as to reduce the parasitic diode loss of the device. The width of the N-type source region 106 of the device cell is 1μm and the thickness is 200nm. This is because the device adopts a deposition process, and the structural thickness is controllable. Therefore, the thickness is designed to be 200nm to reduce the thickness while ensuring the structural capability of the device, so as to reduce the on-resistance of the device. The width of the P-type well region 104 is 2μm and the thickness is 600nm. This is to ensure the drain-source voltage withstand capability during reverse breakdown and to ensure the gate control capability of the device. The N-type low-resistivity region 103 has a width of 2μm and a thickness of 200nm. This is to form a low-resistivity conductive channel for the device, and this conductive channel will not affect the protection of the P-type well region for the device source when the device is reverse breakdown voltage. The P-type shielding layer 1023 is distributed directly below the insulating dielectric layer 107 of the device. Its width is equal to that of the insulating dielectric layer 107. The shielding layer 1023 has a width of 2μm and a thickness of 300nm. This is the minimum thickness that can be controlled by ion implantation, which can ensure the protection of the device gate. The thickness of the gate metal layer 108 is 1.1 μm. This is to ensure that the bottom of the gate metal layer 108 is lower than the bottom of the corresponding P-type well regions 104 on the left and right sides, thereby ensuring the gate control capability of the device and ensuring the low resistance of the conductive channel. The bottom thickness of the insulating dielectric layer 107 of the device is 100nm, and the thickness on the left and right sides is 50nm. This is to ensure the gate control capability of the device. At the same time, the process conditions determine that when the thickness on the left and right sides is 50nm, the thickness of the bottom insulating dielectric layer is 100nm.
[0033] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A 5kV superjunction silicon carbide VDMOS, characterized in that: include: silicon carbide substrate, A drift layer is provided, the lower side of which is connected to the upper side of the silicon carbide substrate. The drift layer contains a first isolation layer, a second isolation layer, and a shielding layer. The second isolation layer is located directly below the shielding layer. The lower sides of both the first and second isolation layers are connected to the upper side of the silicon carbide substrate. A low-resistivity region, the lower side of which is connected to the drift layer and the first isolation layer; The lower side of the P-type well region is connected to the low-resistivity region; The lower side of the P-type source region is connected to the P-type well region; The N-type source region has its lower side connected to the P-type well region, and its inner side connected to the outer side of the N-type source region. An insulating dielectric layer, the lower side of which is connected to a shielding layer, and the outer side of which is connected to the inner side of the low-resistivity region, the inner side of the P-type well region, and the inner side of the N-type source region, respectively. The insulating dielectric layer has grooves inside; A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the P-type source region and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The 5kV superjunction silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the shielding layer is greater than that of the drift layer, and the doping concentration of the shielding layer is greater than that of the second isolation layer.
3. A 5kV superjunction silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the low-resistivity region is greater than that of the first isolation layer, and the doping concentration of the low-resistivity region is greater than that of the drift layer.
4. A 5kV superjunction silicon carbide VDMOS as described in claim 1, characterized in that: The width of the shielding layer is greater than the width of the second isolation layer.
5. A 5kV superjunction silicon carbide VDMOS as described in claim 1, characterized in that: The width of the insulating dielectric layer is equal to the width of the shielding layer.