Camera system and semiconductor device

Abstract

A camera system and semiconductor device. The semiconductor device can include a substrate including a plurality of first contact pads disposed on a first surface and a plurality of second contact pads disposed on a second surface. The substrate includes a plurality of interconnect structures extending between the first surface and the second surface. The semiconductor device can include an axially extending first portion of the interconnect structures having sidewalls of a first profile. The semiconductor device can include an axially extending second portion of the interconnect structures having sidewalls of a second profile, and the second profile is shallower than the first profile.

Description

Technical Field

[0001] This disclosure relates to a camera system and a semiconductor device. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. Recently, improvements in device density have increasingly been associated with three-dimensional features, such as combinations of various substrates (e.g., stacked wafers for three-dimensional integrated circuits (3DIC)). Utility Model Content

[0003] According to some embodiments of this disclosure, a semiconductor device includes a substrate, a first portion extending axially from a plurality of interconnect structures, and a second portion extending axially from a plurality of interconnect structures. The substrate includes a plurality of first contact pads disposed on a first surface and a plurality of second contact pads disposed on a second surface. The substrate includes a plurality of interconnect structures extending between the first and second surfaces. The first portion has a plurality of sidewalls with a first profile. The second portion has a plurality of sidewalls with a second profile, and the second profile is shallower than the first profile.

[0004] According to some embodiments of this disclosure, a semiconductor device includes a substrate and a conductive interconnect structure. The substrate includes a first conductive contact pad and a second conductive contact pad disposed on a first surface and a second surface, respectively. The conductive interconnect structure is disposed in the substrate. The conductive interconnect structure has a first end having a first lateral dimension and a second end having a second lateral dimension. The first end is connected to the first conductive contact pad, the second end is connected to the second conductive contact pad, and the second lateral dimension is smaller than the first lateral dimension. The conductive interconnect structure has an axially extending first portion adjacent to the second end and an axially extending second portion adjacent to the first end. The first portion has a plurality of sidewalls with a first profile, and the second portion has a plurality of sidewalls with a second profile, wherein the second profile is shallower than the first profile.

[0005] According to some embodiments of this disclosure, a camera system includes a first substrate and a second substrate. The first substrate includes a plurality of image sensors. The second substrate includes an image signal processor coupled to the image sensors via a plurality of interconnect structures extending axially between the first and second substrates. Each interconnect structure includes an axially extending first portion and an axially extending second portion. The first portion has a plurality of sidewalls with a first profile and is located close to the image sensors. The second portion has a plurality of sidewalls with a second profile that is shallower than the first profile, and the first portion is located close to the image signal processor. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1 Illustrated cross-sectional views of a semiconductor structure according to some embodiments;

[0008] Figure 2 Illustrated cross-sectional views of an interconnect structure according to some embodiments;

[0009] Figures 3 to 12 Top and side views depicting various alignments between the interconnect structure and the contact pad according to some embodiments;

[0010] Figure 13 and Figure 14 A top view depicting the interconnect structure and contact pad arrangement for the gate, drain, and source of a transistor according to some embodiments;

[0011] Figure 15 and Figure 16 A top view depicting another arrangement of interconnect structures and contact pads for the gate, drain, and source of a transistor according to some embodiments;

[0012] Figure 17 and Figure 18 An additional top view depicting another arrangement of interconnect structures and contact pads for the gate, drain, and source of a transistor according to some embodiments;

[0013] Figure 19 and Figure 20 A top view depicting yet another arrangement of interconnect structures and contact pads for the gate, drain, and source of a transistor according to some embodiments;

[0014] Figure 21 and Figure 22 A top view depicting another arrangement of interconnect structures and contact pads for the gate, drain, and source of a transistor according to some embodiments;

[0015] Figure 23 A flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments;

[0016] Figure 24 A flowchart illustrating a method for operating a camera system according to some embodiments.

[0017] [Symbol Explanation]

[0018] 100: Semiconductor devices

[0019] 102: First substrate

[0020] 104: Second substrate

[0021] 106: Third substrate

[0022] 108: Surface

[0023] 110: Surface

[0024] 112: Surface

[0025] 114: Surface

[0026] 116: Image Sensor

[0027] 118: Image Signal Processor

[0028] 120: Interconnection Structure

[0029] 122: Contact pad

[0030] 124: Contact pad

[0031] 126: Through-hole structure

[0032] 128: Gate Structure

[0033] 130: Source / Drain

[0034] 132: Trap Zone

[0035] 140: Trajectory

[0036] 200: Sectional View

[0037] 201: Total Vertical Dimensions

[0038] 202: Part Three

[0039] 204: Part One

[0040] 206: Part Two

[0041] 208: Top horizontal dimension

[0042] 210: Sidewall

[0043] 212: Negative taper

[0044] 214: Negative taper

[0045] 216: Pitch

[0046] 218: Spacing

[0047] 1202: Trace Section

[0048] 1302, 1402, 1502, 1602, 1702, 1802, 1902, 2002, 2102, 2202: First Component

[0049] 1304, 1404, 1504, 1604, 1704, 1804, 1904, 2004, 2104, 2204: Second Component

[0050] 1306, 1406, 1506, 1606, 1706, 1806, 1906, 2006, 2106, 2206: Third Component

[0051] 2300, 2400: Method

[0052] 2302, 2304, 2306, 2308, 2310: Operations

[0053] 2402, 2404: Operation Detailed Implementation

[0054] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0055] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” “above,” “top,” and “bottom” may be used herein to describe the relationship between one element or feature and another as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0056] The reference to “or” can be interpreted as inclusive, so any term described using “or” can refer to a single, more than one, or any of the descriptive terms. A reference to at least one of a list of connecting terms can be interpreted as inclusive, meaning a single, more than one, or any of the descriptive terms. For example, a reference to “at least one of “A” and “B”” can include only “A”, only “B”, or both “A” and “B”. Such references used in conjunction with “contains” or other open terms can include additional items.

[0057] Three-dimensional integrated circuits (3DICs) comprise multiple layers of electronic circuitry that are vertically stacked and interconnected to form a semiconductor device. This approach offers significant advantages over traditional two-dimensional (2D) ICs, including higher density and reduced inter-circuit delay. However, this increased density in 3DICs can lead to relatively high interconnect density. These interconnections can include those similar to those on 2DICs, as well as vertical interconnections to distribute power and data signals among the various stacked circuits. Routing these interconnections between and within the individual circuits of a 3DIC can be challenging.

[0058] Typically, vertical interconnect structures can be coupled to contact pads on various substrates of a 3DIC. For example, the interconnect structure may include interlayer vias (ILVs), (e.g., through-substrate vias (TSVs), sometimes also referred to as through-silicon vias, but not limited thereto). TSVs or other interconnect structures may extend along the axial length between contact pads coupled at the ends. Opposite ends of the interconnect structure may include different lateral dimensions (relatively wide legs and relatively narrow tips positioned opposite each other). Thus, the lateral dimension of the interconnect structure closer to one end (e.g., the narrow tip) can be used to extend through high-density environments, such as dense metallization layers, well regions (e.g., P-wells or N-wells), or shallow trench isolation (STI) regions. The lateral dimension of the interconnect structure (closer to the other end of the interconnect structure (e.g., the legs)) can be used to provide a robust, low-resistance connection to another substrate.

[0059] In some embodiments, the 3DIC includes a camera system. For example, a first substrate of the 3DIC may include an image sensor. The image sensor may be coupled to an image signal processor on another substrate. The density of the image sensor may be limited by the number of available interconnect network connections (or current carrying capacity). For example, the interconnect network may include various metallized lines and via structures, including TSV interconnect structures. A first end (e.g., a narrow tip) of the TSV interconnect structure may be used to interface with the image sensor via a metallization layer, which can help provide connectivity to image sensors arranged in a high-density configuration. A second end (e.g., a lead) of the TSV may be used to interface with another contact pad, which can reduce the risk of resistance or electromigration, or increase the yield of the semiconductor device.

[0060] Figure 1 A cross-sectional view of a semiconductor device 100 according to some embodiments is shown. The semiconductor device 100 includes a first substrate 102 coupled to a second substrate 104 via an interconnect network, the interconnect network including an interconnect structure 120 and other conductive elements of the metallization layers of the respective substrates 102 and 104. In some embodiments, the interconnect structure 120 coupling the first and second substrates extends through a third substrate 106 disposed between the first and second substrates 102 and 104. That is, the interconnect structure 120 may include TSVs or other substrate-penetrating interconnects.

[0061] In some embodiments, the semiconductor device 100 is a sensing system (e.g., a sensing system for a camera system). The first substrate 102 may include various image sensors 116. For example, the image sensor 116 may include a charge-coupled device (CCD), a complementary metal-oxide-semiconductor sensor (CMOS), or other sensing technologies. According to such a system, the proximity of the (image) sensor 116 to the (image) signal processor 118 can reduce the effects of signal distortion caused by transmission line asymmetry, environmental or system noise, etc. This illustrative example should not be construed as limiting. Embodiments of this disclosure are not limited to camera devices; the systems and methods of this disclosure can be used in various memory, computing devices, non-camera sensor systems, or other high-density semiconductor devices.

[0062] In some embodiments, the density of image sensors 116 is constrained by the connectivity of the interconnect network. For example, the number of image sensors 116 (corresponding to the megapixel count of the camera system) may be limited by the number of connections to the image signal processor (ISP) 118. Relatedly, the range of values ​​for a particular image sensor 116 may be limited by the current carrying capacity of the interconnect structure 120 (e.g., corresponding to the current flowing between the image sensors 116 and the ISP 118). Therefore, efforts to improve image quality at the pixel level may tend to increase the size of the interconnect structure 120, resulting in a decrease in pixel density, while efforts to improve image quality based on pixel density may tend to decrease the size of the interconnect structure 120.

[0063] The second substrate 104 may include an interconnect 118, which is coupled to the image sensor 116 via an interconnect structure 120 extending axially between the first substrate 102 and the second substrate 104. Some exemplary geometries of the interconnect structure 120 are provided below, for example... Figure 2 .like Figure 1 As shown, the axially extending first (upper) portion of the interconnect structure 120 includes sidewalls of a first profile (depicted as generally vertical, such as a rectangular prism or cylindrical cross-section). The axially extending second (lower) portion of the interconnect structure 120 has sidewalls of a profile that is shallower than the first profile. This portion is sometimes referred to as a foot.

[0064] The first substrate 102 and the third substrate 106 can be coupled face-to-face, wherein the metallized surface 108 of the first substrate 102 faces the metallized surface 112 of the second substrate 102. The first substrate 102 and the third substrate 106 can be coupled via a connection between their respective metallized layers. For example, each metallized layer starting from the substrate surfaces 108, 112 can be referred to as layer M0, M1, M2, and so on, until the top layer is reached. The top layers of the first substrate 102 and the third substrate 106 can be coupled to each other. Each metallized layer may include a lateral conductive element (trace 140) coupled to a via structure, such that the image sensor 116 can be coupled to a transistor disposed on the third substrate 106. The transistor can adjust the gain of the signal transmitted from the image sensor 116 to the ISP 118. In some embodiments, the ISP 118 can modulate the operation of the transistor via a control signal. The image sensor signal or control signal can be transmitted along the interconnect structure 120.

[0065] The second substrate 104 can be coupled to the third substrate 106 in a front-back configuration. As shown, the back side of the third substrate 106 (e.g., surface 114 opposite to the front surface 112) is coupled to the metallization layer of the second substrate 104. For example, the third substrate 106 may include contact pads 122 coupled to the interconnect structure 120, while the second substrate 104 may include corresponding contact pads 124. The contact pads 124 of the second substrate 104 may be coupled to the ISP 118 along one or more alternating via structures 126 and lateral conductive elements (sometimes referred to as traces 140) formed on the surface 110 of the second substrate 104.

[0066] Any substrate may include transistors disposed along an active surface. For example, a first substrate 102 may include a reset transistor; a second substrate 104 may include a digital or analog signal processing or memory transistor; and a third substrate may include a source follower transistor (buffer transistor) or a select transistor for an image sensor 116. Each transistor may include a gate structure 128 and a source / drain 130, each of which may be coupled to an interconnect structure 120 via a via structure and other conductive elements of the metallization layer (e.g., lateral traces 140). Furthermore, various substrates may include isolation or other features such as well regions 132. Depending on the proximal connection between the interconnect structure 120 and the gate structure 128 or the source / drain 130, the interconnect structure 120 may pass near the well region 132 (e.g., between adjacent well regions 132). In some embodiments, the lateral distance between the well region 132 and the interconnect structure 120 is at least half the lateral dimension of the upper portion of the interconnect structure 120 (e.g., hereinafter referred to as...). Figure 2 (Half of the uppermost lateral dimension 208). For example, in some embodiments, the interconnect structure 120 may extend within one micrometer (μm) of at least one well region 132. Therefore, transistor density can be increased by reducing the size of the portion of the interconnect structure 120 closest to the transistor (e.g., the uppermost portion).

[0067] In some embodiments, the feet of the interconnect structure 120 may extend laterally, greater than the spacing between features such as adjacent well regions 132 or traces 140. Thus, the stepped profile of the "feet" of the interconnect structure 120 may increase density relative to other methods that may interfere with (e.g., couple or contact) the well regions 132 (e.g., vertical or continuous tapered profiles).

[0068] Figure 2This illustration shows a cross-sectional view 200 of an interconnect structure 120 according to some embodiments. The total vertical dimension 201 of the interconnect structure 120 may extend a distance from a semiconductor substrate (e.g., a silicon wafer or die). For example, the total vertical dimension 201 may extend more than 50 micrometers (μm). In some embodiments, a first portion 204 of the vertical dimension 201 extends greater than about 35 μm. In some embodiments, a second portion 206 extends between about 4 μm and 9 μm. In some embodiments, a third portion 202 extends between about 1 μm and 5 μm.

[0069] Most of the vertical dimensions (e.g., third section 202) extend substantially parallel to the sidewall 210. For example, the sidewall 210 may extend between the feet and opposite ends of the interconnect structure 120 with a negative taper of less than 1 degree (e.g., 0 degrees). In some embodiments, the depicted cross-sectional view may be substantially symmetrical about the axis of the interconnect structure 120 (e.g., the interconnect structure 120 may be cylindrical). In some embodiments, the cross-sectional view may be substantially symmetrical about at least one rotation angle (e.g., the interconnect structure 120 may be a rectangular prism truncated according to the tapered sidewalls). In some embodiments, only a portion of the sidewalls may be tapered (e.g., two opposite sides of the truncated rectangular prism of the interconnect structure 120).

[0070] The first portion of vertical dimension 204 (sometimes referred to as a foot or base) includes sidewalls that exhibit a greater taper than the uppermost portion (described herein as the third portion 202 of total vertical dimension 201). For example, the sidewalls of the first portion 202 may exhibit a negative taper 214 greater than 1 degree (e.g., between about 1 degree and about 10 degrees). Therefore, the lateral dimension of the base of the foot may exceed that of other portions of interconnect structure 120. The various portions of interconnect structure 120 may correspond to individual etching operations or sub-operations. For example, in some embodiments, the uppermost portion may be formed according to a relatively anisotropic process (e.g., a Bosch process), while the foot or other adjacent portions may be formed according to a different orientation or isotropic process. That is, the openings of interconnect structure 120 may be formed according to a multi-step removal process (e.g., a multi-step etching process).

[0071] A second portion of the vertical dimension 206 is located between the first portion 204 and the third (uppermost) portion 202. The sidewalls of the second portion 206 may exhibit a negative taper 212, which is larger than that of the first portion 204 but smaller than that of the third portion 202. In some embodiments, the negative taper 212 of the second portion 206 is between about 1 degree and about 5 degrees. In some embodiments, the second portion 206 is omitted. In some embodiments, an additional portion may be formed between the first portion 204 and the uppermost end of the interconnect structure 120. The additional portion may reduce the offset angle between the portions, thereby avoiding non-uniform etching, impedance mismatch, electromigration, etc. Each portion may correspond to a separate step of the stepped profile of the foot. In some embodiments, each step may be formed according to a separate process (e.g., an etching process associated with an isotropic level corresponding to the sidewall profile).

[0072] In some embodiments, the pitch 216 between adjacent interconnect structures 120 may be less than about 7 μm (e.g., between about 3 μm and 7 μm). The uppermost lateral dimension 208 of the interconnect structure 120 (sometimes referred to as the critical dimension (CD)) may be less than 5 μm (e.g., between about 0.5 μm and 5 μm). The pin spacing 218 may correspond to the pitch 216 minus the pin's lateral dimension. For example, the pin may include a dimension larger than the uppermost lateral dimension 208 (e.g., in some embodiments, greater than 10%, such as greater than about 30%, greater than about 50%, or greater). For example, an illustrative example of interconnect structure 120 may include an uppermost lateral dimension 208 of about 3 μm, and the pin may include a corresponding lateral dimension of about 5 μm.

[0073] See general overview Figures 3 to 12 According to some embodiments, top and side views are provided of various alignments between the interconnect structure 120 and the contact pads 122, 124. For example, Figure 3 and Figure 4 The corresponding side view and top view of the same component can be provided; Figure 5 and Figure 6 A corresponding side view and top view of another component can be provided; Figure 7 and Figure 8 A corresponding side view and top view of another component can be provided; Figure 9 and Figure 10 A corresponding side view and top view of another component can be provided; Figure 11 and Figure 12 A corresponding side view and top view of another component can be provided.

[0074] See also Figure 3 The side view provides a detailed view of the stack. For example, the stack can be compared with... Figure 1The second substrate 104 and the third substrate 106 are stacked together. The stack includes the feet of the interconnect structure 120. Although depicted with substantially vertical sidewalls for clarity of the figures (e.g., Figure 3 , Figure 5 , Figure 7 , Figure 9 and Figure 11 However, in at least some embodiments disclosed herein, the sidewalls of the interconnect structure 120 may exhibit a negative taper. The interconnect structure 120 is connected to the same substrate (e.g., Figure 1 The third substrate 106) contacts the contact pad 122. The interconnect structure 120 and the contact pad 122 may be made of the same or different materials, as will be referred to below. Figure 4 Some examples are provided. The contact pad 122 is coupled to another contact pad 124 of another substrate. For example, the other substrate may be coupled to the rear surface 114 of a substrate including interconnect structure 120. The contact pad 124 may in turn be coupled to another substrate (e.g., in some embodiments, a second substrate 104 including ISP 118). For example, the contact pad 124 may be coupled to the transistor of ISP 118 via via structure 126 and traces 140 of a metallization layer disposed along the surface of a semiconductor portion of the second substrate 104.

[0075] See also Figure 4 A top view, provided as a transparent view, depicts the relative lateral positions of the various stacked elements. According to some embodiments, the hidden portions of the interconnect structure 120 are continuous. Therefore, the feet of the interconnect structure 120 can couple to the surface of the upper contact pad 122 on its lateral surface, thereby reducing the resistance of the contact interface. Furthermore, any misalignment, over-etching, voids in the interconnect structure 120, or other manufacturing variations can be tolerated without affecting the operation of the semiconductor device 100. For example, compared to other methods, heating and current density at the interface between the interconnect structure 120 and adjacent contact pads 122 can be reduced, thereby reducing electromigration and extending device lifetime.

[0076] According to some embodiments, the hidden portions of contact pads 122, 124 are continuous. Therefore, the lower contact pad 124 may be referred to as laterally surrounding the illustrated via structure 126. The via structure 126 may be a via formed in the uppermost metallization layer above the second substrate 104. Furthermore, multiple via structures 126 may be provided (in the illustrated embodiment, all via structures 126 are laterally surrounded by contact pads 124). Additionally, the via structure 126 is configured to be vertically aligned with at least a portion of the interconnect structure 120, thereby reducing the path resistance between the interconnect structure 120 and the trace 140, and further reducing noise or other signal variations due to shorter, straighter, and lower-resistance vertical paths.

[0077] In some embodiments, the various conductive elements provided herein (including interconnect structure 120, via structure 126, trace 140, or gate structure 128) may comprise the same or similar materials. However, when the same materials are included, these portions may be formed according to separate etching and deposition operations, resulting in interfaces that may exhibit contact resistance or other inhomogeneities. Therefore, the electrical properties of the interfaces may be particularly important at these interfaces, especially where manufacturing variations exist. Furthermore, in some embodiments, the various conductive elements may comprise different materials. For example, the material of interconnect structure 120 may comprise tungsten, aluminum, or copper; the material of via structure 126 and trace 140 may comprise copper or aluminum. Gate structure 128 may comprise various metals or polysilicon (PO) gates. Each combination of these materials is considered in the various embodiments. In addition, some materials may comprise individual materials, such as alloys, or individual metallization layers may use different materials.

[0078] See also Figure 5 In the side view, the via structure 126 is not aligned with the interconnect structure 120 along the vertical axis. In fact, neither the via structure 126 nor any portion of the interconnect structure 120 laterally overlaps. Therefore, the current flowing between the via structure 126 and the interconnect structure 120 will flow laterally along the contact pads 122, 124 (and between the contact pads 122, 124). However, at least the contact pads 124 adjacent to the via structure 126 laterally surround the via structure 126. As described above, compared to other embodiments (such as trace connections) (e.g., as... Figures 13 to 22 As shown in the connection with the gate structure 128, this geometry can reduce contact resistance, electromigration, etc.

[0079] See also Figure 6 In the top view, according to the transparent view, contact pads 122, 124 are depicted as misaligned across the entire surface, but including significant overlap (e.g., overlap / contact area exceeding 50%). Furthermore, the upper contact pad 122 laterally surrounds the interconnect structure 120. In some embodiments, contact pads 122, 124 comprise or are composed of the same material, and at least one of the through-hole structure 126 or the interconnect structure 120 comprises a different material. Therefore, increasing the contact area of ​​different materials may be more strongly correlated with the yield or performance of the device than with the same material of the contact pads 122, 124.

[0080] See also Figure 7 The side view, with Figure 5 Similarly, the through-hole structure 126 is not aligned with the interconnect structure 120 along the vertical axis. However, the contact pads 122 and 124 are depicted as mating. Relative to Figure 5This embodiment may be less sensitive to substrate-substrate misalignment, but it can occupy more space in the metallization layer because the contact pads 122 and 124 have larger surface areas. See also Figure 8 In the top view, rectangular contact pads 122 and 124 are depicted as laterally extending in the same layer, as shown in the above. Figure 7 As stated above.

[0081] See also Figure 9 A side view depicting multiple through-hole structures 126. For example, two through-hole structures 126 are depicted according to the depicted cross-sectional view. See also... Figure 10 The top view shows six via structures 126. Increasing the number of via structures 126 can further reduce electromigration, resistance, and the vulnerability of the stacked structure to manufacturing variations (e.g., voids, over-etching, etc.).

[0082] See also Figure 11 The side view provides a view with Figure 5 or Figure 7 Similar outlines. However, according to Figure 12 The transparent top view shows that the through-hole structure 126 is asymmetrical, perpendicular to... Figure 11 The cutting line extends in the direction of the cutting line more than Figure 11 The width shown is longer. This through-hole structure 126 can provide some of the benefits of multiple through-holes in a more compact setup. Although Figures 3 to 12 Various through-hole structures 126 are provided as rectangular through-hole structures (e.g., Figure 11 and Figure 12 Non-square rectangles and Figures 3 to 10 The through-hole structure 126 can be provided in various geometries (such as square or rectangular shapes). For example, in some embodiments, the through-hole structure 126 (or contact pads 122, 124 and interconnect structure 120) can be provided as substantially cylindrical.

[0083] In some embodiments, such as Figure 12 As shown, contact pads 122 and 124 can be coupled to trace portion 1202 to couple to other conductive elements, or to facilitate alignment of the individual contact pads 122 and 124.

[0084] Figure 13 and Figure 14 A top view depicting the arrangement of the interconnect structure 120 and contact pads 122, 124 for the gate structure 128 and drain / source region 130 of a transistor according to some embodiments. First see... Figure 13 The transparent view depicts according to Figure 4The top view provides first component 1302 and second component 1304. These components may include contact pads 122, 124 for coupling to the drain / source 130 of the transistor. Third component 1306 includes contact pads 122, 124 coupled to the gate structure 128 of the same transistor (e.g., polysilicon or metal gate structure 128).

[0085] In some embodiments, as shown, the gate structure 128 or the via structure 126 coupled thereto may not be laterally surrounded by contact pads 122, 124. For example, contact pads 122, 124 may be coupled to via structure 126 via trace portions 1202 that separate contact pads 122, 124 from via structure 126. In some instances, relatively low gate currents may be irrelevant to the electromigration risks associated with source / drain contacts. However, in some embodiments, the gate current may be slightly higher, or the contact pads 122, 124 for gate drive current may laterally surround the coupled near-end via structure 126, thereby reducing the risk from other manufacturing variations (e.g., voids or over-etching). Instead, as shown, using trace portions 1202 instead of significantly larger contact pads 122, 124 may better comply with some design rule checks (DRCs) or help increase the density of interconnects or their wiring (e.g., reduce the metallization density of a layer) compared to other methods.

[0086] In some embodiments, a subset of transistor nodes are coupled along a particular substrate junction (e.g., coupled to a TSV or other interconnect structure 120). For example, at least one source / drain may be coupled between substrate pairs, while a gate or other source / drain may be coupled along the surface of one of the substrate pairs or to another substrate.

[0087] See Figure 14 A top view depicting the layout of the conductive elements of a transistor, relative to... Figure 13 The components are inverted. Specifically, a first component 1402, a second component 1404, and a third component 1406 are provided, mirroring the first component 1302, the second component 1304, and the third component 1306 on a first axis of symmetry. In another embodiment, the conductive element may be reflected on another axis of symmetry (e.g., perpendicular to the first axis of symmetry).

[0088] Figure 15 and Figure 16 A top view depicting another arrangement of the interconnect structure 120 and contact pads 122, 124 for the gate, drain and source of a transistor according to some embodiments. Figure 15 Depicting based on Figure 6 The provided stacked inverted examples include the first component 1502 and the second component 1504. The third component 1506, with a gate, is similar. Figure 13 and Figure 14 The third components 1306 and 1406 (depicted as rotating from themselves). Figure 16 Depicting Figure 15 An inverted instance of the first component 1602, the second component 1604, and the third component 1606, and Figure 15 The first component 1502, the second component 1504 and the third component 1506 are inverted.

[0089] Figure 17 and Figure 18 An additional top view depicts another arrangement of the interconnect structure 120 and contact pads 122, 124 for the gate, drain, and source of a transistor according to some embodiments. Specifically, Figure 17 The first component 1702 and the second component 1704 correspond to Figure 8 A top view is provided. The third component 1706 of the gate structure 128 is similar to... Figure 13 The third component 1306 is provided. Figure 18 Described as with Figure 17 Inverted so as to include inverted first component 1802, second component 1804 and third component 1806.

[0090] Figure 19 and Figure 20 An additional top view illustrating yet another arrangement of the interconnect structure 120 and contact pads 122, 124 for the gate, drain and source of a transistor according to some embodiments. Figure 19 The first component 1902 and the second component 1904 correspond to Figure 10 A top view is provided. The third component 1906 of the gate structure 128 is similar to... Figure 13 The third component 1306 is provided. Figure 20 Described as with Figure 19 Inverted so as to include inverted first component 2002, second component 2004 and third component 2006.

[0091] Figure 21 and Figure 22 An additional top view illustrating another arrangement of the interconnect structure 120 and contact pads 122, 124 for the gate, drain and source of a transistor according to some embodiments. Figure 21 The first component 2102 and the second component 2104 correspond to Figure 12 A top view is provided. The third component 2106 of the gate structure 128 is similar to... Figure 13 The third component 1306 is provided. Figure 22 Described as with Figure 21 Inverted so as to include inverted first component 2202, second component 2204 and third component 2206.

[0092] Figure 23A flowchart illustrating a method 2300 for manufacturing a semiconductor device 100 according to some embodiments is provided. Method 2300 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that various methods can be implemented... Figure 23 Additional operations are provided before, during, or after Method 2300, and this document may only briefly describe some of these additional operations.

[0093] Method 2300 includes operation 2302: forming a first opening. The sidewalls of the opening are formed with a first profile in the substrate. The first profile may be substantially vertical, such as having a negative taper of less than 1 degree. For example, the first opening may correspond to the (uppermost) third portion 202 of the various interconnect structures 120 provided herein.

[0094] Method 2300 includes operation 2304: forming a second opening in a substrate, the second opening having sidewalls of a second profile that is shallower than a first profile. In some embodiments, the second opening is formed by extending a portion of the first opening. For example, a longitudinal portion of the first opening may be tapered from the first opening (e.g., along sidewalls exhibiting a negative taper greater than that of the first opening). In some embodiments, the opening may be extended to form additional portions. For example, a portion of the longitudinal length of the second opening may be extended to form a third opening (e.g., the first, second, and third openings may correspond to a first vertical dimension 202, a second vertical dimension 204, and a third vertical dimension 206). In some embodiments, the respective openings are formed end-to-end with each other (e.g., such that the first and second openings are longitudinally adjacent, the second and third openings are longitudinally adjacent, etc.).

[0095] Method 2300 includes operation 2306: forming a conductive interconnect structure 120 in the first opening and the second opening. For example, the conductive interconnect structure 120 may be formed according to a metal deposition process. In some embodiments, the metal includes tungsten, aluminum, or copper, and may be used to couple with contact pads of the same or different materials (e.g., contacts including tungsten or aluminum).

[0096] Method 2300 includes operation 2308: connecting a first end of conductive interconnect structure 120 to a first conductive contact pad, the first end of conductive interconnect structure 120 having a first lateral dimension. For example, the first end may refer to a foot of interconnect structure 120, and the contact pad 122 may refer to a contact pad 122 disposed along the surface of a substrate.

[0097] Method 2300 includes operation 2310: connecting a second end (e.g., a narrow tip) of the conductive interconnect structure 120 to a second conductive contact pad. For example, the second conductive contact pad may refer to or include various conductive elements, such as conductive elements disposed in a metallization layer of the substrate. In some embodiments, these conductive elements may be coupled to transistors on the substrate.

[0098] As described above, the second end of the conductive interconnect structure 120 may have a second lateral dimension smaller than the first lateral dimension. The second end may extend near other components of the semiconductor device 100, allowing the smaller dimension to contribute to device density. For example, the first lateral dimension may couple to or interfere with another component. Such other components may include, for example, a metallization layer, a well region (e.g., a P-well or N-well), or a conductive interconnect of another component. A portion of the conductive interconnect structure 120 formed in the first opening may be spaced from an element (e.g., another component). This distance is less than half the difference between the first and second lateral dimensions. That is, if the narrower portion of the interconnect structure 120 is replaced with the wider portion, the interconnect structure 120 may contact other elements.

[0099] Figure 24 A flowchart illustrating a method 2400 for operating a camera system according to some embodiments is provided. Method 2400 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that various methods can be implemented... Figure 24 Additional operations are provided before, during, or after Method 2400, and this document may only briefly describe some of these additional operations.

[0100] Method 2400 includes operation 2402: transmitting image data from a plurality of image sensors 116 to an ISP 118 along a plurality of interconnect structures 120. The interconnect structures 120 may include various interconnect structures 120 disclosed herein, such as TSVs. For example, in some embodiments, the image sensors 116 are disposed on a first substrate, while the ISP 118 is disposed on a second substrate. The first substrate is bonded to the second substrate. For example, the first substrate and the second substrate may each be coupled to a third substrate, the third substrate separating the first substrate from the second substrate. In some embodiments, the third substrate includes a plurality of transistors coupled to the ISP 118 via interconnect structures 120 passing through the body of the second substrate (e.g., the interconnect structures 120 may include TSVs of the second substrate).

[0101] Method 2400 includes operation 2404: generating an image. For example, ISP 118 may generate an image based on image data received from received image data. In some embodiments, ISP 118 may modulate an input signal by providing a modulation signal (e.g., to a transistor coupled to image sensor 116) that is transmitted along one of the interconnect structures 120. In some embodiments, method 2400 includes more or fewer operations. For example, method 2400 may omit operation 2404, or may include further operations.

[0102] In some embodiments, the technology described herein relates to a semiconductor device comprising: a substrate including a plurality of first contact pads disposed on a first surface and a plurality of second contact pads disposed on a second surface, the substrate including a plurality of interconnect structures extending between the first and second surfaces; axially extending first portions of the interconnect structures having sidewalls with a first profile; and axially extending second portions of the interconnect structures having sidewalls with a second profile that is shallower than the first profile.

[0103] In some embodiments, the technology described herein relates to a semiconductor device in which a first surface is disposed in a first metallization layer of a substrate; and a second surface is disposed on the back side of the substrate, and the second contact pads are coupled to a second metallization layer of the second substrate.

[0104] In some embodiments, the technology described herein relates to a semiconductor device in which a second substrate includes an image signal processor and a first metallization layer of the substrate is coupled to a third metallization layer of a third substrate, the third substrate including a plurality of image sensors, the interconnect structures of which electrically couple the image sensors to the image signal processor.

[0105] In some embodiments, the technology described herein relates to a semiconductor device in which a third contact pad of a second metallization layer is coupled to and laterally surrounds a plurality of via structures of the second metallization layer.

[0106] In some embodiments, the technology described herein relates to a semiconductor device in which a third contact pad of a second metallization layer is coupled to and laterally surrounds a rectangular via structure of the second metallization layer.

[0107] In some forms, the technology described herein relates to a semiconductor device in which a first lateral dimension (perpendicular to the axial extension of one or more interconnect structures) at a first vertical position of one or more of these interconnect structures exceeds the distance between conductive elements of one or more interconnect structures at a second vertical position, which is perpendicularly spaced from the first vertical position.

[0108] In some embodiments, the technology described herein relates to a semiconductor device including a third portion having a sidewall of a third profile extending axially between a first portion and a second portion, wherein a first angle of the first profile is less than about 1 degree; a second angle of the second profile is less than about 10 degrees and greater than about 1 degree; and a third angle of the third profile is greater than the first angle and less than the second angle.

[0109] In some embodiments, the technology described herein relates to a semiconductor device in which a first axially extending portion has a length greater than about 50 micrometers (μm); a second axially extending portion has a length between about 1 μm and about 5 μm; and a third axially extending portion has a length between about 5 μm and about 10 μm.

[0110] In some cases, the techniques described herein relate to a semiconductor device in which the pitch between at least two of these interconnect structures is less than about 7 μm.

[0111] In some cases, the technology described herein relates to a semiconductor device in which the interconnect structures comprise tungsten, aluminum, or copper; and the second contact pads comprise tungsten or aluminum.

[0112] In some embodiments, the technology described herein relates to a method of manufacturing a semiconductor device, comprising the steps of: forming a first opening in a substrate with sidewalls having a first profile; forming a second opening in the substrate with sidewalls having a second profile, the second profile being shallower than the first profile; forming conductive interconnect structures in the first and second openings; connecting a first end of the conductive interconnect structure to a first conductive contact pad, the first end of the conductive interconnect structure having a first lateral dimension; and connecting a second end of the conductive interconnect structure to a second conductive contact pad, the second end of the conductive interconnect structure having a second lateral dimension smaller than the first lateral dimension, wherein a portion of the conductive interconnect structure formed in the first opening is spaced apart from different conductive elements by a distance less than half the difference between the first and second lateral dimensions.

[0113] In some embodiments, the techniques described herein relate to a method that further includes the steps of: coupling a first conductive contact pad to an image sensor; and coupling a second conductive contact pad to an image signal processor.

[0114] In some embodiments, the techniques described herein relate to a method that further includes the steps of coupling a conductive interconnect structure to one of the metals of a polysilicon gate or transistor that couples an image sensor to an image signal processor.

[0115] In some embodiments, the technology described herein relates to a method comprising a third portion, a sidewall of a third profile extending axially between a first portion having a conductive interconnect structure and a second portion having a conductive interconnect structure, wherein a first angle of the first profile is less than about 1 degree; a second angle of the second profile is less than about 10 degrees and greater than about 1 degree; and a third angle of the third profile is greater than the first angle and less than the second angle.

[0116] In some cases, the technique described herein relates to a method in which the length of a first axially extending portion is greater than about 50 micrometers (μm); the length of a second axially extending portion is between about 1 μm and about 5 μm; and the length of a third axially extending portion is between about 5 μm and about 10 μm.

[0117] In some cases, the techniques described herein involve a method in which the pitch between one conductive interconnect structure and another conductive interconnect structure is less than about 7 μm.

[0118] In some embodiments, the techniques described herein relate to a method in which the conductive interconnect structure comprises tungsten, aluminum, or copper; and the second conductive contact pad comprises tungsten or aluminum.

[0119] In some embodiments, the technology described herein relates to a camera system comprising: a first substrate including a plurality of image sensors; and a second substrate including an image signal processor coupled to the image sensors via a plurality of interconnect structures extending axially between the first and second substrates, the interconnect structures including: an axially extending first portion having a sidewall having a first profile adjacent to the image sensors; and an axially extending second portion having a sidewall having a second profile shallower than the first profile, the first portion adjacent to the image signal processor.

[0120] In some embodiments, the technology described herein relates to a camera system in which interconnect structures extend through a third substrate disposed between a first substrate and a second substrate, the third substrate including a plurality of transistors coupled to the image sensor, the interconnect structures being coupled to the transistors at a first end and to an image signal processor at a second end.

[0121] In some embodiments, the technology described herein relates to a camera system in which these interconnect structures are coupled to contact pads of a second substrate, the bodies of which surround a plurality of via structures coupled to an image signal processor.

[0122] In some embodiments, the technology described herein relates to a semiconductor device comprising a substrate and a conductive interconnect structure. The substrate includes a first conductive contact pad and a second conductive contact pad disposed on a first surface and a second surface, respectively. The conductive interconnect structure is disposed in the substrate. The conductive interconnect structure has a first end having a first lateral dimension and a second end having a second lateral dimension. The first end is connected to the first conductive contact pad, the second end is connected to the second conductive contact pad, and the second lateral dimension is smaller than the first lateral dimension. The conductive interconnect structure has an axially extending first portion adjacent to the second end and an axially extending second portion adjacent to the first end, the first portion having a plurality of sidewalls of a first profile, the second portion having a plurality of sidewalls of a second profile, and the second profile being shallower than the first profile.

[0123] As used herein, the terms “about” and “approximately” generally refer to a given quantity value that can vary depending on the specific technology node associated with the target semiconductor device. Based on a specific technology node, the term “about” can refer to a given quantity value that varies within, for example, 10-30% of that value (e.g., +10%, ±20%, or ±30% of the value).

[0124] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A substrate includes a plurality of first contact pads disposed on a first surface and a plurality of second contact pads disposed on a second surface, the substrate including a plurality of interconnect structures extending between the first surface and the second surface; A first portion extending axially from the plurality of interconnecting structures has a plurality of sidewalls with a first profile; as well as The axially extending second portion of the plurality of interconnected structures has a plurality of sidewalls with a second profile that is shallower than the first profile.

2. The semiconductor device as claimed in claim 1, characterized in that, in: The first surface is disposed in a first metallization layer of the substrate; and The second surface is disposed on a back side of the substrate, and the plurality of second contact pads are coupled to a second metallization layer of a second substrate.

3. The semiconductor device as claimed in claim 2, characterized in that, The second substrate includes an image signal processor, and the first metallization layer of the substrate is coupled to a third metallization layer of a third substrate. The third substrate includes a plurality of image sensors, and the plurality of interconnect structures electrically couple the plurality of image sensors to the image signal processor.

4. The semiconductor device as claimed in claim 2, characterized in that, in: A third contact pad of the second metallization layer is coupled to and laterally surrounds the multiple via structures of the second metallization layer.

5. The semiconductor device as claimed in claim 2, characterized in that, in: A third contact pad of the second metallization layer is coupled to and laterally surrounds a plurality of rectangular through-hole structures of the second metallization layer.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, In the plurality of interconnect structures, a first lateral dimension at a first vertical position of one or more of the interconnect structures is perpendicular to the axial extension of the one or more interconnect structures, exceeding a distance at a second vertical position that limits the distance between the plurality of conductive elements of the one or more interconnect structures, the second vertical position being perpendicularly spaced from the first vertical position.

7. The semiconductor device according to any one of claims 1 to 5, characterized in that, It includes a third portion having a plurality of sidewalls of an axially extending third profile located between the first portion and the second portion, wherein: The first angle of the first profile is less than 1 degree; The second angle of the second profile is less than 10 degrees and greater than 1 degree; and The third angle of the third profile is greater than the first angle and less than the second angle.

8. A semiconductor device, characterized in that, Include: A substrate, comprising a first conductive contact pad and a second conductive contact pad respectively disposed on a first surface and a second surface; and A conductive interconnect structure is disposed in the substrate. The conductive interconnect structure has a first end with a first lateral dimension and a second end with a second lateral dimension. The first end is connected to a first conductive contact pad, and the second end is connected to a second conductive contact pad. The second lateral dimension is smaller than the first lateral dimension. The conductive interconnect structure has an axially extending first portion adjacent to the second end and an axially extending second portion adjacent to the first end. The first portion has a plurality of sidewalls with a first profile, and the second portion has a plurality of sidewalls with a second profile. The second profile is shallower than the first profile.

9. A camera system, characterized in that, Include: A first substrate, comprising multiple image sensors; and A second substrate includes an image signal processor coupled to the plurality of image sensors via a plurality of interconnect structures extending axially between the first substrate and the second substrate, the plurality of interconnect structures comprising: An axially extending first portion having a plurality of sidewalls with a first profile, the first portion being adjacent to the plurality of image sensors; and The axially extending second portion has multiple sidewalls with a second profile that is shallower than the first profile, and the first portion is close to the image signal processor.

10. The camera system as claimed in claim 9, characterized in that, in: The plurality of interconnect structures extend through a third substrate disposed between the first substrate and the second substrate. The third substrate includes a plurality of transistors coupled to the plurality of image sensors. The plurality of interconnect structures are coupled to the plurality of transistors at a first end and to the image signal processor at a second end.

Images