A solar cell, photovoltaic module

Abstract

The application discloses a solar cell and a photovoltaic module. The solar cell comprises a silicon substrate, a back surface of the silicon substrate has first regions and second regions arranged alternately, the second regions are recessed relative to the first regions and form a groove structure, the groove structure comprises a groove bottom surface and groove side surfaces, the groove side surfaces comprise first sub-regions and second sub-regions, the first sub-regions are located on a side close to the groove bottom surface, the second sub-regions are located on a side away from the groove bottom surface, the first sub-regions have a plurality of columnar crystals, after the columnar crystals are sorted according to length values, lengths of columnar crystals located in the middle 80% are between 2 microns and 15 microns, and a standard deviation of the lengths of the columnar crystals located in the middle 80% is less than or equal to 1 micron; a first semiconductor layer is located on the first regions, and a second semiconductor layer is located on the second regions. The application can reduce light escape and improve photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and more particularly to a solar cell and a photovoltaic module. Background Technology

[0002] Solar cells convert solar energy into electrical energy through the photoelectric effect of semiconductor materials, and their photoelectric conversion efficiency directly affects the utilization efficiency of solar energy. In crystalline silicon solar cells, the silicon substrate, as the main light-absorbing region, has a significant impact on light absorption efficiency. However, some incident light tends to escape from the back surface after passing through the silicon substrate, which limits further improvement in the photoelectric conversion efficiency of solar cells. Summary of the Invention

[0003] In order to reduce light escape and improve the photoelectric conversion efficiency of solar cells, this application provides a solar cell and a photovoltaic module.

[0004] In a first aspect, embodiments of this application provide a solar cell.

[0005] A solar cell, comprising:

[0006] A silicon substrate, wherein the backlight surface of the silicon substrate has an alternately arranged first region and a second region, the second region being recessed relative to the first region to form a groove structure, the groove structure including a groove bottom surface and a groove side surface, the groove side surface including a first sub-region, the first sub-region having a plurality of columnar crystals, the columnar crystals being sorted by length value, the length of the columnar crystals located in the middle 80% being between 2μm and 15μm, and the standard deviation of the length of the columnar crystals located in the middle 80% being less than or equal to 1μm;

[0007] A first semiconductor layer is located on the first region, and a second semiconductor layer is located on the second region. One of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

[0008] And / or,

[0009] The N-type semiconductor layer includes a combination of a stacked dielectric layer and an N-type doped polycrystalline silicon layer, a combination of a stacked dielectric layer and an N-type doped amorphous silicon layer, a combination of a stacked dielectric layer and an N-type doped microcrystalline silicon layer, or a combination of a stacked hydrogenated intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer.

[0010] The P-type semiconductor layer includes a combination of a hydrogenated intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer stacked together, a dielectric layer and a P-type doped polycrystalline silicon layer stacked together, a dielectric layer and a P-type doped amorphous silicon layer stacked together, or a dielectric layer and a P-type doped microcrystalline silicon layer stacked together.

[0011] As an optional implementation, in the embodiments of this application, the bottom surface of the groove has a velvety structure;

[0012] The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.

[0013] As an optional implementation, in the embodiments of this application, the density of the columnar crystals in the first sub-region is 10 to 30 crystals per 10,000 nm. 2 .

[0014] As an optional implementation, in an embodiment of this application, the side of the groove further includes a second sub-region, the second sub-region being located on the side away from the bottom surface of the groove, and the first sub-region being located on the side close to the bottom surface of the groove. The second sub-region has a linear texture structure, the length of which is 0.5μm to 2μm.

[0015] As an optional implementation, in the embodiments of this application, the length direction of the columnar crystal is arranged relatively parallel to the length direction of the linear texture structure.

[0016] As an optional implementation, in the embodiments of this application, the top of the columnar crystal has a pyramid structure, and the top of the linear texture structure has a flat structure.

[0017] As an optional implementation, in the embodiments of this application, in the pyramid structure at the top of the columnar crystal, the included angle between any two opposite pyramid sides is 70° to 85°.

[0018] As an optional implementation, in the embodiments of this application, the orthographic projection length of the first sub-region on the silicon substrate is W1, where W1 is 0.2μm to 4μm, and the orthographic projection length of the second sub-region on the silicon substrate is W2, where W2 is 4μm to 15μm.

[0019] As an optional implementation, in an embodiment of this application, the orthographic projection length of the trench side surface onto the silicon substrate is L1, the width of the P-type semiconductor layer is L2, and the width of the N-type semiconductor layer is L3, wherein:

[0020] The ratio of L1 to L2 is 1% to 2%; or the ratio of L1 to L3 is 1.5% to 4%.

[0021] Secondly, embodiments of this application provide a photovoltaic module.

[0022] A photovoltaic module comprising a solar cell as described in the first aspect.

[0023] Compared with the prior art, the beneficial effects of this application are as follows:

[0024] This application provides a solar cell where, when the length of the columnar crystal in the first sub-region of the solar cell is controlled within the range of 2μm to 15μm and its length standard deviation is less than or equal to 1μm, the columnar crystal exhibits characteristics of long dimensions and high uniformity. This structural characteristic can simultaneously enhance the scattering and multiple reflection effects of incident light, effectively suppress light escape from the back surface, and significantly improve the photoelectric response capability of the back surface, thereby effectively improving the photoelectric conversion efficiency and bifaciality of the solar cell. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of the solar cell disclosed in the embodiments of this application;

[0027] Figure 2 for Figure 1 Enlarged structural diagram of section A in the middle;

[0028] Figure 3 This is a schematic diagram illustrating the groove structure disclosed in the embodiments of this application;

[0029] Figure 4 This is a SEM image of the groove side of the groove structure disclosed in the embodiments of this application;

[0030] Figure 5 This is a SEM image of the linear texture structure in the second sub-region disclosed in the embodiments of this application;

[0031] Figure 6 This is a schematic diagram of the included angle of the pyramid structure at the top of a columnar crystal, as disclosed in the embodiments of this application.

[0032] Icons: 1. Silicon substrate; 10. Backlight surface; 1A. First region; 1B. Second region; 11. Groove structure; 111. Groove bottom; 112. Groove side; 1121. First sub-region; 1122. Second sub-region; 113. Textured surface; 2. Columnar crystal; 21. Pyramid structure; 3. Linear texture structure; 31. Flat structure; 4. First semiconductor layer; 41. N-type semiconductor layer; 411. Dielectric layer; 412. N-type doped polycrystalline silicon layer; 5. Second semiconductor layer; 51. P-type semiconductor layer; 511. Hydrogenated intrinsic amorphous silicon layer; 512. P-type doped amorphous silicon layer; 6. Transparent conductive layer; 71. First electrode; 72. Second electrode. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0035] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0036] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0037] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0038] The technical solution of this application will be further described below with reference to the embodiments and accompanying drawings.

[0039] In a first aspect, embodiments of this application provide a solar cell.

[0040] Reference Figures 1-4 A solar cell, comprising:

[0041] A silicon substrate 1 has a backlight surface 10 with alternating first regions 1A and second regions 1B. The second region 1B is recessed relative to the first region 1A to form a groove structure 11. Figure 3 As shown, the groove structure 11 has a connected groove bottom surface 111 and groove side surface 112, and the groove side surface 112 includes a first sub-region 1121. Further integration Figure 4 As shown, the first sub-region 1121 has a number of columnar crystals 2. After the columnar crystals 2 are sorted by length value, the length of the middle 80% of the columnar crystals 2 is between 2μm and 15μm, and the standard deviation of the length of the middle 80% of the columnar crystals 2 is less than or equal to 1μm.

[0042] Reference Figure 1 and Figure 2 The solar cell also includes:

[0043] First semiconductor layer 4, the first semiconductor layer 4 is located on the first region 1A;

[0044] The second semiconductor layer 5 is located on the second region 1B. One of the first semiconductor layer 4 and the second semiconductor layer 5 is an N-type semiconductor layer 41, and the other is a P-type semiconductor layer 51.

[0045] The inventors discovered that when the length of the columnar crystal 2 in the first sub-region 1121 is controlled within the range of 2μm to 15μm, and its length standard deviation is less than or equal to 1μm, the columnar crystal 2 exhibits characteristics of long dimensions and high uniformity. This structural characteristic can simultaneously enhance the scattering and multiple reflection effects of incident light, effectively suppress the light escape phenomenon of the backlight surface 10, and significantly improve the photoelectric response capability of the backlight surface 10, thereby effectively improving the photoelectric conversion efficiency and bifaciality of the solar cell.

[0046] It should be noted that, as Figure 4 As shown, the method for measuring the length of columnar crystal 2 is as follows: In the SEM (scanning electron microscope) image characterizing the structure of the sidewall 112 of the groove, the length is measured along the growth principal axis direction of columnar crystal 2 (i.e., Figure 4 (In the X direction shown), the straight-line distance from the bottom endpoint to the top endpoint of the columnar crystal 2 is measured, where: the bottom endpoint is defined as the contact point between the columnar crystal 2 and the bottom surface 111 of the groove structure 11; the top endpoint is defined as the vertex of the end of the columnar crystal 2 on the side away from the bottom surface 111. For example, the length of the columnar crystal 2 can be 2μm, 5μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, or 15μm, etc.

[0047] The "standard deviation of the length of the middle 80% of columnar crystals 2" mentioned in the embodiments of this application refers to the following: within the first sub-region 1121, all the length measurements of the columnar crystals 2 are sorted from smallest to largest; after removing the shortest and longest 10% of the data, the middle 80% of the crystal lengths are retained as valid samples.

[0048] Let N be the total number of original measurement data, and let the dataset in the valid sample contain M valid data points, i.e., M equals 80% × N. Record these M valid data points sequentially as L1, L2, L3, ..., L... M The length standard deviation σ of this dataset is calculated using the following formula:

[0049]

[0050] Where σ represents the standard deviation of the length to be calculated (unit: μm); L i Let represent the length of the i-th columnar crystal in the set (unit: μm); μ represents the arithmetic mean of the lengths of the "middle 80%" data set (unit: μm), calculated using the following formula: M represents the total number of data points in the "middle 80%" dataset (i.e., the number of valid samples).

[0051] Reference Figure 1 and Figure 3 In some embodiments, the bottom surface 111 of the groove has a velvety structure 113;

[0052] The first semiconductor layer 4 is an N-type semiconductor layer 41, and the second semiconductor layer 5 is a P-type semiconductor layer 51.

[0053] The textured structure 113 of the trench bottom surface 111 can enhance the light scattering effect by extending the transmission path of incident light within the silicon substrate 1, effectively suppressing light escape from the back surface 10, thereby improving the bifaciality of the solar cell. Simultaneously, the N-type semiconductor layer 41 exhibits excellent rate uniformity during chemical etching. When the N-type semiconductor layer 41 serves as the cover layer for the back surface 10 of the silicon substrate 1, the trench side surface 112 and trench bottom surface 111 formed by chemical etching exhibit highly flat morphology. This flat etching interface provides favorable conditions for subsequent texturing, enabling the formation of columnar crystals 2 with a specific morphology in the first sub-region 1121—under the same texturing conditions, the length of the columnar crystals 2 is concentrated in the range of 2μm to 15μm with a length standard deviation less than or equal to 1μm. Comparative experiments show that when the first semiconductor layer 4 is a P-type semiconductor layer 51, the light absorption effect of the resulting first sub-region 1121 is relatively poor. This is because when the chemical etching solution needs to penetrate the P-type semiconductor layer 51, irregular pit defects are more likely to form on the side surface 112 and bottom surface 111 of the groove structure 11. At this time, the length of the columnar crystal 2 in the first sub-region 1121 is shortened and the length distribution dispersion increases, resulting in a decrease in light absorption performance.

[0054] In some embodiments, the density of columnar crystals 2 in the first sub-region 1121 is 10 to 30 per 10,000 nm. 2 .

[0055] The columnar crystal 2 has a high density in the first sub-region 1121, which is conducive to forming multiple light scattering effects, significantly increasing the reflection path length of incident light in the silicon substrate 1, thereby effectively suppressing the light escape phenomenon of the backlight surface 10 and improving the light capture efficiency.

[0056] It should be noted that, during the density measurement of columnar crystal 2, an area of ​​10000 nm was selected in the first sub-region 1121. 2 Within a selected region (e.g., a 100nm × 100nm region), the number of columnar crystals 2 within that region is counted. For example, the density of columnar crystals 2 can be 10 per 10000nm. 2 20 per 10000nm 2 Or 30 per 10000nm 2 wait.

[0057] In some embodiments, reference is made to Figure 4 and Figure 5 As shown, the side surface 112 of the groove also includes a second sub-region 1122, which is located on the side away from the bottom surface 111 of the groove, while the first sub-region 1121 is located on the side closer to the bottom surface 111 of the groove. The second sub-region 1122 has a linear texture structure 3, which is specifically as follows: Figure 5As shown in the red box, the length of the linear texture structure 3 is 0.5μm to 2μm.

[0058] The length of the linear texture structure 3 in the second sub-region 1122 is controlled within the range of 0.5μm to 2μm, which is significantly shorter than the length of the columnar crystal 2 in the first sub-region 1121 (2μm to 15μm). It can optimize the absorption effect of light of different wavelengths by forming a gradient scattering structure with the first sub-region 1121: short-wavelength light (such as 300nm to 600nm) is captured in the second sub-region 1122, while long-wavelength light (such as 700nm to 1100nm) is captured in the first sub-region 1121, thereby improving the absorption rate of light across the entire wavelength range.

[0059] It should be noted that the length of the linear texture structure 3 is measured as follows: Figure 4 In the SEM (scanning electron microscope) image shown, along the growth direction of the linear texture structure 3 (e.g.) Figure 4 (In the X direction shown), the straight-line distance from the bottom endpoint to the top endpoint of the linear texture structure 3 is measured, where: the bottom endpoint is defined as the contact point between the linear texture structure 3 and the columnar crystal 2; the top endpoint is defined as the vertex of the end of the linear texture structure 3 away from the columnar crystal 2. For example, the length of the linear texture structure 3 can be 0.5 μm, 0.8 μm, 1.2 μm, 1.6 μm, or 2 μm, etc.

[0060] In some embodiments, the length direction of the columnar crystal 2 is relatively parallel to the length direction of the linear texture structure 3.

[0061] The columnar crystal 2 and the linear texture structure 3 are parallel in length direction, which can form a cooperative directional scattering structure, guide the incident light to be reflected in a specific direction, reduce the loss caused by random light scattering, and improve the light absorption and utilization effect.

[0062] It should be noted that the length direction of columnar crystal 2 is the same as the growth axis direction of columnar crystal 2 mentioned above, and the length direction of linear texture structure 3 is the growth direction of linear texture structure 3.

[0063] In some embodiments, the columnar crystal 2 has a pyramidal structure 21 at the top, and the linear textured structure 3 has a flat structure 31 at the top.

[0064] The pyramid structure 21 at the top of the columnar crystal 2 reduces the reflectivity of incident light through multiple internal reflections, significantly enhancing the light-harvesting capability of the first sub-region 1121. Simultaneously, the flat structure 31 at the top of the linear textured structure 3, with its lower surface roughness, better improves the surface contact effect of the second sub-region 1122 and the quality of the film deposited on its surface, reducing carrier recombination. Through the synergy of these two morphologies, the photoelectric conversion efficiency of the solar cell is improved.

[0065] It should be noted that, unlike the undulating pyramid-shaped velvet surface 113, the flat structure 31 is a relatively flat, continuous flat structure without abrupt changes in height.

[0066] Reference Figure 6 In some embodiments, in the pyramid structure 21 at the top of the columnar crystal 2, the included angle α between the two opposite sides of any opposite pyramid structure 21 is 70° to 85°.

[0067] When the angle α between the two opposite sides of the pyramid structure 21 at the top of the columnar crystal 2 is controlled within the range of 70° to 85°, the reflection angle of the incident light on the sides of the pyramid is increased by optimizing the multiple reflection paths of the light, thereby maintaining the total internal reflection effect until the light energy is fully absorbed. For example, the angle α can be 70°, 75°, 80°, or 85°, etc.

[0068] It should be noted that, as Figure 6 As shown, during the measurement of the included angle α, two opposite sides of the pyramid structure 21 are selected, namely the first pyramid side and the second pyramid side. A perpendicular line a is drawn from the top of the pyramid to the bottom edge of the first pyramid side, and a perpendicular line b is drawn from the top of the pyramid to the bottom edge of the second pyramid side. The angle formed by the intersection of the perpendicular lines a and b is the size of the included angle α.

[0069] Reference Figure 3 The depth H of the groove structure 11 is 2 μm to 12 μm. This depth of the groove structure 11 can better reduce the possibility of contact between the first semiconductor layer 4 and the second semiconductor layer 5. During measurement, the depth of the groove structure 11 is the distance between the bottom of the textured structure 113 of the groove bottom surface 111 and the surface of the silicon substrate 1 without the groove structure 11. For example, the depth H of the groove structure 11 can be 2 μm, 5 μm, 7 μm, 9 μm, or 12 μm, etc.

[0070] Reference Figure 3 In some embodiments, the orthographic projection length of the first sub-region 1121 on the silicon substrate 1 is W1, where W1 is 0.2 μm to 4 μm, and the orthographic projection length of the second sub-region 1122 on the silicon substrate 1 is W2, where W2 is 4 μm to 15 μm.

[0071] This application differentiates the projected lengths of the first sub-region 1121 and the second sub-region 1122 to synergistically enhance the light absorption capacity and structural stability of the battery. Specifically, the first sub-region 1121 corresponds to the main region of the columnar crystal 2 structure, and its projected length W1 is 0.2μm to 4μm. The longer dimension helps to extend the propagation path of light inside the columnar crystal 2, reducing the probability of light escape and thus improving the light absorption and utilization rate. The second sub-region 1122 is located at the edge of the groove structure 11 and corresponds to the main region of the linear texture structure 3 structure. Its projected length W2 is controlled within a relatively short range of 4μm to 15μm, which can reduce light loss at the edge while ensuring the mechanical strength of the groove structure 11, thus balancing optical performance and structural reliability. For example, W1 can be 0.2μm, 1μm, 2μm, 3μm, or 4μm, and W2 can be 4μm, 7μm, 10μm, 13μm, or 15μm, etc.

[0072] In some embodiments, reference is made to the return Figure 1 The length of the orthogonal projection of the trench side 112 onto the silicon substrate 1 is L1, the width of the P-type semiconductor layer 51 is L2, and the width of the N-type semiconductor layer 41 is L3, wherein: the ratio of L1 to L2 is 1% to 2%; or the ratio of L1 to L3 is 1.5% to 4%.

[0073] By controlling the ratio of L1 in the sidewall 112 to L2 in the P-type semiconductor layer 51, or by controlling the ratio of L1 in the sidewall 112 to L3 in the N-type semiconductor layer 41, it is beneficial to balance the light absorption capacity and the carrier transport effect. For example, the ratio of L1 to L2 can be 1%, 1.5%, or 2%, etc.; the ratio of L1 to L3 can be 1.5%, 2%, 3%, or 4%, etc.

[0074] Furthermore, when the P-type semiconductor layer 51 is disposed in the second region 1B, the width L3 of the N-type semiconductor layer 41 is 250μm to 400μm, and the width L2 of the P-type semiconductor layer 51 is 400μm to 600μm. Setting the widths of the P-type semiconductor layer 51 and the N-type semiconductor layer 41 within these ranges is beneficial for achieving better carrier transport performance and improving the performance of the solar cell. In addition, the P-type semiconductor layer 51 is deposited on the bottom surface 111 of the trench structure 11, and the width of the bottom surface 111 is positively correlated with the width of the P-type semiconductor layer 51. Therefore, this width setting of the P-type semiconductor layer 51 is beneficial for achieving a better width-to-depth ratio (2μm to 12μm) of the bottom surface 111 of the trench structure 11, which facilitates uniform flow of the etching solution within the trench structure 11 during etching, avoiding etching dead zones caused by excessive narrowness. The width of the N-type semiconductor layer 41 can be 250μm, 300μm, 350μm or 400μm, and the width of the P-type semiconductor layer 51 can be 400μm, 450μm, 500μm, 550μm or 600μm, etc.

[0075] In some embodiments, the N-type semiconductor layer 41 includes a combination of a stacked dielectric layer 411 and an N-type doped polycrystalline silicon layer 412, a combination of a stacked dielectric layer 411 and an N-type doped amorphous silicon layer, a combination of a stacked dielectric layer 411 and an N-type doped microcrystalline silicon layer, or a combination of a stacked hydrogenated intrinsic amorphous silicon layer 511 and an N-type doped amorphous silicon layer.

[0076] The P-type semiconductor layer 51 includes a combination of a hydrogenated intrinsic amorphous silicon layer 511 and a P-type doped amorphous silicon layer 512 stacked together, a combination of a dielectric layer 411 and a P-type doped polycrystalline silicon layer stacked together, a dielectric layer 411 and a P-type doped amorphous silicon layer stacked together, or a dielectric layer 411 and a P-type doped microcrystalline silicon layer stacked together.

[0077] This application sets the N-type semiconductor layer 41 and the P-type semiconductor layer 51 into multiple independently selectable combinations, allowing the battery structure to flexibly match different design requirements. Preferably, the N-type semiconductor layer 41 is a combination of a stacked dielectric layer 411 and an N-type doped polycrystalline silicon layer 412, and the P-type semiconductor layer 51 is a combination of a stacked hydrogenated intrinsic amorphous silicon layer 511 and a P-type doped amorphous silicon layer 512. This structure combines the high carrier selectivity of the passivated contact structure with the excellent passivation characteristics of the heterojunction structure. The complementary advantages of the two technologies can significantly improve the photoelectric conversion efficiency of the solar cell.

[0078] It should be noted that the material of the dielectric layer 411 can include a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the dielectric layer 411 can be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, which can minimize the recombination loss of minority carriers on the surface of the silicon substrate 1. To better provide interface passivation for the silicon substrate 1, the thickness of the dielectric layer 411 can be from 0.1 nm to 5 nm. For example, the thickness of the dielectric layer 411 can be 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, etc. However, the present invention is not limited to these values, and the thickness of the dielectric layer 411 can have various values.

[0079] In some embodiments, a transparent conductive layer 6 is provided on the surface of both the N-type semiconductor layer 41 and the P-type semiconductor layer 51;

[0080] The solar cell also includes a first electrode 71 and a second electrode 72. The first electrode 71 forms an ohmic contact with the transparent conductive layer 6 located on the surface of the N-type semiconductor layer 41, and the second electrode 72 forms an ohmic contact with the transparent conductive layer 6 located on the surface of the P-type semiconductor layer 51.

[0081] Secondly, embodiments of this application provide a photovoltaic module.

[0082] A photovoltaic module, comprising solar cells as mentioned in the first aspect.

[0083] The structure of a solar cell will be further explained below in conjunction with the fabrication method of the solar cell.

[0084] A method for fabricating a solar cell includes the following steps:

[0085] The N-type monocrystalline silicon wafer is cleaned to remove lines, damage, dirt, particles, etc. from its surface.

[0086] A SiO2 dielectric layer with a thickness of 1 nm to 2 nm is deposited on the back surface of an N-type single-crystal silicon wafer using LPCVD (low-pressure chemical vapor deposition).

[0087] An N-type doped polycrystalline silicon layer and a phosphosilicate glass layer were prepared on the back surface of an N-type single-crystal silicon wafer using LPCVD.

[0088] A horizontal chain cleaning machine is used to remove the phosphor-silicon glass layer coated on one side of the light-receiving surface.

[0089] A silicon nitride mask is deposited on the back surface of an N-type monocrystalline silicon wafer, and the silicon nitride mask stack is disposed on the side of the phosphosilicate glass layer away from the N-type monocrystalline silicon wafer.

[0090] Laser patterning was used to remove part of the silicon nitride mask and phosphosilicate glass layer;

[0091] Next, alkaline polishing is performed to form a groove structure in the N-type monocrystalline silicon wafer. Through texturing, a textured surface structure is formed on the light-receiving surface of the N-type monocrystalline silicon wafer and the bottom and part of the side surfaces of the groove structure. Afterwards, a cleaning process is performed to remove the texturing additives and other impurities on the N-type monocrystalline silicon wafer.

[0092] An alumina layer is deposited on the light-receiving surface using atomic layer deposition.

[0093] A silicon nitride layer is deposited on the light-receiving side using PECVD (plasma-enhanced chemical vapor deposition) for anti-reflection and hydrogen passivation.

[0094] A horizontal chain machine is used to remove the aluminum oxide layer and silicon nitride layer coated around the backlight surface;

[0095] A hydrogenated intrinsic amorphous silicon layer (ia-Si:H) is deposited on the backlight surface using PECVD.

[0096] A P-type doped amorphous silicon layer with a doping concentration of 5×10⁻⁶ was deposited on the backlight surface using PECVD. 19 cm -3 The thickness of the deposited film is 2nm to 15nm, and the ratio of the thickness of the hydrogenated intrinsic amorphous silicon layer to the thickness of the doped amorphous silicon layer is 1:(1.4 to 1.8).

[0097] Laser removal is used to remove the P-type doped amorphous silicon layer and the hydrogenated intrinsic amorphous silicon layer located above the N-type doped polycrystalline silicon layer. Then, wet cleaning is performed to form a columnar crystal structure in the first sub-region on the side of the groove structure and a linear texture structure in the second sub-region.

[0098] A transparent conductive layer of ITO (indium tin oxide) is deposited on the backlight surface using PVD (physical vapor deposition), with the film thickness controlled between 50 nm and 100 nm.

[0099] A first electrode and a second electrode are prepared by screen printing, wherein the first electrode is in contact with an ITO transparent conductive layer on the surface of an N-type doped polysilicon layer, and the second electrode is in contact with an ITO transparent conductive layer on the surface of a P-type doped polysilicon layer. The gate line width of the first electrode and the second electrode is 5 μm to 15 μm, and the height is 8 μm to 20 μm.

[0100] The technical solutions disclosed in the embodiments of this application have been described in detail above. Specific examples have been used in this article to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core inventive points of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A solar cell, characterized in that, include: A silicon substrate, wherein the backlight surface of the silicon substrate has an alternately arranged first region and a second region, the second region being recessed relative to the first region to form a groove structure, the groove structure including a groove bottom surface and a groove side surface, the groove side surface including a first sub-region, the first sub-region having a plurality of columnar crystals, the columnar crystals being sorted by length value, the length of the columnar crystals located in the middle 80% being between 2μm and 15μm, and the standard deviation of the length of the columnar crystals located in the middle 80% being less than or equal to 1μm; A first semiconductor layer is located on the first region; The second semiconductor layer is located on the second region, wherein one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer and the other is a P-type semiconductor layer.

2. The solar cell according to claim 1, characterized in that, The bottom surface of the groove has a velvety structure; The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer; And / or, The N-type semiconductor layer includes a combination of a dielectric layer and an N-type doped polycrystalline silicon layer stacked together, or a combination of a hydrogenated intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer stacked together. The P-type semiconductor layer includes a combination of a hydrogenated intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer stacked together, or a dielectric layer and a P-type doped polycrystalline silicon layer stacked together.

3. The solar cell according to claim 1, characterized in that, In the first sub-region, the density of the columnar crystals is 10–30 per 10,000 nm. 2 .

4. The solar cell according to claim 3, characterized in that, The side of the groove also includes a second sub-region, which is located on the side away from the bottom surface of the groove, while the first sub-region is located on the side close to the bottom surface of the groove. The second sub-region has a linear texture structure with a length of 0.5 μm to 2 μm.

5. The solar cell according to claim 4, characterized in that, The length direction of the columnar crystal is parallel to the length direction of the linear texture structure.

6. The solar cell according to claim 4, characterized in that, The columnar crystal has a pyramidal structure at the top, while the linear texture structure has a flat top.

7. The solar cell according to claim 6, characterized in that, In the pyramid structure at the top of the columnar crystal, the included angle between any two opposite sides of the pyramid is 70° to 85°.

8. The solar cell according to claim 4, characterized in that, The first sub-region has a projected length of W1 on the silicon substrate, which is 0.2 μm to 4 μm. The second sub-region has a projected length of W2 on the silicon substrate, which is 4 μm to 15 μm.

9. The solar cell according to claim 1, characterized in that, The length of the orthographic projection of the trench side onto the silicon substrate is L1, the width of the P-type semiconductor layer is L2, and the width of the N-type semiconductor layer is L3, wherein: The ratio of L1 to L2 is 1% to 2%; or the ratio of L1 to L3 is 1.5% to 4%.

10. A photovoltaic module, characterized in that, Includes the solar cell as described in any one of claims 1-9.

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