A solar cell and photovoltaic module

Abstract

The application relates to the technical field of solar cells, and specifically discloses a solar cell and a photovoltaic module, the solar cell comprising a silicon substrate, the silicon substrate having a front surface and a back surface arranged oppositely; the back surface of the silicon substrate is provided with P-type doped layers and N-type doped layers in an interdigital alternating mode, the back surface of the silicon substrate comprises a first subregion corresponding to the P-type doped layers and a second subregion corresponding to the N-type doped layers, and a first roughness of the first subregion is smaller than a second roughness of the second subregion. The application can better improve the utilization efficiency and passivation performance of the back surface of the solar cell to the light, and further improve the photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] This application relates to the technical field of solar cells, and more particularly to a solar cell and a photovoltaic module. Background Technology

[0002] By transferring structures such as electrode grids from the front side of a solar cell to the back side, the shading of the front grids can be eliminated, improving the light absorption efficiency of the solar cell. However, the back side of the solar cell has poor light utilization efficiency and passivation effect, limiting further improvements in solar cell performance. Utility Model Content

[0003] In order to better improve the light utilization efficiency and passivation performance of the back side of the solar cell, so as to further improve the photoelectric conversion efficiency of the solar cell, this application discloses a solar cell and a photovoltaic module.

[0004] In a first aspect, embodiments of this application provide a solar cell.

[0005] A solar cell includes a silicon substrate having a front side and a back side disposed opposite to each other. The back side of the silicon substrate is stacked with alternating P-type doped layers and N-type doped layers in an interdigitated pattern. The back side of the silicon substrate includes a first sub-region corresponding to the P-type doped layer and a second sub-region corresponding to the N-type doped layer. The first roughness of the first sub-region is less than the second roughness of the second sub-region.

[0006] As an optional implementation, in the embodiments of this application, the first roughness is 2 nm to 20 nm, and / or the second roughness is 21 nm to 50 nm.

[0007] As an optional implementation, in the embodiments of this application, the surface relative height difference of the first sub-region is 15 nm to 100 nm, and the surface relative height difference of the second sub-region is greater than 100 nm.

[0008] As an optional implementation, in the embodiments of this application, the surface of the first sub-region has a plurality of first tower bases, the surface of the second sub-region has a plurality of second tower bases, and the tower base size of the second tower base is larger than the tower base size of the first tower base.

[0009] As an optional implementation, in the embodiments of this application, the tower base size of the first tower base is 10μm~20μm, and the tower base size of the second tower base is 18μm~40μm.

[0010] As an optional implementation, in the embodiments of this application, the first tower base surface is a flat structure, and the second tower base surface has a plurality of protruding structures.

[0011] As an optional implementation, in the embodiments of this application, the P-type doped layer includes a P-type doped polysilicon layer, and the N-type doped layer includes an N-type doped polysilicon layer; A first dielectric layer is disposed between the silicon substrate and the P-type doped layer, and a second dielectric layer is disposed between the silicon substrate and the N-type doped layer.

[0012] As an optional implementation, in an embodiment of this application, the solar cell further includes: A positive passivation layer and / or a back passivation layer, wherein the positive passivation layer covers the front side of the silicon substrate, and the back passivation layer covers the side of the P-type doped layer opposite to the silicon substrate and the side of the N-type doped layer opposite to the silicon substrate; A first electrode and a second electrode, wherein the first electrode passes through the back passivation layer to form an ohmic contact with the P-type doped layer, and the second electrode passes through the back passivation layer to form an ohmic contact with the N-type doped layer.

[0013] As an optional implementation, in the embodiments of this application, the positive passivation layer includes a positive alumina layer and a positive silicon nitride layer stacked together, wherein the positive alumina layer is located on the side close to the silicon substrate, and the positive silicon nitride layer is located on the side of the positive alumina layer away from the silicon substrate; The back passivation layer includes a back alumina layer and a back silicon nitride layer stacked together, wherein the back alumina layer is located on the side close to the silicon substrate, and the back silicon nitride layer is located on the side of the back alumina layer away from the silicon substrate.

[0014] Secondly, embodiments of this application provide a photovoltaic module.

[0015] A photovoltaic module comprising a solar cell as described in the first aspect.

[0016] Compared with the prior art, the beneficial effects of this application are as follows: This application employs differentiated roughness treatment on different regions of the back side of a silicon substrate, allowing the P-type and N-type doped layers to correspond to first and second sub-regions with varying roughness, respectively. This structural design improves the contact quality between the P-type doped layer and the silicon substrate, enhancing interface compatibility and thus increasing the carrier extraction capability of the P-type doped layer and strengthening passivation. Simultaneously, the N-type doped layer, positioned in the higher roughness region, maintains good electrical performance and contributes to enhanced absorption and utilization of incident light on the back side. This structure, while maintaining good passivation, effectively increases the bifaciality of the solar cell, thereby maximizing overall photoelectric conversion performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of the solar cell disclosed in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the silicon substrate disclosed in the embodiments of this application; Figure 3 This is a graph obtained by detecting the relative height difference of the surface of the first sub-region using a Zeta 3D microscope, as disclosed in the embodiments of this application. Figure 4 This is a diagram illustrating the morphology of the first and second sub-regions under a Zeta 3D microscope, as disclosed in an embodiment of this application. Figure 5 This is a diagram illustrating the morphology of the first and second tower bases under a Zeta 3D microscope, as disclosed in the embodiments of this application.

[0019] Icons: 1. Silicon substrate; 11. Front side; 12. Back side; 121. First sub-region; 122. Second sub-region; 21. P-type doped layer; 211. P-type doped polysilicon layer; 22. N-type doped layer; 221. N-type doped polysilicon layer; 31. First tower base; 32. Second tower base; 41. First dielectric layer; 42. Second dielectric layer; 51. Positive passivation layer; 511. Positive alumina layer; 512. Positive silicon nitride layer; 52. Back passivation layer; 521. Back alumina layer; 522. Back silicon nitride layer; 61. First electrode; 62. Second electrode. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0022] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0023] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0024] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0025] The technical solution of this application will be further described below with reference to the embodiments and accompanying drawings.

[0026] In a first aspect, embodiments of this application provide a solar cell.

[0027] Reference Figure 1 and Figure 2 A solar cell includes a silicon substrate 1, the structure of which is as follows: Figure 2 As shown, a front side 11 and a back side 12 are arranged opposite to each other. The back side 12 of the silicon substrate 1 is stacked with an interdigitated P-type doped layer 21 and an N-type doped layer 22. The back side 12 of the silicon substrate 1 includes a first sub-region 121 corresponding to the P-type doped layer 21 and a second sub-region 122 corresponding to the N-type doped layer 22. The first roughness of the first sub-region 121 is less than the second roughness of the second sub-region 122.

[0028] This application employs differentiated roughness treatment on different regions of the back surface 12 of the silicon substrate 1, so that the P-type doped layer 21 and the N-type doped layer 22 correspond to the first sub-region 121 and the second sub-region 122 with different roughnesses, respectively. This structural design improves the contact quality between the P-type doped layer 21 and the silicon substrate 1, enhances interface matching, thereby increasing the carrier extraction capability of the P-type doped layer 21 and strengthening the passivation effect. Simultaneously, the N-type doped layer 22, located in the region with higher roughness, maintains good electrical performance and helps enhance the absorption and utilization of incident light by the back surface 12. This structure, while maintaining good passivation, effectively improves the bifaciality of the solar cell, thereby maximizing the overall photoelectric conversion performance.

[0029] It should be noted that the first roughness is the surface roughness of the first sub-region 121, and the second roughness is the surface roughness of the second sub-region 122.

[0030] In some embodiments, the first roughness is 2 nm to 20 nm, and / or the second roughness is 21 nm to 50 nm.

[0031] By controlling the first roughness and the second roughness within the aforementioned specific ranges, both the deposition quality and carrier extraction capability of the P-type doped layer 21 can be guaranteed, while the light absorption effect of the second sub-region 122 can be enhanced, thereby optimizing the overall performance of the solar cell. For example, the first roughness can be 2 nm, 5 nm, 10 nm, 15 nm, or 20 nm, etc., and the second roughness can be 21 nm, 33 nm, 42 nm, or 50 nm, etc.

[0032] In some embodiments, the relative height difference of the surface of the first sub-region 121 is 15 nm to 100 nm, and the relative height difference of the surface of the second sub-region 122 is greater than 100 nm.

[0033] Controlling the relative height difference of the surface of the first sub-region 121 within the range of 15-100 nm helps maintain the surface flatness of the first sub-region 121, thereby reducing contact resistance and carrier recombination. A relative height difference of the surface of the second sub-region 122 greater than 100 nm further enhances its surface light scattering capability, causing incident light to undergo multiple reflections on the back surface 12, extending the optical path, increasing the light absorption probability, and significantly improving the bifaciality and overall efficiency of the battery. For example, the relative height difference of the surface of the first sub-region 121 can be 15 nm, 25 nm, 45 nm, 75 nm, or 100 nm, and the relative height difference of the surface of the second sub-region 122 can be 110 nm, 150 nm, 180 nm, 220 nm, or 280 nm, etc.

[0034] It should be noted that the relative height difference of the surface is the vertical distance between the highest and lowest points within the specified detection area. For example, by using a Zeta 3D microscope to test the first roughness of the first sub-region 121, the following can be obtained: Figure 3 The graph shown (unit: μm) is obtained by selecting and calculating this... Figure 3 The highest point of the wave shown (at) Figure 3 Marked as B) and the lowest point of the wave crest (in Figure 3 The difference in the vertical coordinates, labeled A), is the relative height difference of the surface of the first sub-region 121.

[0035] Reference Figure 4 In some embodiments, the surface of the first sub-region 121 has a plurality of first tower bases 31, and the surface of the second sub-region 122 has a plurality of second tower bases 32, wherein the tower base size of the second tower base 32 is larger than the tower base size of the first tower base 31.

[0036] Furthermore, such as Figure 4 As shown, the boundary between the first sub-region 121 and the second sub-region 122 is clear. The smaller first bases 31 are all distributed in the first sub-region 121, while the larger second bases 32 are all distributed in the second sub-region 122. The larger base size of the second bases 32 makes it easier to obtain a surface with high roughness, thus increasing the roughness of the second sub-region 122. Conversely, the smaller base size of the first bases 31 makes it easier to obtain a surface with low roughness, thus reducing the roughness of the first sub-region 121. By controlling the base size and morphology, the surface roughness of the first sub-region 121 and the second sub-region 122 can be controlled, better balancing the requirements for improving the deposition quality of the P-type doped layer 21 and improving light absorption, thereby maximizing the performance of the solar cell.

[0037] It should be noted that, as Figure 4 As shown, the top of the tower base structure is a rhomboid or near-rhomboid structure. In this application, the tower base dimensions of the first tower base 31 and the second tower base 32 refer to the side length of any side of the top of the tower base structure.

[0038] In some embodiments, the tower base 31 has a tower base size of 10 μm to 20 μm, and the tower base 32 has a tower base size of 18 μm to 40 μm.

[0039] The small base size of the first sub-region 121 facilitates the uniform deposition of the P-type doped layer 21 and the formation of a low-defect interface; the large base size of the second sub-region 122 enhances the light scattering effect and improves the backlight capturing capability. This morphologically differentiated design achieves a synergistic improvement in both electrical and optical performance.

[0040] For example, the base size of the first tower base 31 can be 10 μm, 13 μm, 17 μm or 20 μm, etc., and the base size of the second tower base 32 can be 18 μm, 28 μm, 35 μm or 40 μm, etc.

[0041] Reference Figure 5 In some embodiments, the surface of the first tower base 31 is a flat structure, and the surface of the second tower base 32 has several protruding structures.

[0042] The flat structure of the first base 31 can better meet the low roughness requirement of the P-type doped layer 21 and reduce the interface state density; the raised structure of the second base 32 enhances the light scattering ability and improves the light absorption efficiency of the back side 12.

[0043] It should be noted that, unlike the surface of the second tower base 32 which has several protruding structures, the flat structure of the surface of the first tower base 31 is a relatively flat, continuous flat structure without abrupt changes in height.

[0044] Refer to the return Figure 1 In some embodiments, the P-type doped layer 21 includes a P-type doped polysilicon layer 211, and the N-type doped layer 22 includes an N-type doped polysilicon layer 221. A first dielectric layer 41 is disposed between the silicon substrate 1 and the P-type doped layer 21, and a second dielectric layer 42 is disposed between the silicon substrate 1 and the N-type doped layer 22.

[0045] The combination of the P-type doped polysilicon layer 211 with the first dielectric layer 41 and the N-type doped polysilicon layer 221 with the second dielectric layer 42 can effectively suppress carrier recombination and improve the interface passivation effect.

[0046] The materials of the first dielectric layer 41 and the second dielectric layer 42 may include a variety of dielectric materials, such as at least one selected from silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. To better provide interface passivation for the substrate, the thickness of the first dielectric layer 41 and the second dielectric layer 42 may be 0.5 nm to 3 nm. For example, the thickness of the first dielectric layer 41 and the second dielectric layer 42 may be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 3 nm, etc.; however, this application is not limited to these values, and the thickness of the first dielectric layer 41 and the second dielectric layer 42 may have various values.

[0047] Reference Figure 1 In some embodiments, the solar cell further includes: A positive passivation layer 51 and / or a back passivation layer 52, wherein the positive passivation layer 51 covers the front side 11 of the silicon substrate 1, and the back passivation layer 52 covers the side of the P-type doped layer 21 away from the silicon substrate 1 and the side of the N-type doped layer 22 away from the silicon substrate 1. The first electrode 61 and the second electrode 62 are connected. The first electrode 61 passes through the back passivation layer 52 and forms an ohmic contact with the P-type doped layer 21. The second electrode 62 passes through the back passivation layer 52 and forms an ohmic contact with the N-type doped layer 22.

[0048] The presence of the positive passivation layer 51 and the back passivation layer 52 can more comprehensively suppress surface recombination and improve battery efficiency. The back passivation layer 52 covers the surfaces of the P-type doped layer 21 and the N-type doped layer 22, effectively reducing carrier recombination, promoting efficient carrier extraction, and ultimately achieving efficient photoelectric conversion.

[0049] Reference Figure 1 In some embodiments, the positive passivation layer 51 includes a positive alumina layer 511 and a positive silicon nitride layer 512 stacked together, wherein the positive alumina layer 511 is located on the side close to the silicon substrate 1, and the positive silicon nitride layer 512 is located on the side of the positive alumina layer 511 away from the silicon substrate 1. The back passivation layer 52 includes a back alumina layer 521 and a back silicon nitride layer 522 stacked together, wherein the back alumina layer 521 is located on the side close to the silicon substrate 1, and the back silicon nitride layer 522 is located on the side of the back alumina layer 521 away from the silicon substrate 1.

[0050] The stacked structure of aluminum oxide and silicon nitride layers can synergistically improve the passivation effect and optical performance of the battery.

[0051] Secondly, embodiments of this application provide a photovoltaic module.

[0052] A photovoltaic module, comprising solar cells as mentioned in the first aspect.

[0053] The structure of a solar cell will be further explained below in conjunction with the fabrication method of the solar cell.

[0054] A method for fabricating a solar cell includes the following steps: The N-type single crystal silicon wafer is polished for the first time. The first polishing alkali solution for the first polishing contains a first polishing additive. The first polishing additive destroys the selective corrosion of the (111) crystal plane, making the corrosion rates of the (100) crystal plane and the (111) crystal plane tend to be consistent, thereby changing the surface chemical reaction path, inhibiting pyramid nucleation and growth, enhancing uniform corrosion, inhibiting anisotropic corrosion, and promoting planarization. The alkali in the first polishing alkali solution can be NaOH and / or KOH. The main components of the first polishing additive can be carboxymethyl cellulose, defoaming agent, antioxidant, sodium gluconate, accelerator and brightener, etc. The first polishing additive can be obtained commercially. After the first polishing process, the wafer is rinsed and dried with deionized water to remove any residual first polishing additives or impurities. This controls the roughness of the back surface of the N-type single-crystal silicon wafer to 2 nm–20 nm and the relative height difference to 15 nm–100 nm, resulting in the desired surface roughness. Figure 4 The structure of the first sub-region shown; On the back side of an N-type single-crystal silicon wafer, a first SiO2 dielectric layer with a thickness of 0.5 nm to 3 nm, a P-type doped polycrystalline silicon layer with a thickness of 100 nm to 300 nm, and a first doped silicon oxide mask layer with a thickness of 50 nm to 70 nm are sequentially stacked. A portion of the first doped silicon oxide mask layer on one side of the backlight is removed by a first laser patterning process, wherein the depth of the laser patterning process is greater than or equal to the thickness of the first doped silicon oxide mask layer. A second polishing process is performed, using a polishing alkali solution to etch the area below the first laser patterned region down to the silicon substrate surface. Areas not treated with the first laser pattern are protected by a first doped silicon oxide mask layer and are less susceptible to erosion by the polishing alkali solution. Unlike the first polishing process, the second polishing process can accelerate the etching rate by appropriately increasing the reaction temperature and / or the concentration of the second polishing alkali solution, thereby increasing the surface roughness of the silicon substrate. The alkali in the second polishing alkali solution can be NaOH and / or KOH. A second polishing additive can also be added during the second polishing process. The main components of the second polishing additive can be sodium gluconate, accelerators, brighteners, etc., and the second polishing additive can also be commercially available. After the second polishing process, the wafer undergoes a series of steps including alkaline washing, water washing, acid washing, water washing, and drying to remove any residual second polishing additives or impurities. This controls the roughness of the back surface of the N-type single-crystal silicon wafer to be between 21 nm and 50 nm, with a relative height difference greater than 100 nm, resulting in the desired surface texture. Figure 4 The structure of the second sub-region is shown; On the back side of an N-type single-crystal silicon wafer, a second SiO2 dielectric layer with a thickness of 0.5 nm to 3 nm, an N-type doped polycrystalline silicon layer with a thickness of 100 nm to 300 nm, and a second doped silicon oxide mask layer with a thickness of 20 nm to 60 nm are sequentially stacked and prepared by LPCVD. The second laser patterning process is used to create a second doped silicon oxide mask layer above the P-type doped polysilicon layer and a second doped silicon oxide mask layer near the P-type doped polysilicon layer. The texturing process involves single-sided acid polishing on the front side of the silicon substrate to remove the coating layer. Then, the texturing alkaline solution is used to etch the surface, forming a pyramidal texture on the front side of the silicon substrate. The remaining N-type doped polysilicon layer and the second SiO2 dielectric layer below the second laser patterning area on the back side of the silicon substrate are removed by the texturing alkaline solution. The non-second laser patterning area is protected by the second doped silicon oxide mask layer and is not easily etched by the texturing alkaline solution. Acid washing is performed to remove the remaining first and second doped silicon oxide mask layers, followed by water washing and drying. Plasma chemical vapor deposition (PECVD) is used to deposit a positive alumina layer and a back alumina layer on the front and back sides of a silicon substrate, respectively. Then, a positive silicon nitride layer is deposited on the positive alumina layer and a back silicon nitride layer is deposited on the back alumina layer to complete the preparation of the positive passivation layer and the back passivation layer. The first electrode and the second electrode are prepared by screen printing, so that the first electrode passes through the back passivation layer and forms an ohmic contact with the P-type doped layer, and the second electrode passes through the back passivation layer and forms an ohmic contact with the N-type doped layer.

[0055] The technical solutions disclosed in the embodiments of this application have been described in detail above. Specific examples have been used in this article to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core utility model points of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A solar cell, characterized in that, The device includes a silicon substrate having a front side and a back side disposed opposite to each other. The back side of the silicon substrate is stacked with alternating P-type doped layers and N-type doped layers in an interdigitated pattern. The back side of the silicon substrate includes a first sub-region corresponding to the P-type doped layer and a second sub-region corresponding to the N-type doped layer. The first roughness of the first sub-region is less than the second roughness of the second sub-region.

2. The solar cell according to claim 1, characterized in that, The first roughness is 2 nm to 20 nm, and / or the second roughness is 21 nm to 50 nm.

3. The solar cell according to claim 2, characterized in that, The surface relative height difference of the first sub-region is 15 nm to 100 nm, and the surface relative height difference of the second sub-region is greater than 100 nm.

4. The solar cell according to claim 1, characterized in that, The surface of the first sub-region has a plurality of first tower bases, and the surface of the second sub-region has a plurality of second tower bases, wherein the tower base size of the second tower base is larger than the tower base size of the first tower base.

5. The solar cell according to claim 4, characterized in that, The first tower base has a tower base size of 10 μm to 20 μm, and the second tower base has a tower base size of 18 μm to 40 μm.

6. The solar cell according to claim 4, characterized in that, The first tower base surface is a flat structure, while the second tower base surface has several protruding structures.

7. The solar cell according to any one of claims 1-6, characterized in that, The P-type doped layer includes a P-type doped polysilicon layer, and the N-type doped layer includes an N-type doped polysilicon layer. A first dielectric layer is disposed between the silicon substrate and the P-type doped layer, and a second dielectric layer is disposed between the silicon substrate and the N-type doped layer.

8. The solar cell according to any one of claims 1-6, characterized in that, The solar cell also includes: A positive passivation layer and / or a back passivation layer, wherein the positive passivation layer covers the front side of the silicon substrate, and the back passivation layer covers the side of the P-type doped layer opposite to the silicon substrate and the side of the N-type doped layer opposite to the silicon substrate; A first electrode and a second electrode, wherein the first electrode passes through the back passivation layer to form an ohmic contact with the P-type doped layer, and the second electrode passes through the back passivation layer to form an ohmic contact with the N-type doped layer.

9. The solar cell according to claim 8, characterized in that, The solar cell further includes the positive passivation layer, which includes a positive alumina layer and a positive silicon nitride layer stacked together, wherein the positive alumina layer is located on the side close to the silicon substrate, and the positive silicon nitride layer is located on the side of the positive alumina layer away from the silicon substrate; The solar cell further includes the back passivation layer, which includes a back alumina layer and a back silicon nitride layer stacked together, wherein the back alumina layer is located on the side close to the silicon substrate, and the back silicon nitride layer is located on the side of the back alumina layer away from the silicon substrate.

10. A photovoltaic module, characterized in that, Includes the solar cell as described in any one of claims 1-9.

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