redistribution structure

Abstract

This application discloses a redistribution structure comprising: a first dielectric layer; a first circuit layer, a portion of which is covered by the first dielectric layer; a first protective layer covering a portion of the first circuit layer; and a second dielectric layer covering both the first dielectric layer and a portion of the first circuit layer, wherein the first circuit layer is exposed by an opening defined by the second dielectric layer and the first protective layer. The purpose of this invention is to reduce the impact of electromigration and improve the circuit strength of the first circuit layer, at least through the first protective layer.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a redistribution structure. Background Technology

[0002] For high-performance computing (HPC) and artificial intelligence (AI) applications, advanced fan-out packaging with fine copper traces using a redistribution layer (RDL) is a key technology enabling high-bandwidth, dense transmission. However, such fine traces face three major challenges. (See also...) Figure 1 , Figure 2 as well as Figure 3 To understand. Figure 1 , Figure 2 as well as Figure 3 Schematic diagrams are shown illustrating defects in the copper trace 100 of the prior art. First, see... Figure 1 The diagram shows several top-down views of the copper traces 100. Because the copper traces 100 are so small, some may lack sufficient structural strength and break under stress 110. Currently, the yield loss due to the breakage of fine copper traces 100 exceeds 10%. Secondly, see... Figure 2 The image shows a cross-section of a single copper trace 100. Generally, copper traces 100 in the prior art are used to transmit high-frequency signals. However, when high-frequency current passes through copper trace 100, due to the skin effect, the current tends to flow more on the surface of copper trace 100. Figure 2 The diagram shows a high current density region 101 and a low current density region 102 of the copper trace 100. Due to the skin effect, the high-frequency current transmitted in the copper trace 100 tends to flow towards the high current density region 101 located on the surface of the copper trace 100 rather than towards the low current density region 102. This reduces the effective flow area of ​​the current in the copper trace 100, thereby increasing the resistance of the copper trace 100. This increased resistance leads to a deterioration in the integrity of the high-frequency signal, resulting in a high insertion loss fail rate (HFSF) greater than 10%. Third, see... Figure 3In general, existing technologies manufacture copper traces 100 using a semi-additive process. However, copper traces 100 manufactured using this process lack capping layers on their upper and side surfaces. Furthermore, due to the evolving functional requirements of semiconductors, the geometric dimensions of copper traces 100 are continuously shrinking, leading to a corresponding increase in the current density flowing through them. This higher current density exacerbates the problem of electromigration. See [link to relevant documentation] for details. Figure 3 Electromigration can cause voids to appear inside the copper trace 100. Severe electromigration can result in a yield loss of more than 10%. Utility Model Content

[0003] To address the above issues, this application proposes a redistribution structure that reduces the impact of electromigration and improves the line strength of the first line layer, at least through a first protective layer.

[0004] The technical solution of this application is implemented as follows:

[0005] According to one aspect of this application, a redistribution structure is provided, comprising: a first dielectric layer; a first circuit layer, a portion of which is covered by the first dielectric layer; a first protective layer covering a portion of the first circuit layer; and a second dielectric layer covering the first dielectric layer and a portion of the first circuit layer, wherein the first circuit layer is exposed by an opening, wherein the opening is jointly defined by the second dielectric layer and the first protective layer.

[0006] In some embodiments, the inner sidewall of the second dielectric layer is aligned with the inner sidewall of the first protective layer to form the sidewall of the opening.

[0007] In some embodiments, the first protective layer extends from the upper surface of the first circuit layer to the upper surface of the first dielectric layer.

[0008] In some embodiments, the first protective layer is a graphene layer.

[0009] In some embodiments, the first circuit layer includes a first conductive material layer and a first metal barrier layer. The first conductive material layer includes a first horizontal portion and a first trapezoidal portion extending from the lower surface of the first horizontal portion and gradually narrowing in width from top to bottom. The first metal barrier layer covers the sidewalls and lower surface of the first trapezoidal portion and the lower surface of the first horizontal portion exposed relative to the first trapezoidal portion.

[0010] In some embodiments, the first conductive material layer is a copper layer.

[0011] In some embodiments, the first metal barrier layer is one of a titanium (Ti) layer, a tantalum (Ta) layer, titanium nitride (TiN), tantalum nitride (TaN) layer, or a tungsten (W) layer.

[0012] In some embodiments, the first protective layer covers the upper surface of the first horizontal portion, the side surface of the first horizontal portion, and the exposed surface of the first metal barrier layer sandwiched between the lower surface of the first horizontal portion and the upper surface of the first dielectric layer.

[0013] In some embodiments, the thickness of the first protective layer is... to Within the range.

[0014] In some embodiments, the thickness of the first metal barrier layer is... to Within the range.

[0015] In some embodiments, the lower surface of the first dielectric layer is flush with the lower surface of the first metal barrier layer.

[0016] In some embodiments, the redistribution structure further includes a second line layer disposed above the first line layer and electrically connected to the first line layer through an opening.

[0017] In some embodiments, the second circuit layer includes a second conductive material layer and a second metal barrier layer. The second conductive material layer includes a second horizontal portion and a second trapezoidal portion extending from the lower surface of the second horizontal portion and gradually narrowing in width from top to bottom. The second metal barrier layer covers the sidewalls and lower surface of the second trapezoidal portion and the lower surface of the second horizontal portion exposed relative to the second trapezoidal portion.

[0018] In some embodiments, the redistribution structure further includes a second protective layer covering the upper surface and sidewalls of the second transverse portion.

[0019] In some embodiments, the second trapezoidal portion of the second circuit layer is laterally offset from the first trapezoidal portion of the first circuit layer.

[0020] In some embodiments, the second protective layer and the second metal barrier layer completely cover the second conductive material layer.

[0021] In some embodiments, the redistribution structure further includes a third circuit layer disposed on the upper surface of the first dielectric layer, the third circuit layer including metal traces and a third metal barrier layer located below the metal traces.

[0022] In some embodiments, the redistribution structure further includes a third protective layer covering the upper surface and sidewalls of the metal traces, as well as the sidewalls of the third metal barrier layer.

[0023] In some embodiments, the metal trace is a copper trace.

[0024] According to another aspect of this application, a redistribution structure is provided, comprising: a first dielectric layer; a first circuit layer partially embedded in the first dielectric layer; a first protective layer disposed on a surface of the first circuit layer exposed relative to the first dielectric layer; and a second dielectric layer disposed above the first protective layer and the first dielectric layer, wherein the second dielectric layer and the first protective layer together form an opening to expose the first circuit layer.

[0025] The beneficial effects of the above technical solution include at least the following: reducing the impact of electromigration through the first protective layer and improving the line strength of the first line layer. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 , Figure 2 as well as Figure 3 Schematic diagrams are shown for defects in copper traces in the prior art.

[0028] Figure 4 A cross-sectional schematic diagram of a redistribution structure 200 according to some embodiments of this application is shown.

[0029] Figure 5 It shows Figure 4 An enlarged schematic diagram of region A in the middle.

[0030] Figure 6 A three-dimensional structural schematic diagram of a first protective layer according to some embodiments of this application is shown.

[0031] Figure 7 A cross-sectional view of a first circuit layer and a schematic diagram of current lines located in the first circuit layer are shown according to some embodiments of this application.

[0032] Figure 8 A schematic diagram of a third circuit layer according to some embodiments of this application is shown.

[0033] Figure 9 A schematic diagram of a third circuit layer according to other embodiments of this application is shown.

[0034] Figure 10 It shows Figure 8 Enlarged schematic diagram of region B in the middle.

[0035] Figure 11 A top view of the third circuit layer covered by a third protective layer is shown.

[0036] Figure 12 A cross-sectional schematic diagram of the third circuit layer covered by a third protective layer is shown.

[0037] Figure 13 A cross-sectional schematic diagram of a redistribution structure according to some embodiments of this application is shown.

[0038] Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 as well as Figure 23 A schematic cross-sectional view during the fabrication of a redistribution structure according to some embodiments of this application is shown.

[0039] Figure 24 A three-dimensional schematic diagram of the metal traces is shown.

[0040] Figure 25 A three-dimensional schematic diagram of the metal traces covered with a third protective layer is shown. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0042] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. These are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the present invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0043] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0044] Figure 4A cross-sectional schematic diagram of a redistribution structure 200 according to some embodiments of this application is shown. Figure 5 It shows Figure 4 A magnified view of region A in the middle. See also... Figure 4 The redistribution structure 200 includes: a first dielectric layer 210; a first circuit layer 220, a portion of which is covered by the first dielectric layer 210; a first protective layer 230, covering a portion of the first circuit layer 220; and a second dielectric layer 240, covering both the first dielectric layer 210 and a portion of the first circuit layer 220. The first circuit layer 220 is exposed by an opening 250, which is jointly defined by the second dielectric layer 240 and the first protective layer 230. It can be understood that... Figure 4 as well as Figure 5 The illustration shows an opening 250 defined by a second dielectric layer 240 and a first protective layer 230, exposing the upper surface of the first wiring layer 220. The opening 250 can also be further enlarged to expose the sidewalls of the first wiring layer 220. In some embodiments, the redistribution structure 200 may further include a second wiring layer 260 disposed above the first wiring layer 220, which may be disposed within the opening 250. It is understood that in some embodiments, the opening 250 is first defined by the second dielectric layer 240 and the first protective layer 230, and then the second wiring layer 260 is formed within the opening. By providing a first protective layer 230 that partially covers the first wiring layer 220, it serves as a protective layer to strengthen the wiring of the first wiring layer 220 and can reduce voids caused by electromigration. See further... Figure 4 and Figure 5In some embodiments, the inner sidewall of the second dielectric layer 240 is aligned with the inner sidewall of the first protective layer 230 to form the sidewall of the opening 250. In other embodiments, the inner sidewall of the second dielectric layer 240 and the inner sidewall of the first protective layer 230 may be offset to form a stepped sidewall of the opening 250. In some embodiments, the first protective layer 230 extends from the upper surface of the first circuit layer 220 to the upper surface of the first dielectric layer 210. The first protective layer 230 may be a graphene layer, specifically, a multilayer graphene layer, because graphene acts as a barrier, thus greatly enhancing its resistance to electromigration. Furthermore, the first circuit layer 220 may include a first conductive material layer 221 and a first metal barrier layer 222. The first conductive material layer 221 includes a first horizontal portion 2211 and a first trapezoidal portion 2212 extending from the lower surface of the first horizontal portion 2211 and gradually narrowing in width from top to bottom. The first metal barrier layer 222 covers the sidewalls and lower surface of the first trapezoidal portion 2212, as well as the lower surface of the first horizontal portion 2211 exposed relative to the first trapezoidal portion 2212. The first conductive material layer 221 may be a copper (Cu) layer. Furthermore, the first metal barrier layer 222 may be one of a titanium (Ti) layer, a tantalum (Ta) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, or a tungsten (W) layer. And, in some embodiments, such as... Figure 4 and Figure 5 As illustrated, the first protective layer 230 may cover a portion of the upper surface of the first horizontal portion 2211, the side surface of the first horizontal portion 2211, and the exposed surface of the first metal barrier layer 222 sandwiched between the lower surface of the first horizontal portion 2211 and the upper surface of the first dielectric layer 210. The thickness of the first protective layer 230 may be... to Within the range. And the thickness of the first metal barrier layer 222 can be within the range. to Within the range. In some embodiments, the lower surface of the first dielectric layer 210 is flush with the lower surface of the first metal barrier layer 222.

[0045] See also Figure 4 and Figure 5In some embodiments, the second wiring layer 260 is disposed above the first wiring layer 220 and electrically connected to the first wiring layer 220 through an opening 250. Further, the second wiring layer 260 may include a second conductive material layer 261 and a second metal barrier layer 262. The second conductive material layer 261 includes a second horizontal portion 2611 and a second trapezoidal portion 2612 extending from the lower surface of the second horizontal portion 2611 and gradually narrowing in width from top to bottom. The second metal barrier layer 262 covers the sidewalls and lower surface of the second trapezoidal portion 2612, as well as the lower surface of the second horizontal portion 2611 exposed relative to the second trapezoidal portion 2612. Further, the redistribution structure 200 may also include a second protective layer 270 covering the upper surface and sidewalls of the second horizontal portion 2611. The arrangement of the second protective layer 270 may be similar to that of the first protective layer 230, and correspondingly, the arrangement of the second wiring layer 260 may also be similar to that of the first wiring layer 220. The second protective layer 270 and the second metal barrier layer 262 can completely cover the second conductive material layer 261.

[0046] Figure 6 A three-dimensional structural schematic diagram of the first protective layer 230 according to some embodiments of this application is shown. Figure 7 A cross-sectional view of a first circuit layer 220 according to some embodiments of this application and a schematic diagram of current lines located in the first circuit layer 220 are shown. See also Figure 6 and Figure 7 In one embodiment where the first protective layer 230 is a graphene layer, such as... Figure 6 As shown, the first protective layer 230 is formed by multiple first protective sublayers 231 stacked in layers, in which case the first protective sublayer 231 is a single layer of graphene. Figure 6 The diagram also shows the horizontal direction (lateral X and longitudinal Y) and the vertical direction (Z), due to the structural characteristics of the graphene layers. Figure 6 In the vertical direction Z illustrated, the current needs to pass through multiple stacked graphene layers, where the graphene's "vertical resistivity" is 1000 μΩ·cm. However, in the horizontal directions X and Y, the current does not need to pass through multiple stacked graphene layers but only flows along a single graphene layer. Furthermore, as a two-dimensional material, graphene has a lower resistivity within the plane of a single graphene layer, resulting in a "planar resistivity" of 1.0 μΩ·cm. Figure 7As shown, due to the presence of the first protective layer 230 as a graphene layer, the direction of the first current 1001 is not perpendicular to the graphene layer and needs to pass through multiple graphene layers, thus allowing the first current 1001 to flow within the first circuit layer 230. However, the direction of the second current 1002 is perpendicular to the graphene layer and also needs to pass through multiple graphene layers. Due to the excessively high "vertical resistivity" of graphene in this direction, the second current 1002 is difficult to conduct. Further details are also provided. Figure 4 and Figure 5 In order to ensure the electrical connection path between the first circuit layer 220 and the second circuit layer 260, the first protective layer 230 between the first circuit layer 220 and the second circuit layer 260 is removed. Since when the first protective layer 230 is a multilayer graphene layer, the current flowing between the first circuit layer 220 and the second circuit layer 260 needs to pass through the multilayer graphene layer and is therefore affected by a relatively large "vertical resistivity", the first protective layer 230 at the bottom of the opening 250 should be removed to expose the first circuit layer 220 and make the second circuit layer 260 directly contact the first circuit layer 220 to reduce the resistance between the first circuit layer 220 and the second circuit layer 260.

[0047] Similarly, the three problems encountered with the aforementioned fine copper traces can be understood. By employing a first protective layer 230 as a multilayer graphene layer, significant improvements can be achieved. When the first circuit layer 220 exhibits a similar effect due to the skin effect... Figure 2 When the copper trace 100 is located in the high current density region 101 on the periphery and the low current density region 102 on the inside, the current is basically concentrated on the periphery of the first circuit layer 220, close to the first protective layer 230 located on the periphery of the first circuit layer 220. Furthermore, the graphene layers in the first protective layer 230 are stacked on the sidewalls and top surface of the first circuit layer 220, and the extension direction of each graphene layer is correspondingly parallel to the planar direction of the sidewalls and top surface of the first circuit layer 220. At this time, due to the low horizontal resistivity of graphene, the skin effect can be used to concentrate the current on the periphery of the first circuit layer 220, and high-frequency current can be transmitted with low resistivity along the plane of each graphene layer, thereby improving the integrity of the high-frequency signal. By using the first protective layer 230 as a multilayer graphene layer, the conductivity of the first circuit layer 220 can be improved by 20%. Secondly, since graphene has a Young's modulus of approximately 2400 GPa, which is higher than copper's 115 GPa, the mechanical strength of the first circuit layer 220 can be increased by 15% by using the first protective layer 230 as a multilayer graphene layer. Furthermore, since graphene can act as a diffusion barrier layer for copper, reducing the impact of electromigration, the lifespan of the first circuit layer 220 can be increased by more than two times by using the first protective layer 230 as a multilayer graphene layer.

[0048] Figure 8 A schematic diagram of a third line layer 290 according to some embodiments of this application is shown. Figure 9 A schematic diagram of a third circuit layer 290 according to other embodiments of this application is shown. In some embodiments, the redistribution structure 200 may further include a third circuit layer 290 disposed on the upper surface of the first dielectric layer 210. The third circuit layer 290 includes a metal trace 291 and a third metal barrier layer 292 located below the metal trace 291. The third circuit layer 290 may be embedded in the second dielectric layer 240, or similarly. Figure 9 No other layers are disposed above the third circuit layer 290. The metal trace 291 can be a copper trace. Furthermore, the redistribution structure 200 can also be provided with a third protective layer 310, which covers the upper surface and sidewalls of the metal trace 291, as well as the sidewalls of the third metal barrier layer 292. Similarly, the third protective layer 310 can also be configured as a stacked multilayer graphene layer, similar to the first protective layer 230, and can bring corresponding effects to the third circuit layer 290. Preferably, similar to the first metal barrier layer 222, the third metal barrier layer 292 can be one of a titanium (Ti) layer, a tantalum (Ta) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, or a tungsten (W) layer.

[0049] Figure 10 It shows Figure 8 A magnified view of region B in the diagram, with different depths used to distinguish the layers for easier differentiation. See also... Figure 8 and Figure 10 The third protective layer 310 and the third metal barrier layer 292 together completely surround the metal trace 291, thereby reducing the adverse effects of electromigration.

[0050] Figure 11 A top view of the third circuit layer 290 covered by the third protective layer 310 is shown. See also: Figure 11 In some embodiments, in the top view illustrated, the third protective layer 310 may slightly expose the third circuit layer 290 located beneath it; however, preferably, the third protective layer 310 completely covers the third circuit layer 290 in this top view. Under the action of pressure 110, the third protective layer 310 strengthens the structural strength of the third circuit layer 290, thus reducing the possibility of the third circuit layer 290 breaking.

[0051] Figure 12 A schematic cross-sectional view of the third circuit layer 290 covered by the third protective layer 310 is shown. See also Figure 12The third protective layer 310 covers the third circuit layer 290. Due to the skin effect, the metal trace 291 (which may be a copper trace) includes a high current density region 2901 on the periphery and a low current density region 2902 in the center. As mentioned above, due to the low "horizontal resistivity" of the third protective layer 310, that is, the graphene layer, the current can be concentrated on the periphery of the third circuit layer 290 by utilizing the skin effect and the high-frequency current can be transmitted at a low resistivity along the plane of each graphene layer, thereby improving the integrity of the high-frequency signal.

[0052] Figure 13 A schematic cross-sectional view of a redistribution structure 200 according to some embodiments of this application is shown. See also Figure 13 In some embodiments, the second trapezoidal portion 2612 of the second circuit layer 260 is laterally offset from the first trapezoidal portion 2212 of the first circuit layer 220.

[0053] This application also provides a redistribution structure 200, which can be referred to in conjunction with it. Figure 4 and Figure 5 Understandably, the redistribution structure 200 includes: a first dielectric layer 210; a first circuit layer 220 partially embedded in the first dielectric layer 210; a first protective layer 230 disposed on the surface of the first circuit layer 220 exposed relative to the first dielectric layer 210; and a second dielectric layer 240 disposed above the first protective layer 230 and the first dielectric layer 210, wherein the second dielectric layer 240 and the first protective layer 230 together form an opening to expose the first circuit layer 220.

[0054] Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 as well as Figure 23 A schematic cross-sectional view of a redistribution structure 200 according to some embodiments of this application is shown during manufacturing. See also Figure 14 A first dielectric layer 210 is formed on the fan-out multilayer (FO multi-layer) 500, and the first dielectric layer 210 has a first opening 2101. Figure 15 In this process, a first seed layer 510 is deposited on the surface of the first dielectric layer 210 and the first opening 2101. Of course, although not shown, before depositing the first seed layer 510, a first metal barrier layer 222 and a third metal barrier layer 292 may be deposited accordingly on the surface of the first dielectric layer 210 and the first opening 2101. Furthermore, in... Figure 16In the process, a first photoresist 520 is printed (lithograph) on the first seed layer 510. And... Figure 17 In this process, copper is electroplated on the first seed layer 510 to form a first conductive material layer 221 and a metal trace 291. Figure 18 In the next step, the first photoresist 520 is stripped, exposing the first conductive material layer 221 and the metal traces 291. Figure 19 In the process, the first seed layer 510, exposed by the first conductive material layer 221 and the metal trace 291, is etched, thereby forming the first circuit layer 220 and the third circuit layer 290. Figure 20 In this process, graphene is selectively deposited on the first conductive material layer 221 and the metal trace 291 by plasma-enhanced chemical vapor deposition (PECVD) to form the first protective layer 230 and the third protective layer 310 accordingly. Figure 21 In this process, a second dielectric layer 240 is formed and an opening 250 is formed, exposing a portion of the first protective layer 230 on the first circuit layer 220. Figure 22 In this process, the portion of the first protective layer 230 exposed on the first circuit layer 220 by the opening 250 is removed by dry etching. Dry etching can employ either chemical ion bombardment or radical chemical etching. Figure 23 In, similar to Figures 14 to 20 The process involves forming a second circuit layer 260 covered by a second protective layer 270 and a third circuit layer 290 covered by a third protective layer 310 on the second dielectric layer 240.

[0055] Figure 24 A three-dimensional schematic diagram of the metal trace 291 is shown. Figure 25 A three-dimensional schematic diagram of the metal trace 291 covered with a third protective layer 310 is shown.

[0056] The technical solutions provided in this application can be applied to all products containing metal circuitry, such as: Fan-Out Chip-on-Substrate (FOCoS), Fan-Out Chip-on-Substrate Bridge (FOCoS-B), 2.5D packaging, three-dimensional integrated circuits (3D ICs), and Fan-Out Substrate (FOSub) packaging. The graphene protective layer in the technical solutions provided in this application enhances the performance of the fine circuit layer, reducing the low open-circuit failure rate to below 5%, the low insertion loss failure rate to below 2%, and the low electromigration failure rate to below 5%. Furthermore, the graphene protective layer structure extends the capabilities of the "semi-additive process" from the micrometer level to the sub-micrometer level, resulting in redistributed structures with higher electromigration reliability and mean time to failure reliability.

[0057] The technical solution provided in this application, at least through the first protective layer, avoids electron migration, reduces resistivity, and improves the line strength of the first line layer.

[0058] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A redistribution structure, characterized in that, include: First dielectric layer; The first circuit layer, a portion of which is covered by the first dielectric layer; The first protective layer covers a portion of the first circuit layer; A second dielectric layer covers the first dielectric layer and a portion of the first circuit layer, wherein the first circuit layer is exposed by an opening defined by the second dielectric layer and the first protective layer.

2. The redistribution structure according to claim 1, characterized in that, The inner sidewall of the second dielectric layer is aligned with the inner sidewall of the first protective layer to form the sidewall of the opening.

3. The redistribution structure according to claim 1, characterized in that, The first protective layer extends from the upper surface of the first circuit layer to the upper surface of the first dielectric layer.

4. The redistribution structure according to claim 1, characterized in that, The first protective layer is a graphene layer.

5. The redistribution structure according to claim 1, characterized in that, The first circuit layer includes a first conductive material layer and a first metal barrier layer. The first conductive material layer includes a first horizontal portion and a first trapezoidal portion extending from the lower surface of the first horizontal portion and gradually narrowing in width from top to bottom. The first metal barrier layer covers the sidewalls and lower surface of the first trapezoidal portion and the lower surface of the first horizontal portion exposed relative to the first trapezoidal portion.

6. The redistribution structure according to claim 5, characterized in that, The first conductive material layer is a copper layer.

7. The redistribution structure according to claim 5, characterized in that, The first metal barrier layer is one of a titanium (Ti) layer, a tantalum (Ta) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, or a tungsten (W) layer.

8. The redistribution structure according to claim 5, characterized in that, The first protective layer covers the upper surface of the first horizontal portion, the side surface of the first horizontal portion, and the exposed surface of the first metal barrier layer sandwiched between the lower surface of the first horizontal portion and the upper surface of the first dielectric layer.

9. The redistribution structure according to claim 1, characterized in that, The thickness of the first protective layer is to Within the range.

10. The redistribution structure according to claim 5, characterized in that, The thickness of the first metal barrier layer is to Within the range.

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