Semiconductor dies and semiconductor packages

Abstract

The utility model provides a kind of semiconductor die, it includes semiconductor substrate, inner connection structure, capacitor structure, rewiring layer and bonding conductor. Inner connection structure is arranged on semiconductor substrate. Capacitor structure is arranged on inner connection structure. Rewiring layer is arranged on inner connection structure and is electrically connected to inner connection structure. Bonding conductor and capacitor structure are electrically contacted and physically contacted at the side wall of bonding conductor, wherein rewiring layer is located at the lower level than bonding conductor.

Description

Technical Field

[0001] Embodiments of this utility model relate to semiconductor dies and semiconductor packages. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. In recent years, the growing demand for miniaturization, higher speeds, wider bandwidths, and lower power consumption and latency has also led to a growing need for packaging technologies for smaller, more innovative semiconductor dies. Utility Model Content

[0003] This utility model provides a semiconductor die, comprising: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate; a capacitor structure disposed on the interconnect structure; a redistribution layer disposed on the interconnect structure and electrically connected to the interconnect structure; and a bonding conductor that is in electrical and physical contact with the capacitor structure at the sidewall of the bonding conductor, wherein the redistribution layer is located at a lower level than the bonding conductor.

[0004] This utility model provides a semiconductor package, including: a first semiconductor die; and a second semiconductor die electrically connected to the first semiconductor die, wherein the second semiconductor die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate; a bonding conductor disposed on the interconnect structure and electrically connected to the interconnect structure; a redistribution layer disposed on the interconnect structure and located at a level lower than the bonding conductor; and a capacitor structure laterally surrounding the sidewall of the bonding conductor and electrically connected to the sidewall of the bonding conductor. Attached Figure Description

[0005] The best understanding of all aspects of this invention will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figures 1A to 1I Schematic cross-sectional views are shown of various stages of a method for manufacturing a semiconductor die according to some embodiments of the present invention.

[0007] Figure 2 This is a schematic cross-sectional view of a semiconductor die according to some alternative embodiments of the present invention.

[0008] Figure 3This is a schematic cross-sectional view of a semiconductor die according to some alternative embodiments of the present invention.

[0009] Figure 4 This is a schematic cross-sectional view of a semiconductor die according to some alternative embodiments of the present invention.

[0010] Figures 5A to 5H Schematic cross-sectional views are shown of various stages of a method for manufacturing a semiconductor package according to some embodiments of the present invention.

[0011] Figure 6 yes Figure 5H A schematic top view of a portion of a semiconductor die in a semiconductor package.

[0012] Figure 7 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present invention.

[0013] Figure 8 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present invention.

[0014] Figure 9 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present invention.

[0015] Figure 10 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present invention.

[0016] Figure 11 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present invention.

[0017] Figure 12 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present invention.

[0018] Figure 13 This is a schematic cross-sectional view of the packaging structure according to some embodiments of the present invention. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various examples. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0021] In addition, for ease of description, this article may use terms such as “first” and “second” to describe similar or different elements or features as shown in the figure, and these terms may be used interchangeably depending on the order of appearance or the context of the description.

[0022] As used herein, “about,” “approximately,” or “substantially” generally means within 20%, 10%, 5%, 3%, or 1% of a given value or range. The values ​​given herein are approximate, meaning that the terms “about,” “approximately,” or “substantially” can be inferred unless explicitly stated otherwise.

[0023] It should be understood that the following embodiments of the present invention provide applicable concepts that can be embodied in various specific contexts. These embodiments are intended to provide further illustration and are not intended to limit the scope of the present invention. The specific embodiments described herein relate to a semiconductor package and a method of manufacturing the same, but are not intended to limit the scope of the present invention. In some embodiments, the semiconductor package may be or include a system-on-integrated-circuit (SoIC) package, an integrated fan-out (InFO) package, a chip-on-wafer (CoW) package, a system-on-wafer (SoW), a chip-on-wafer-on-substrate (CoWoS) package, a package-on-package (PoP), an InFO package with a POP, a wafer-level package (WLP), a three-dimensional fabric (3Dfabric) device or package, etc.

[0024] Other features and processes may also be included. For example, test structures may be incorporated to assist in verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate, which allow for testing of 3D packages or 3DICs, probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods that incorporate intermediate verification of known-good dies to increase yield and reduce costs.

[0025] Figures 1A to 1I A schematic cross-sectional view is shown of various stages of a method for manufacturing a semiconductor die 100 according to some embodiments of the present invention.

[0026] refer to Figure 1AA semiconductor substrate 110 is provided. In some embodiments, the semiconductor substrate 110 serves as a carrier for forming or depositing subsequent layers / constructions thereon. In some embodiments, the semiconductor substrate 110 comprises Si, Ge, SiGe, SiC, or other suitable semiconductor materials. The semiconductor substrate 110 may be a bulk substrate or configured as a semiconductor on an insulator (SOI) substrate. The semiconductor substrate 110 may include a redistribution layer (RDL), a dielectric structure, or a combination thereof. The RDL may include multiple conductive layers and / or multiple vias. The semiconductor substrate 110 may include one or more devices 112 adjacent to the top surface of the semiconductor substrate 110. Devices 112 may include integrated circuit devices, such as transistors, diodes, resistors, capacitors, etc.

[0027] Continue to refer to Figure 1A An interconnect structure 120 is formed on a semiconductor substrate 110. In some embodiments, the interconnect structure 120 includes a plurality of dielectric layers 121, a plurality of conductive patterns 122, and a plurality of etch stop layers 123. In some embodiments, see... Figure 1A Multiple dielectric layers 121 and multiple etch stop layers 123 are alternately formed along a direction Z perpendicular to the top surface of the semiconductor substrate 110, and multiple conductive patterns 122 are embedded in the multiple dielectric layers 121 and multiple etch stop layers 123. Figure 1A As shown, the plurality of conductive patterns 122 include multiple wiring traces 122a extending horizontally in a direction X perpendicular to the Z direction within a plurality of dielectric layers 121, and a plurality of vias 122b penetrating the plurality of dielectric layers 121 vertically to establish electrical connections between the upper and lower wiring traces 122a and to establish electrical connections with a plurality of devices 112. In other words, the interconnect structure 120 provides a redistribution function for routing, repositioning, or reassigning the electrical connection paths of the plurality of devices 112.

[0028] Additionally, a sealing ring 130 with a through-connection structure 120 is formed. For example... Figure 1AAs shown, a sealing ring 130 extends vertically through a plurality of dielectric layers 121 and a plurality of etch stop layers 123. In some embodiments, the sealing ring 130 is formed of one or more materials that are the same as the materials of the plurality of conductive patterns 122. The sealing ring 130 serves as a structural support element to enhance structural rigidity during cutting or trimming. In some embodiments, the sealing ring 130 is an electrically floating element. It should be understood that the number and configuration of the plurality of dielectric layers 121, the plurality of etch stop layers 123, and the plurality of conductive patterns 122 are merely exemplary and are not intended to limit the scope of the present invention.

[0029] Continue to refer to Figure 1A A passivation layer 140 is formed on the interconnect structure 120. The material of the passivation layer 140 may include silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass (USG), etc. Furthermore, refer to... Figure 1A A redistribution layer 150 is formed, penetrating the passivation layer 140, to be electrically connected to the interconnect structure 120. Specifically, such as Figure 1A As shown, the redistribution layer 150 has a plurality of vias V penetrating the passivation layer 140 for electrical connection to the interconnect structure 120. In some embodiments, the redistribution layer 150 includes a plurality of conductive patterns, such as conductive pads and / or conductive wiring. The plurality of conductive patterns of the redistribution layer 150 may have a different pitch or line / spacing (L / S) than the plurality of conductive patterns 122 of the interconnect structure 120. In some embodiments, the material of the redistribution layer 150 includes aluminum, aluminum-copper, copper, or any other suitable conductive material. In some embodiments, the redistribution layer 150 includes aluminum pads or copper-doped aluminum pads, wherein the copper doping concentration is from about 0.001% to about 50%. In one embodiment, the copper doping concentration is about 0.5%.

[0030] refer to Figure 1BA gap-filling dielectric layer 160 is formed on the passivation layer 140, and the gap-filling dielectric layer 160 covers the redistribution layer 150. In some embodiments, the gap-filling dielectric layer 160 fills the gaps between a plurality of conductive patterns of the redistribution layer 150 to provide a substantially flat top surface. In some embodiments, a planarization process is performed on the gap-filling dielectric layer 160 to provide a substantially flat top surface. The planarization process may include performing a chemical mechanical polishing (CMP) process. In some embodiments, the gap-filling dielectric layer 160 is formed by chemical vapor deposition (CVD) (e.g., plasma-enhanced CVD, high-density plasma CVD (HDPCVD), or metal-organic CVD (MOCVD)) or physical vapor deposition (PVD). In some embodiments, the material of the gap-filling dielectric layer 160 may include a dielectric material, such as SiO, SiN, or SiON.

[0031] After forming the gap-filling dielectric layer 160, a capacitor structure 170 is formed on the gap-filling dielectric layer 160. The following will refer to... Figures 1C to 1F The formation of capacitor structure 170 is described in detail.

[0032] refer to Figure 1C A dielectric material layer DL1 and a conductive material layer CL1 are sequentially formed on the interstitial filling dielectric layer 160. In some embodiments, the dielectric material layer DL1 is made of a high dielectric constant (high k) dielectric material (e.g., a dielectric constant (k) in the range of about 10 to about 20) comprising oxides or other suitable materials including Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu. In some embodiments, the dielectric material layer DL1 is formed by performing a plasma-enhanced CVD process, a low-pressure CVD process, an atomic layer deposition (ALD) process, a molecular beam deposition (MBD) process, or other suitable processes. In some embodiments, the conductive material layer CL1 is made of a metal. In some embodiments, the conductive material layer CL1 is made of aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, or other suitable materials. In some embodiments, a conductive material layer CL1 is formed by performing a deposition process (e.g., CVD, PVD, or ALD).

[0033] refer to Figure 1DThe dielectric material layer DL1 and the conductive material layer CL1 are patterned using photolithography and etching and / or any suitable patterning process to form dielectric layer 171 and electrode layer 172. In some embodiments, the dielectric material layer DL1 and the conductive material layer CL1 are patterned in the same patterning process. In some alternative embodiments, the dielectric material layer DL1 and the conductive material layer CL1 are patterned in different patterning processes. Figure 1D As shown, the sidewalls of the electrode layer 172 are substantially aligned with the sidewalls of the underlying dielectric layer 171.

[0034] refer to Figure 1E A dielectric material layer DL2, a conductive material layer CL2, and a dielectric material layer DL3 are sequentially formed on the gap-filling dielectric layer 160. In some embodiments, the dielectric material layer DL2, the conductive material layer CL2, and the dielectric material layer DL3 are conformally formed on the gap-filling dielectric layer 160 and cover the dielectric layer 171 and the electrode layer 172, as shown below. Figure 1E As shown. The materials and processes used to form dielectric material layers DL2 and DL3 can be similar to or the same as those used to form dielectric material layer DL1, and will not be described further here. The materials and processes used to form conductive material layer CL2 can be similar to or the same as those used to form conductive material layer CL1, and will not be described further here. The material of dielectric material layer DL2 can be the same as or different from the material of dielectric material layer DL1. Furthermore, the material of dielectric material layer DL3 can be the same as or different from the material of dielectric material layer DL2. And, the material of conductive material layer CL2 can be the same as or different from the material of conductive material layer CL1.

[0035] refer to Figure 1F Subsequently, the dielectric material layer DL2, the conductive material layer CL2, and the dielectric material layer DL3 are patterned using photolithography and etching and / or any suitable patterning process to form a dielectric layer 173, an electrode layer 174, and a dielectric layer 175, thereby forming a capacitor structure 170. In some embodiments, the conductive material layer CL2 and the dielectric layer DL3 are patterned in the same patterning process. In some alternative embodiments, the conductive material layer CL2 and the dielectric layer DL3 are patterned in different patterning processes. Further, in some embodiments, the dielectric material layer DL2 and the conductive material layer CL2 are patterned using different patterning processes. Figure 1F As shown, electrode layer 174 partially overlaps with electrode layer 172. Dielectric layer 173 may be located between electrode layer 174 and electrode layer 172. The sidewalls of electrode layer 172 can be separated from electrode layer 174 by dielectric layer 173. In addition, dielectric layer 175 has a sidewall substantially aligned with the sidewall of the underlying electrode layer 174, and the sidewall of dielectric layer 173 intersects with the sidewall of the overlying electrode layer 174, but is substantially aligned with the sidewall of the underlying electrode layer 172.

[0036] like Figure 1F As shown, the capacitor structure 170 includes a metal-insulator-metal (MIM) capacitor, comprising an electrode layer 172 as a bottom electrode layer, a dielectric layer 173 as a capacitor dielectric layer, and an electrode layer 174 as a top electrode layer. It should be understood that the number and configuration of the electrode layers and dielectric layers in the capacitor structure 170 are merely exemplary and are not intended to limit the scope of this invention. That is, the process for forming the capacitor structure 170 described above is only one method for forming a MIM capacitor, and other methods are fully included within the scope of this embodiment.

[0037] refer to Figure 1G A passivation layer 180 is formed on the gap-filling dielectric layer 160 and covers the capacitor structure 170. The material of the passivation layer 180 may include silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass (USG), etc.

[0038] Continue to refer to Figure 1G An opening O is formed through the passivation layer 180 and the gap-filling dielectric layer 160 to expose a portion of the redistribution layer 150. In some embodiments, the opening O in the passivation layer 180 and the gap-filling dielectric layer 160 is formed by any acceptable patterning process. For example, a photoresist is formed on and patterned over the passivation layer 180, and one or more etching processes can be used to remove the portions of the passivation layer 180 and the gap-filling dielectric layer 160 where the opening O needs to be formed. Note that the exposed portion of the redistribution layer 150 is for performing chip probe (CP) testing and / or wafer acceptance testing (WAT). However, the present invention is not limited thereto. In some alternative embodiments, the formation of the opening O is omitted in the method of manufacturing the semiconductor die 100.

[0039] refer to Figure 1H An etch stop layer 182 and a dielectric layer 192 are sequentially formed over the passivation layer 140. In some embodiments, the dielectric layer 192 is configured to be hybrid-bonded or fusion-bonded to another dielectric layer. In such embodiments, the dielectric layer 192 is referred to as a bonding dielectric layer. In some embodiments, the dielectric layer 192 comprises an oxide-based layer. In some embodiments, the dielectric layer 192 comprises silicon oxide, silicon oxynitride, or any suitable material configured for hybrid-bonding or fusion-bonding.

[0040] refer to Figure 1IA plurality of bonding conductors 194 are formed to electrically connect to the redistribution layer 150 and the capacitor structure 170. The material of the bonding conductors 194 may be or include copper or other suitable conductive materials. Furthermore, in some embodiments, each bonding conductor 194 may optionally include a barrier layer (not shown) on its outer surface to prevent atomic diffusion between the multiple elements. For example, the material of the barrier layer may be or include tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), combinations thereof, or other suitable materials. Additionally, as... Figure 1I As shown, multiple bonding conductors 194 are formed at a level higher than the weight wiring layer 150.

[0041] like Figure 1I As shown, due to the formation of the etch stop layer 182, the plurality of bonding conductors 194 may each include a via 194b and a conductive pad 194a wider than the via 194b. Although in Figure 1I In this embodiment, the bonding conductor 194 is formed having two parts (i.e., a via 194b and a conductive pad 194a), but the present invention is not limited thereto. In some alternative embodiments, the bonding conductor 194 may be formed as a single part with continuous sidewalls.

[0042] In detail, such as Figure 1IAs shown, the conductive pad 194a of each bonding conductor 194 is formed to be embedded in and in physical contact with the dielectric layer 192. A via 194b of one of the bonding conductors 194 is formed to pass through the passivation layer 180, dielectric layer 173, electrode layer 172, dielectric layer 171, and gap-filling dielectric layer 160 and is electrically connected to the redistribution layer 150. A via 194b of another of the bonding conductors 194 is formed to pass through the passivation layer 180, dielectric layer 173, electrode layer 174, dielectric layer 175, and gap-filling dielectric layer 160 and is electrically connected to the redistribution layer 150. In other words, one of the bonding conductors 194 serves as an electrode connector electrically connected to the electrode layer 172 of the capacitor structure 170, while another of the bonding conductors 194 serves as another electrode connector electrically connected to the electrode layer 174 of the capacitor structure 170. In other words, the electrode layer 172 of the capacitor structure 170 is in electrical and physical contact with the sidewall of one of the plurality of bonding conductors 194 (e.g., the sidewall of the via 194b), and the electrode layer 174 of the capacitor structure 170 is in electrical and physical contact with the sidewall of another of the plurality of bonding conductors 194 (e.g., the sidewall of the via 194b). From another perspective, in some embodiments, the capacitor structure 170 laterally surrounds the sidewalls of some of the bonding conductors 194. It should be noted that because the plurality of bonding conductors 194 made of copper are used as the plurality of electrode connections of the capacitor structure 170, the junction resistance between the capacitor structure 170 and the plurality of electrode connections can be reduced. This improves the capacitance efficiency of the capacitor structure 170. In some embodiments, the junction resistance of capacitor structure 170 is less than the resistance of passivation layer 180, gap-filling dielectric layer 160, passivation layer 140, or dielectric layer 121, and greater than or substantially equal to the resistance of bonding conductor 194, redistribution layer 150, or conductive pattern 122.

[0043] Furthermore, in some embodiments, the top surface of the bonding conductor 194 (i.e., the top surface of the conductive pad 194a) is substantially coplanar with the top surface of the dielectric layer 192, such as... Figure 1I As shown. It is worth noting that the top surfaces of the bonding conductor 194 and the dielectric layer 192 are highly coplanar, which is beneficial for subsequent processes (e.g., bonding processes).

[0044] Continue to refer to Figure 1I The monomerization process is performed along multiple scribe lines to form multiple monomerized semiconductor dies 100. It should be noted that the above manufacturing process is part of a wafer-level packaging process, although... Figure 1IThe illustration shows a monomerized semiconductor die 100, but those skilled in the art will understand that multiple semiconductor dies 100 are obtained after the monomerization process. In some embodiments, the monomerization process includes a dicing or sawing process. In subsequent processes, the monomerized semiconductor die 100 may, for example, be disposed on a packaging substrate or other components as needed.

[0045] Although the steps of the method are illustrated and described as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be construed as limiting. Furthermore, not all processes or steps shown are necessary to implement one or more embodiments of this invention.

[0046] like Figure 1I As shown, capacitor structure 170 comprises a five-layer structure (i.e., IMIMI). However, this invention is not limited thereto. It should be understood that... Figure 1I The structure shown is for illustrative purposes only; more than five layers are possible to increase the capacitance of the capacitor, or fewer layers are possible depending on product requirements. The following will refer to... Figure 2 Other embodiments are described.

[0047] Figure 2 This is a schematic cross-sectional view of a semiconductor die 200 according to some alternative embodiments of the present invention. Figure 2 The semiconductor die 200 shown is Figure 1I The semiconductor die 100 shown is similar; therefore, the same reference numerals are used to refer to the same or similar parts, and their detailed description will be omitted here. The differences between semiconductor die 200 and semiconductor die 100 will be described below.

[0048] refer to Figure 2 In the semiconductor die 200, the capacitor structure 270 includes an electrode layer 176 and a dielectric layer 177 sequentially formed on a dielectric layer 175. That is, the capacitor structure 270 includes a seven-layer structure (i.e., 1MIMIMI). More specifically, as... Figure 2 As shown, in the semiconductor die 200, electrode layer 176 and electrode layer 174 partially overlap. Figure 2 As shown, in the semiconductor die 200, the dielectric layer 175 can be located between the electrode layer 176 and the electrode layer 174, and the sidewall of the electrode layer 174 can be separated from the electrode layer 176 by the dielectric layer 173. Additionally, as... Figure 2 As shown, in the semiconductor die 200, the dielectric layer 177 has a sidewall substantially aligned with the sidewall of the underlying electrode layer 176, and the sidewall of the dielectric layer 175 is staggered with the sidewall of the overlying electrode layer 176, but substantially aligned with the sidewall of the underlying electrode layer 174. Further, as... Figure 2As shown, in the semiconductor die 200, the electrode layers 172 and 176 of the capacitor structure 270 are electrically connected to the same bonding conductor 194; while the electrode layer 174 of the capacitor structure 270 is electrically connected to another bonding conductor 194.

[0049] like Figures 1A to 1I As shown, in the semiconductor die 100, the capacitor structure 170 is formed after the redistribution layer 150 is formed. However, the present invention is not limited thereto. In some alternative embodiments, the capacitor structure 170 may be formed before the redistribution layer 150 is formed. The following will be combined with... Figure 3 and Figure 4 Other embodiments are described.

[0050] Figure 3 This is a schematic cross-sectional view of a semiconductor die 300 according to some alternative embodiments of the present invention. Figure 3 The semiconductor die 300 shown is Figure 1I The semiconductor die 100 shown is similar; therefore, the same reference numerals are used to refer to the same or similar parts, and their detailed description will be omitted here. The differences between semiconductor die 300 and semiconductor die 100 will be described below.

[0051] refer to Figure 3 In the semiconductor die 300, the capacitor structure 170 is disposed between the interconnect structure 120 and the redistribution layer 150, and is covered by the passivation layer 140. Specifically, as Figure 3 As shown, in the semiconductor die 300, multiple bonding conductors 194, which are electrically and physically in contact with the capacitor structure 170 and serve as multiple electrode connectors of the capacitor structure 170, extend perpendicularly along the Z direction through the gap-filling dielectric layer 160, passivation layer 140, and capacitor structure 170, and sit on multiple conductive patterns 122 of the interconnect structure 120. Furthermore, as... Figure 3 As shown, in the semiconductor die 300, all of the plurality of bonding conductors 194 are situated on and in physical contact with the plurality of conductive patterns 122 of the interconnect structure 120. However, the present invention is not limited thereto. In some alternative embodiments, such as Figure 4 As shown, in the semiconductor die 400, some bonding conductors 194 are situated on and physically in contact with the redistribution layer 150. Specifically, as... Figure 4 As shown, in the semiconductor die 400, the bonding conductor 194, which is not used as an electrode connector in the capacitor structure 170, vertically passes through the gap-filling dielectric layer 160 to establish an electrical connection with the redistribution layer 150. Because... Figure 4 The semiconductor die 400 shown is Figure 3The semiconductor die 300 shown is similar, therefore the same reference numerals are used to refer to the same or similar parts, and their detailed description is omitted here.

[0052] In some embodiments, the semiconductor die 100 can be used in a semiconductor package. For example, the semiconductor die 100 can be assembled with other components to form a semiconductor package. In some embodiments, the semiconductor package is a three-dimensional integrated circuit (3D-IC) package. In some embodiments, the semiconductor package is a system-on-integrated circuit (SoIC) package, etc. The manufacturing process of the semiconductor package utilizing the semiconductor die 100 will be described below.

[0053] Figures 5A to 5H A schematic cross-sectional view is shown of various stages of a method for manufacturing a semiconductor package SP according to some embodiments of the present invention.

[0054] refer to Figure 5A A semiconductor substrate 510 is provided. The semiconductor substrate 510 can be used as a carrier for forming or placing subsequent layers / constructions thereon. The semiconductor substrate 510 may include one or more devices 512 adjacent to the top surface of the semiconductor substrate 510. Devices 512 may include integrated circuit devices, such as transistors, diodes, resistors, capacitors, etc.

[0055] Continue to refer to Figure 5A An interconnect structure 520 is formed on a semiconductor substrate 510, and vias 524 are formed penetrating the interconnect structure 520 to extend into a portion of the semiconductor substrate 510. In some embodiments, the interconnect structure 520 includes a plurality of dielectric layers 521, a plurality of conductive patterns 522, and a plurality of etch stop layers 523, and the plurality of conductive patterns 522 are electrically connected to a plurality of devices 512. In some embodiments, a sealing ring 530 is formed penetrating the interconnect structure 520. In some embodiments, the sealing ring 530 is formed of one or more materials that are the same as the material of the plurality of conductive patterns 522. The sealing ring 530 serves as a structural support element to enhance structural rigidity during cutting or trimming. In some embodiments, the sealing ring 530 is an electrically floating element. It should be understood that the number and configuration of the plurality of dielectric layers 521, the plurality of etch stop layers 523, and the plurality of conductive patterns 522 are merely exemplary and are not intended to limit the scope of the present invention.

[0056] Continue to refer to Figure 5A A passivation layer 540 is formed on the interconnect structure 520. The material of the passivation layer 540 may include silicon oxide, silicon nitride, silicon oxynitride, USG, etc. Furthermore, refer to... Figure 5AA redistribution layer 550 is formed, penetrating the passivation layer 540, to electrically connect to the interconnect structure 520 and the via 524. In some embodiments, the redistribution layer 550 includes a plurality of conductive patterns, such as conductive pads and / or conductive wiring. The plurality of conductive patterns of the redistribution layer 550 may have a different pitch or line / spacing (L / S) than the plurality of conductive patterns 522 of the interconnect structure 520. In some embodiments, the material of the redistribution layer 550 includes copper, aluminum, aluminum-copper, or any other suitable conductive material. In some embodiments, the material of the redistribution layer 550 includes aluminum or copper-doped aluminum, wherein the copper doping concentration is from 0.001% to about 50%. In one embodiment, the copper doping concentration is about 0.5%.

[0057] Continue to refer to Figure 5A A gap-filling dielectric layer 560 is formed on the passivation layer 540, and the gap-filling dielectric layer 560 covers the redistribution layer 550. In some embodiments, the gap-filling dielectric layer 560 fills the gaps between a plurality of conductive patterns of the redistribution layer 550 to provide a substantially flat top surface. In some embodiments, a planarization process is performed on the gap-filling dielectric layer 560 to provide a substantially flat top surface. The planarization process may include performing a CMP process. In some embodiments, the gap-filling dielectric layer 560 is formed by CVD (e.g., plasma-enhanced CVD, HDPCVD, or MOCVD) or PVD. In some embodiments, the material of the gap-filling dielectric layer 560 may include a dielectric material, such as SiO, SiN, or SiON.

[0058] Continue to refer to Figure 5A An etch stop layer 582 and a dielectric layer 592 are sequentially formed over the gap-filling dielectric layer 560. In some embodiments, the dielectric layer 592 is configured to be hybrid-bonded or fused-bonded to another dielectric layer. In such embodiments, the dielectric layer 592 is referred to as a bonding dielectric layer. In some embodiments, the dielectric layer 592 comprises an oxide-based layer. In some embodiments, the dielectric layer 592 comprises silicon oxide, silicon oxynitride, or any suitable material configured for hybrid-bonding or fused bonding. In some embodiments, the dielectric layer 592 comprises a polymer, such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc.

[0059] Continue to refer to Figure 5AA bonding conductor 594 is formed to electrically connect with the redistribution layer 550. The material of the bonding conductor 594 may be or include copper or other suitable conductive materials. Furthermore, in some embodiments, the bonding conductor 594 may optionally include a barrier layer (not shown) on its outer surface to prevent atomic diffusion between multiple elements. For example, the material of the barrier layer may be or include tungsten (W), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), combinations thereof, or other suitable materials. It should be understood that the number of bonding conductors 594 is merely exemplary and not intended to limit the scope of the invention. That is, more than one bonding conductor 594 may also be formed on the redistribution layer 550. In some embodiments, the bonding conductor 594 may be an under-bump metallization (UBM) pad for mounting conductive connectors (i.e., Figure 5H The bump connector 902 shown.

[0060] like Figure 5A As shown, due to the formation of the etch stop layer 582, the bonding conductor 594 may include a bottom portion formed to physically contact the redistribution layer 550 through the gap-filling dielectric layer 560, and a top portion formed within the dielectric layer 592 and wider than the bottom portion. However, the present invention is not limited thereto. In some alternative embodiments, the bonding conductor 594 may be formed as a single portion having continuous sidewalls. Furthermore, as Figure 5A As shown, the bonding conductor 594 can be exposed through the top surface of the dielectric layer 592.

[0061] Continue to refer to Figure 5A A bonding layer 596 is formed on the dielectric layer 592 and covers the bonding conductor 594. In some embodiments, the bonding layer 596 may include an oxide-based layer having an oxide-based bonding surface.

[0062] Continue to refer to Figure 5A The monomerization process is performed along multiple dicing lines to form multiple monomerized semiconductor dies 500. It should be noted that the above manufacturing process is part of a wafer-level packaging process, although... Figure 5A The illustration shows a monomerized semiconductor die 500, but those skilled in the art will understand that multiple semiconductor dies 500 are obtained after the monomerization process. In some embodiments, the monomerization process includes a dicing or sawing process. In subsequent processes, the monomerized semiconductor die 500 may, for example, be disposed on a packaging substrate or other components as required.

[0063] refer to Figure 5BA carrier 800A is provided, and a semiconductor die 500 is bonded to the carrier 800A. In some embodiments, a bonding layer 430 is formed on the carrier 800A. The bonding layer 430 may comprise an oxide-based layer having an oxide-based bonding surface. In some embodiments, a bonding layer 596 is fused to the bonding layer 430. Before bonding the semiconductor die 500 to the carrier 800A, an alignment mark 92 may be located in the bonding layer 430. Viewed from a top angle (i.e., along direction Z), the alignment mark 92 may not overlap with the semiconductor die 500.

[0064] refer to Figure 5C A dielectric structure 620 is formed to cover the bonding layer 430 and laterally encapsulate the semiconductor die 500 along direction X, and the semiconductor substrate 510 is thinned to expose the via 524. In some embodiments, a CMP process may be performed to remove portions of the semiconductor substrate 510, portions of the dielectric structure 620, and portions of the via 524 to expose a portion of the via 524 from the surface of the semiconductor substrate 510. The dielectric structure 620 may be a gap-filling dielectric material (e.g., an oxide material formed from tetraethoxysilane (TEOS) or other suitable dielectric material) formed by a deposition process (e.g., CVD, PVD, or other suitable deposition process).

[0065] refer to Figure 5D A bonding structure 420 is formed on the semiconductor substrate 510 and the dielectric structure 620. In detail, as shown... Figure 5D As shown, the bonding structure 420 includes a bonding layer 422 and a plurality of bonding conductors 424 embedded in the bonding layer 422. Furthermore, as... Figure 5D As shown, one of a plurality of bonding conductors 424 is formed to connect to a via 524. The bonding layer 422 may comprise an oxide-based layer having an oxide-based bonding surface. The bonding conductors 424 may be exposed through the top surface of the oxide-based layer (e.g., the oxide-based bonding surface). It should be understood that the number of bonding conductors 424 is merely exemplary and is not intended to limit the scope of the invention.

[0066] refer to Figure 5E Semiconductor die 100 is bonded to semiconductor die 500. Although Figure 5ESemiconductor die 100 is shown bonded to semiconductor die 500; however, those skilled in the art will understand that semiconductor dies 200 to 400 may also be selected to be bonded to semiconductor die 500. In some embodiments, the dielectric layer 192 of semiconductor die 100 is bonded to the bonding layer 422 of bonding structure 420. In some embodiments, the dielectric layer 192 of semiconductor die 100 is fused to bonding layer 422. In some embodiments, the bonding conductor 194 of semiconductor die 100 is in physical contact with and bonded to the bonding conductor 424 of bonding structure 420. That is, dielectric layer 192 and bonding conductor 194 may be collectively referred to as the bonding structure of semiconductor die 100, and semiconductor die 100 is bonded to semiconductor die 500 through the bonding structure 420 and the bonding structure of semiconductor die 100.

[0067] In detail, such as Figure 5E As shown, the bonding interface between the bonding structure 420 and the bonding structure of the semiconductor die 100 includes a metal-to-metal bonding interface and a dielectric-to-dielectric bonding interface. The metal-to-metal bonding interface is located between the bonding conductor 194 and the bonding conductor 424, while the dielectric-to-dielectric bonding interface is located between the dielectric layer 192 and the bonding layer 422. That is, the bonding structure of the semiconductor die 100 and the bonding structure 420 are hybridly bonded.

[0068] In some embodiments, such as Figure 5E As shown, the support die 70 can be selectively bonded to the semiconductor die 500. In some embodiments, the support die 70 includes a body portion 710 and a bonding layer 720. The body portion 710 may include a semiconductor substrate, including Si, Ge, SiGe, SiC, or other suitable semiconductor materials. The body portion 710 may be a bulk substrate or configured as a semiconductor on insulating layer (SOI) substrate. The bonding layer 720 may include an oxide-based layer having an oxide-based bonding surface. In some embodiments, the bonding layer 720 is fused to a bonding layer 422. In some embodiments, the oxide-based layer of the bonding layer 720 is fused to the oxide-based bonding surface of the bonding layer 422. Notably, by including the support die 70 bonded to the semiconductor die 500, the resulting semiconductor package SP exhibits a more uniform stress distribution and better heat dissipation efficiency.

[0069] refer to Figure 5FA dielectric structure 610 is formed to cover the bonding layer 422 and laterally encapsulate the semiconductor die 100 and the support die 70, and the bonding layer 410 is formed on the dielectric structure 610, the semiconductor die 100, and the support die 70. The bonding layer 410 may include an oxide-based layer with an oxide-based bonding surface. The materials and processes for forming the dielectric structure 610 may be similar to or the same as those for forming the dielectric structure 620, and will not be described further here.

[0070] refer to Figure 5G A bonding layer 440 is formed or disposed on a bonding layer 410, and a carrier 800B may be formed or disposed on a bonding layer 440. The bonding layer 440 may include an oxide-based layer having an oxide-based bonding surface. In some embodiments, the oxide-based layer of the bonding layer 440 is fused to the oxide-based bonding surface of the bonding layer 410. The carrier 800B may be a semiconductor substrate. (Continue referring to...) Figure 5G A portion of the carrier 800A, bonding layer 430, bonding layer 596, and dielectric structure 620 is removed to expose the bonding conductor 594.

[0071] refer to Figure 5H A passivation layer 900 is formed on the dielectric layer 592 and the bonding conductor 594, and a bump connector 902 is formed that penetrates the passivation layer 900 to electrically connect to the bonding conductor 594. This forms a semiconductor package SP. The passivation layer 900 may include silicon oxide, silicon nitride, silicon oxynitride, USG, etc. The bump connector 902 may be or may include a controlled collapse chip connection (C4) bump. It should be understood that the number of bump connectors 902 is merely exemplary and is not intended to limit the scope of the invention. That is, more than one bump connector 902 may be formed on the redistribution layer 550.

[0072] like Figure 5H As shown, in the semiconductor package SP, the semiconductor die 100 is bonded and electrically connected to the semiconductor die 500 via bonding conductors 194. That is, external electrical connections of the semiconductor die 100 can be achieved through bonding conductors 194. It should be noted that in the semiconductor die 100, the arrangement density of the plurality of bonding conductors 194 (including the plurality of vias 194b) capable of external electrical connections is lower than the arrangement density of the plurality of conductive patterns (including the plurality of vias V) in the redistribution layer 150. That is, as... Figure 6As shown, the opening area of ​​the passivation layer 180 (corresponding to the plurality of vias 194b) is smaller than the opening area of ​​the passivation layer 140 (corresponding to the plurality of vias V). In other words, the opening density of the passivation layer 180 is lower than that of the passivation layer 140. Thus, by arranging the passivation layer 180 with a lower opening density, the arrangement area of ​​the capacitor structure 170 embedded in the passivation layer 180 is increased. From another perspective, since the bonding conductor 194 enables external electrical connections, the bonding conductor 194 is the outermost conductive component of the semiconductor die 100. That is, the surface of the bonding conductor 194 exposed through the top surface of the dielectric layer 192 constitutes part of the outermost surface of the semiconductor die 100.

[0073] like Figure 5H As shown, in the semiconductor package SP, a bonding conductor 594 connects between the redistribution layer 550 and the bump connector 902. However, the present invention is not limited thereto. In some alternative embodiments, such as Figure 7 As shown, in the semiconductor package SP1, a bonding conductor 594 connects between a plurality of conductive patterns 522 and bump connectors 902 in the interconnect structure 520. Specifically, as Figure 7 As shown, the bottom portion of the bonding conductor 594 vertically penetrates the gap-filling dielectric layer 560 and passivation layer 540 to establish an electrical connection with the interconnect structure 520. Because... Figure 7 The semiconductor package SP1 shown is Figure 5H The semiconductor packages shown are similar, so the same reference numerals are used to refer to the same or similar parts, and their detailed descriptions are omitted here.

[0074] In addition, such as Figure 5H As shown, in the semiconductor package SP, there is no capacitor structure in the semiconductor die 500. However, the present invention is not limited thereto. In some alternative embodiments, such as Figure 8 As shown, in the semiconductor package SP2, the semiconductor die 500 includes a capacitor structure 570, and a plurality of bonding conductors 594 serve as a plurality of electrode connections for the capacitor structure 570. It should be noted that since the plurality of bonding conductors 594, made of copper, are used as the plurality of electrode connections for the capacitor structure 570, the junction resistance between the capacitor structure 570 and the plurality of electrode connections can be reduced. This improves the capacitance efficiency of the capacitor structure 570. Furthermore, it should be noted that for the semiconductor package (e.g., semiconductor package SP, semiconductor package SP1, semiconductor package SP2) or the semiconductor die 500, external electrical connections can be achieved through the plurality of bonding conductors 594 of the semiconductor die 500. Thus, by using the plurality of bonding conductors 594 that achieve external electrical connections as the plurality of electrode connections for the capacitor structure 570, the capacitance area of ​​the capacitor structure 570 is increased. The capacitor structure 570 can be coupled with… Figures 1C to 1FIt is manufactured using a similar process. Specifically, as... Figure 8 As shown, capacitor structure 570 is formed on gap-filling dielectric layer 560 and covered by passivation layer 580. The materials and processes for forming passivation layer 580 can be similar to or the same as those for forming passivation layer 180, and will not be described in detail here.

[0075] In addition, such as Figure 5H , Figure 7 and Figure 8 As shown, in semiconductor packages SP to SP2, the top die (i.e., semiconductor die 100) and the bottom die (i.e., semiconductor die 500) are joined to each other by dielectric-to-dielectric bonding of dielectric layer 192 and bonding layer 422, and metal-to-metal bonding of bonding conductor 194 and bonding conductor 424. That is, bonding conductor 194 can achieve external electrical connection through direct metal-to-metal bonding. However, the present invention is not limited thereto. In some alternative embodiments, the bonding conductor can achieve external electrical connection through joint terminals or metal wiring. Reference will be made below. Figures 9 to 12 Other embodiments are described.

[0076] refer to Figure 9 In the semiconductor package SP3, the semiconductor die 100, serving as the top die, is bonded and electrically connected to the semiconductor die 500, serving as the bottom die, via a plurality of connection terminals 702. For example, the connection terminals 702 are sandwiched between the bonding conductor 194 and the bonding conductor 424 to achieve an electrical connection between the semiconductor die 100 and the semiconductor die 500. More specifically, as... Figure 9 As shown, the connection terminal 702 is in physical contact with the bonding conductor 194 and the bonding conductor 424. In some embodiments, the connection terminal 702 is a solder joint formed via a ball placement process and / or a reflow process. The connection terminal 702 may be or may include microbumps, metal pillars, or C4 bumps. It is worth noting that the number of connection terminals 702 is merely exemplary and is not intended to limit the scope of this invention.

[0077] In some embodiments, such as Figure 9 As shown, the semiconductor package SP3 includes a dielectric structure 704 surrounding the semiconductor die 100, the semiconductor die 500, and the connection terminal 702. Further, in some embodiments, such as... Figure 9 As shown, the portion of the bump connector 902 near the dielectric layer 592 and the bonding conductor 594 is laterally surrounded by the dielectric structure 704. The dielectric structure 704 may be a molding compound formed by a mold injection process or other suitable process.

[0078] like Figure 9 As shown, in the semiconductor package SP3, the semiconductor die 500 does not contain a capacitor structure. However, the present invention is not limited thereto. In some alternative embodiments, such as Figure 10 As shown, in the semiconductor package SP4, the semiconductor die 500 includes a capacitor structure 570 (refer to the description above). Figure 8 Furthermore, multiple bonding conductors 594 serve as multiple electrode connectors for the capacitor structure 570.

[0079] Furthermore, such as Figure 9 As shown, in the semiconductor package SP3, only the top die includes a capacitor structure, while... Figure 10 As shown, in the semiconductor package SP4, both the top die and the bottom die include capacitor structures. However, this invention is not limited to this. In some alternative embodiments, in the semiconductor package, the top die may not include a capacitor structure, while the bottom die may include a capacitor structure. Reference will be made below. Figures 11 to 12 Other embodiments are described.

[0080] Figure 11 This is a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present invention. Figure 11 The semiconductor package SP5 shown is Figure 10 The semiconductor package SP4 shown is similar to the one in the figures, therefore the same reference numerals are used to refer to the same or similar parts, and a detailed description thereof will be omitted here. The differences between semiconductor package SP5 and semiconductor package SP4 will be described below.

[0081] refer to Figure 11 The semiconductor package SP5 includes a semiconductor die 800 as the top die and a semiconductor die 500 as the bottom die. Semiconductor die 800 and... Figure 5H The semiconductor package 100 shown is similar, and the same reference numerals are used to refer to the same or similar components, and their detailed description is omitted here. The difference between semiconductor die 800 and semiconductor die 100 is that semiconductor die 800 does not have a capacitor structure, and the redistribution layer 150 enables external electrical connection with semiconductor die 500. That is, the conductive pattern of the redistribution layer 150 can be referred to as a bonding conductor. Furthermore, semiconductor die 800 is electrically connected to semiconductor die 500 via a connection terminal 702. For example, the connection terminal 702 is sandwiched between the bonding conductor 424 and the conductive pattern of the redistribution layer 150 to achieve the electrical connection between semiconductor die 800 and semiconductor die 500.

[0082] like Figure 11As shown, in the semiconductor package SP5, the connection terminal 702 is in direct contact with the bonding conductor 424. However, the present invention is not limited thereto. In some alternative embodiments, such as Figure 12 As shown, in the semiconductor package SP6, the connection terminal 702 is sandwiched between the bonding conductor 594 and the conductive pattern of the redistribution layer 150 to achieve an electrical connection between the semiconductor die 800 and the semiconductor die 500. That is, in the semiconductor package SP6, the bonding conductor 594 of the semiconductor die 500 can be externally electrically connected to the semiconductor die 800 through the connection terminal 702. On the other hand, in the semiconductor package SP6, the bump connector 902 is in direct contact with and electrically connected to the bonding conductor 424.

[0083] To increase the capacitance area of ​​the capacitor structure, the above embodiments of this invention use a bonding conductor capable of external electrical connection as the electrode connector of the capacitor structure. Furthermore, to reduce the junction resistance of the capacitor structure, the above embodiments of this invention use a bonding conductor made of copper as the electrode connector of the capacitor structure.

[0084] Figure 13 This is a schematic cross-sectional view of the package structure according to some embodiments of the present invention. (See reference) Figure 13 A package structure PS is provided, comprising a first component C1 and a second component C2 disposed on the first component C1. The first component C1 may be or may include an interposer (organic or inorganic), a package substrate, a printed circuit board (PCB), and / or other carriers capable of carrying integrated circuits. The second component C2 mounted on the first component C1 may be or may include: logic chips / dies (e.g., central processing unit (CPU), graphics processing unit (GPU), core chiplet die (CCD), input / output die (IOD), memory chips / dies (e.g., static random access memory (SRAM)), passive components (e.g., capacitors, inductors), and combinations thereof. The second component C2 may be similar. Figure 5H and Figures 7 to 12Any of the plurality of semiconductor packages. For example, one of semiconductor packages SP to SP6 may be electrically coupled to the first component C1 via a plurality of terminals CT. The terminals CT may be the aforementioned bump connector 902. Alternatively, in some embodiments, the terminals CT are terminals larger than the bump connector 902, and a reflow process may be performed on the terminals CT to bond the second component C2 to the first component C1. Furthermore, in some embodiments, more than one semiconductor package (e.g., any combination of the plurality of semiconductor packages described above) may be arranged side by side and electrically coupled to the first component C1.

[0085] In some embodiments, an underfill (not shown) may be selectively formed between the gap of the first member C1 and the second member C2 to at least laterally cover the plurality of terminals CT. The bonding strength between the first member C1 and the second member C2 is enhanced due to the underfill. The underfill can be any acceptable material, such as polymers, epoxy resins, molded underfill, etc. In one embodiment, the underfill can be formed by underfill dispensing, capillary flow processes, or any other suitable method.

[0086] Other packaging technologies can also be used to form the package structure PS, and this invention does not limit this. For example, the package structure PS can be formed using wafer-level packaging (WLP), co-wafer-on-substrate (CoWoS) technology, chip-on-chip-on-substrate (CoCoS) technology, integrated fan-out, etc. The package structure PS can be part of an electronic system, used in, for example, computers (e.g., high-performance computers), computing devices used in conjunction with artificial intelligence systems, wireless communication devices, computer-related peripherals, entertainment devices, etc. It should be noted that other electronic applications are also possible.

[0087] According to an embodiment, a semiconductor die includes a semiconductor substrate, an interconnect structure, a capacitor structure, a redistribution layer, and a bonding conductor. The interconnect structure is disposed on the semiconductor substrate. The capacitor structure is disposed on the interconnect structure. The redistribution layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The bonding conductor is in electrical and physical contact with the capacitor structure at its sidewalls, wherein the redistribution layer is located at a lower level than the bonding conductor. In some embodiments, the bonding conductor sits on the interconnect structure and is electrically connected to the interconnect structure. In some embodiments, the material of the redistribution layer is different from the material of the bonding conductor. In some embodiments, the material of the redistribution layer includes aluminum, and the material of the bonding conductor includes copper. In some embodiments, the bonding conductor sits on the redistribution layer and is electrically connected to the redistribution layer. In some embodiments, the semiconductor die further includes: a dielectric layer covering the redistribution layer; and a passivation layer disposed on the dielectric layer and covering the capacitor structure. In some embodiments, the capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer between the first electrode layer and the second electrode layer, and the sidewall of the bonding conductor is in electrical and physical contact with one of the first electrode layer and the second electrode layer. In some embodiments, the semiconductor die further includes a dielectric layer laterally surrounding the bonding conductor, wherein the surface of the bonding conductor connected to the sidewall of the bonding conductor is exposed by the dielectric layer.

[0088] According to an embodiment, a semiconductor package includes a first semiconductor die and a second semiconductor die. The second semiconductor die is electrically connected to the first semiconductor die, wherein the second semiconductor die includes a semiconductor substrate, an interconnect structure, a bonding conductor, a redistribution layer, and a capacitor structure. The interconnect structure is disposed on the first semiconductor substrate. The bonding conductor is disposed on the interconnect structure and electrically connected to the interconnect structure. The redistribution layer is disposed on the interconnect structure and is located at a level lower than the bonding conductor. The capacitor structure laterally surrounds the sidewalls of the bonding conductor and is electrically connected to the sidewalls of the bonding conductor. In some embodiments, the semiconductor package further includes a bonding structure electrically connected to and sandwiched between the first semiconductor die and the second semiconductor die, wherein the bonding structure is in physical contact with the bonding conductor. In some embodiments, the second semiconductor die further includes: a dielectric layer laterally surrounding the bonding conductor of the second semiconductor die, wherein the surface of the bonding conductor of the second semiconductor die, which is connected to the sidewall of the bonding conductor of the second semiconductor die, is exposed by the dielectric layer; and the bonding structure includes: a bonding conductor; and a bonding layer laterally surrounding the bonding conductor of the bonding structure, wherein the bonding conductor of the bonding structure is in physical contact with the bonding conductor of the second semiconductor die, and the bonding layer is in physical contact with the dielectric layer. In some embodiments, the bonding structure includes a connection terminal in physical contact with the bonding conductor of the second semiconductor die. In some embodiments, the first semiconductor die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate of the first semiconductor die; a bonding conductor disposed on the interconnect structure of the first semiconductor die and electrically connected to the interconnect structure of the first semiconductor die; and a capacitor structure laterally surrounding the sidewall of the bonding conductor of the first semiconductor die and electrically connected to the sidewall of the bonding conductor of the first semiconductor die. In some embodiments, the semiconductor package further includes: a bump connector in physical contact with the bonding conductor of the first semiconductor die. In some embodiments, the bonding conductor of the second semiconductor die is situated on and electrically connected to the interconnect structure of the second semiconductor die. In some embodiments, the material of the redistribution layer is different from the material of the bonding conductor of the second semiconductor die, and the bonding conductor of the second semiconductor die is situated on and electrically connected to the redistribution layer. In some embodiments, the capacitor structure of the second semiconductor die includes a first electrode layer, a second electrode layer, and a dielectric layer between the first electrode layer and the second electrode layer, and the sidewall of the bonding conductor of the second semiconductor die is in electrical and physical contact with one of the first electrode layer and the second electrode layer.

[0089] According to an embodiment, a method of manufacturing a semiconductor die includes the following processes: forming an interconnect structure on a semiconductor substrate; forming a capacitor structure on the interconnect structure; forming a redistribution layer electrically connected to the interconnect structure on the interconnect structure; and forming a bonding conductor perpendicularly through the capacitor structure to be electrically connected to the capacitor structure at a sidewall of the bonding conductor, wherein the bonding conductor is formed at a level higher than the redistribution layer. In some embodiments, the redistribution layer is formed prior to the formation of the capacitor structure, and the material of the redistribution layer is different from the material of the bonding conductor. In some embodiments, the method of manufacturing a semiconductor die further includes forming a passivation layer covering the capacitor structure, wherein the redistribution layer is formed to pass through the passivation layer and be electrically connected to the interconnect structure, and the material of the redistribution layer is different from the material of the bonding conductor.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor die, characterized in that, include: Semiconductor substrate; An interconnect structure is disposed on the semiconductor substrate; A capacitor structure is disposed on the internal interconnection structure; A redistribution layer is disposed on the interconnect structure and electrically connected to the interconnect structure; as well as The bonding conductor is in electrical and physical contact with the capacitor structure at the sidewall of the bonding conductor, wherein the redistribution layer is located at a level lower than the bonding conductor.

2. The semiconductor die according to claim 1, characterized in that, The bonding conductor sits on the interconnect structure and is electrically connected to the interconnect structure.

3. The semiconductor die according to claim 1, characterized in that, The material of the redistribution layer is different from the material of the bonding conductor.

4. The semiconductor die according to claim 1, characterized in that, The capacitor structure includes a first electrode layer, a second electrode layer, and a dielectric layer between the first electrode layer and the second electrode layer, and the sidewall of the bonding conductor is in electrical and physical contact with one of the first electrode layer and the second electrode layer.

5. The semiconductor die according to claim 1, characterized in that, Also includes: A dielectric layer laterally surrounds the bonding conductor, wherein the surface of the bonding conductor, which is connected to the sidewall of the bonding conductor, is exposed by the dielectric layer.

6. A semiconductor package, characterized in that, include: First Semiconductor Chip; as well as A second semiconductor die is electrically connected to the first semiconductor die, wherein the second semiconductor die comprises: Semiconductor substrate; An interconnect structure is disposed on the semiconductor substrate; A bonding conductor is disposed on the interconnect structure and electrically connected to the interconnect structure; A redistribution layer, disposed on the interconnect structure and located at a level lower than the bonding conductor; and A capacitor structure that laterally surrounds the sidewalls of the bonding conductor and is electrically connected to the sidewalls of the bonding conductor.

7. The semiconductor package according to claim 6, characterized in that, Also includes: A bonding structure is electrically connected to and sandwiched between the first semiconductor die and the second semiconductor die, wherein the bonding structure is in physical contact with the bonding conductor.

8. The semiconductor package according to claim 6, characterized in that, The first semiconductor die includes: Semiconductor substrate; An interconnect structure is disposed on the semiconductor substrate of the first semiconductor die; A bonding conductor is disposed on the interconnect structure of the first semiconductor die and electrically connected to the interconnect structure of the first semiconductor die; and A capacitor structure laterally surrounds the sidewall of the bonding conductor of the first semiconductor die and is electrically connected to the sidewall of the bonding conductor of the first semiconductor die.

9. The semiconductor package according to claim 6, characterized in that, The bonding conductor of the second semiconductor die is located on the interconnect structure of the second semiconductor die and is electrically connected to the interconnect structure of the second semiconductor die.

10. The semiconductor package according to claim 6, characterized in that, The material of the redistribution layer is different from the material of the bonding conductor of the second semiconductor die, and the bonding conductor of the second semiconductor die is located on the redistribution layer and electrically connected to the redistribution layer.

Images