A system-level power module MOS and substrate delamination improved packaging structure

Abstract

This utility model relates to an improved packaging structure for a system-level power module with a delamination design between the MOS and the substrate. The structure includes a substrate and a MOS. The upper surface of the substrate has solder joints and a solder mask layer. The MOS is soldered to the substrate via these solder joints. A molding compound fills the space between the MOS and the substrate. The solder mask layer has grooves corresponding to the MOS, and the depth of these grooves is greater than the maximum outer diameter of the resin particles in the molding compound. This allows the resin particles in the molding compound to fill the gap between the MOS and the substrate when residual solder material is removed from the bottom of the MOS. This utility model ensures that the EMC (Electromagnetic Compound) fully fills the gap between the MOS and the substrate during molding, guaranteeing the bonding strength between the MOS and the substrate after packaging. Subsequent processes prevent delamination and cracking between the MOS and the substrate, as well as the molding compound formed by the EMC, thus ensuring the normal function of the MOS in the system-level power module and guaranteeing the reliability and quality of the system-level power module product.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a packaging structure with improved layering of the MOS and substrate in a system-level power module. Background Technology

[0002] Semiconductor (chip) packaging is currently a research hotspot both domestically and internationally. System-in-Package (SIP) packages with a molding thickness of > / = 2.0mm are semiconductor devices that highly integrate multiple electronic components together to form a complete or near-complete power supply function. They offer a more efficient, reliable, compact, and easy-to-use solution compared to building circuits with isolated electronic components. For power modules, the packaging process involves SMT, DEFLUX, LA, molding, SBM, and dicing. Molding involves pressing epoxy molding compound (EMC) into a mold cavity, embedding the chip and all other electronic components within the EMC (without voids or delamination). After the EMC cross-links and cures within the mold cavity, the entire device becomes a semiconductor device with a specific structural shape. The purpose of molding is to protect the chip and other electronic components from damage caused by various environmental factors such as moisture, dust, and physical impact.

[0003] During molding, air needs to be expelled from the mold cavity. Epoxy resin encapsulates all electronic components, MOSFETs, and the substrate, and then cures at high temperatures. The gap between the MOSFET and the substrate directly affects the EMC filling. Incomplete EMC filling creates voids between the MOSFET and the substrate, affecting the bonding strength between the EMC and the substrate / MOSFET. In subsequent processes, after multiple high-temperature treatments, the internal and external pressure differences created by these voids, along with the mutual influence of stresses on the MOSFET, EMC, and substrate during the high-temperature and cooling stages, can lead to cracking and detachment between the MOSFET, substrate, and EMC, directly impacting the function and reliability of the entire semiconductor device.

[0004] Therefore, during the packaging of power modules, the bottom space is typically increased by optimizing the height of the solder material at the bottom of the MOSFET, while the DEFLUX parameter is optimized to ensure the cleanliness of the bottom space of the MOSFET, thus guaranteeing the filling and bonding strength of the EMC. However, it is difficult to precisely control the amount of solder material at the bottom of the MOSFET, resulting in inconsistent bottom heights after soldering (e.g., a minimum height of 11.5μm). Since the maximum size of EMC resin particles is 20μm, if the bottom space of the MOSFET is not thoroughly cleaned, the EMC resin particles cannot adequately fill the gap between the MOSFET and the substrate, leading to the quality problems mentioned above, which require improvement. Utility Model Content

[0005] The purpose of this invention is to address the shortcomings in the aforementioned background technology by providing a solution that can improve the EMC filling between the MOS and the substrate, thereby enhancing the packaging quality of semiconductor devices.

[0006] To achieve the above objectives, this utility model provides a system-level power module MOS and substrate layered improved packaging structure, including a substrate and a MOS; the upper surface of the substrate is provided with solder joints and an oil-curing layer, the MOS is soldered to the substrate through the solder joints, and a molding compound is filled between the MOS and the substrate; the oil-curing layer is provided with grooves, the grooves are corresponding to the MOS, and the depth of the grooves is greater than the maximum outer diameter of the resin particles of the molding compound, so that when the solder material remaining at the bottom of the MOS is removed, the gap between the MOS and the substrate can be fully filled by the resin particles of the molding compound.

[0007] Furthermore, the depth of the groove is greater than 20 μm.

[0008] Furthermore, the corresponding position of the green oil layer is partially or completely removed along the thickness direction to form the groove.

[0009] Furthermore, the green varnish layer includes a first green varnish layer and a second green varnish layer, the first green varnish layer is bonded to the substrate of the substrate, the second green varnish layer is bonded to the first green varnish layer, and the groove is formed in the second green varnish layer.

[0010] Furthermore, the thickness of the second green oil layer is set to be 20 μm or more.

[0011] Furthermore, the depth of the groove is minimum near the solder joint of the substrate and gradually increases as it moves away from the solder joint of the substrate.

[0012] Furthermore, the depth of the groove is set sequentially to 25μm, 30μm, 35μm, and 40μm from the solder joint position of the substrate outwards.

[0013] The above-mentioned solution of this utility model has the following beneficial effects:

[0014] The improved packaging structure of the system power module MOS and substrate provided by this utility model, through the grooves opened in the green oil layer on the substrate, enables the EMC to fully fill the gap between the MOS and the substrate during molding, ensuring the bonding force between the MOS and the substrate after packaging. In subsequent processes, there will be no delamination or cracking between the MOS and the substrate, or between the EMC and the molding body, thus ensuring the normal and reliable function of the MOS in the system power module, thereby ensuring the reliability and quality of the system power module product.

[0015] Other beneficial effects of this invention will be described in detail in the following detailed description section. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall structure of this utility model;

[0017] Figure 2 This is a schematic diagram of the overall structure of the present invention (first green oil layer and second green oil layer);

[0018] Figure 3 This is a schematic diagram of the overall structure of this utility model (groove depth stepped distribution).

[0019] [Explanation of Labels in the Attached Image]

[0020] 1-Substrate; 2-MOS; 3-Metal heat sink; 4-Solder joint; 5-Soil solder mask; 6-Groove; 7-First oil solder mask; 8-Second oil solder mask; 9-Encapsulation. Detailed Implementation

[0021] To make the technical problems, solutions, and advantages of this utility model clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0022] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0024] like Figure 1 As shown, this embodiment of the present invention provides a system-level power module MOS and substrate layered improved packaging structure, including substrate 1 and MOS2. MOS2, or Metal-Oxide-Semiconductor Field-Effect Transistor, serves as the core power switch in the power module, responsible for efficiently controlling and managing electrical energy. MOS2 has a large metal heat sink 3 for heat dissipation. There is a physical connection (electrical connection) between the metal heat sink 3 and substrate 1, enabling high-current conduction between the solder joints 4 of the metal heat sink 3 (drain plate) and substrate 1. Soldering materials need to be removed from the solder joints 3 of the metal heat sink 3 that do not correspond to those of substrate 1 to ensure sufficient EMC filling between MOS2 and substrate 1. After curing, this ensures a strong connection between the metal heat sink 3 and substrate 1, preventing cracking or other defects.

[0025] In this embodiment, a green solder mask layer 5 is formed on the upper surface of the substrate 1. The EMC (Electromagnetic Compound) contacts both the green solder mask layer 5 and the metal heat sink 3 between the MOS 2 and the substrate 1. When the gap between the green solder mask layer 5 and the metal heat sink 3 is less than 20 μm, the resin particles of the EMC cannot fill this gap. Therefore, in this embodiment, a groove 6 is formed in the green solder mask layer 5 on the upper surface of the substrate 1. The groove 6 corresponds to the metal heat sink 3 of the MOS 2, and the depth of the groove 6 is set to be greater than 20 μm. Therefore, after the SMT and DEFLUX processes, the minimum gap between the bottom of the groove 6 and the metal heat sink 3 is greater than 31.5 μm, exceeding the maximum outer diameter of the EMC resin particles (20 μm). Thus, the EMC can fully fill the gap between the MOS 2 and the substrate 1, ensuring the bonding strength between the MOS 2 and the substrate 1.

[0026] It should be noted that the groove 6 in the green solder mask layer 5 on the upper surface of the substrate 1 can be formed by directly removing the green solder mask layer 5. Depending on the thickness of the green solder mask layer 5, the green solder mask layer 5 at the location of the groove 6 may be partially or completely removed. After complete removal, the PP layer or ceramic layer of the substrate 1 is exposed, thereby increasing the gap between the MOS 2 and the substrate 1.

[0027] It should be noted that the solution provided in this embodiment mainly targets the connection position between MOS2 and substrate 1. For chips or other electronic components, when the soldering material removal effect is poor or the EMC filling effect is poor, it is also possible to consider creating a groove 6 in the green solder mask layer 5 on the upper surface of substrate 1 at the corresponding position, so that EMC can fully fill the gap between the corresponding electronic component and substrate 1. Of course, in the actual process, when the EMC filling effect between the corresponding electronic component and substrate 1 is good, it is not necessary to remove the green solder mask layer 5 at the corresponding position to form a groove 6, which can ensure reliability while simplifying the process and saving costs.

[0028] The green solder mask 5 uses a liquid photoresist, which is an acrylic oligomer. The green solder mask 5 is applied to the surface of the substrate 1 to form a solder mask layer on the unsoldered circuitry and substrate, protecting the formed circuit patterns. It should be noted that the solder mask layer for the power module is typically made of a black material; however, in this embodiment, it will still be referred to as "green solder mask 5" for consistency.

[0029] At the same time, such as Figure 2 As shown, in a preferred embodiment, the solder mask 5 on the upper surface of the substrate 1 includes a first solder mask 7 and a second solder mask 8. The first solder mask 7 is bonded to the PP layer of the substrate 1, and the second solder mask 8 is bonded to the first solder mask 7. The first solder mask 7, being the part bonded to the substrate 1, remains intact when the groove 6 is formed, functioning as a normal solder mask 5. The second solder mask 8 is removed at the corresponding position when the groove 6 is formed, thereby increasing the gap height between the MOS 2 and the substrate 1. It is understood that the thickness of the second solder mask 8 can be set to 20 μm or more. Therefore, when the corresponding position of the second solder mask 8 is removed, the depth of the resulting groove 6 is greater than 20 μm, achieving the aforementioned effect.

[0030] At the same time, such as Figure 3 As shown, as a further improvement, the depth of the groove 6 in this embodiment can be set in a stepped manner. For example, the depth of the groove 6 is smaller near the solder joint 4 (welded to MOS2) on the substrate 1, and gradually increases as it moves away from the solder joint on the substrate 1. Therefore, the gap between MOS2 and the substrate 1 gradually expands outward from the solder joint 4. Considering that the solder joint 4 is usually located at the center of MOS2, the gap gradually expands outward from the center, i.e., a gap distribution pattern that is low in the middle and high at the edges. Therefore, after the molten EMC flows in from the mold channel, it fills the gap between MOS2 and the substrate 1 from the outside in. The high gap at the edges brings low flow resistance, ensuring that the EMC flows in quickly. The decreasing gap height along the EMC flow direction makes the EMC flow rate gradually increase, which can better squeeze out the central gas and avoid voids.

[0031] In one specific embodiment, the depth of the groove 6 is set to 25μm, 30μm, 35μm and 40μm from the center to the outside, which not only reflects the form of the gap gradually expanding from the weld point 4 to the outside, but also meets the gap requirement of EMC full filling.

[0032] As can be seen from the above, the groove 6 is mainly formed on the substrate 1, so it can be directly completed by the substrate manufacturer. Especially for the scheme with the first green solder mask layer 7 and the second green solder mask layer 8, the substrate manufacturer can prefabricate the corresponding position and depth of the groove 6 based on customized requirements. For the packaging manufacturer, it can further optimize the process parameters to improve the bonding between MOS2 and substrate 1. For example, the cleaning parameters of the Deflux process (i.e., the solder material cleaning process parameters) can be improved. The solder material remaining on the bottom of MOS2 after soldering needs to be removed by a combination of chemical solution (saponifying agent) and deionized water and specific cleaning parameters. In one specific embodiment, the saponifying agent concentration is controlled at 3, and the cleaning parameter chain speed is controlled at 10mm / s. This combination can effectively remove the solder material residue on the bottom of MOS2 and ensure its cleanliness.

[0033] In summary, the improved packaging structure of the system power module MOS and substrate provided in this embodiment, through the groove 6 opened in the green oil layer 5 on the substrate 1, enables the EMC to fully fill the gap between MOS2 and substrate 1 during molding, ensuring the bonding force between MOS2 and substrate 1 after packaging. In subsequent processes, delamination and cracking will not occur between MOS2 and substrate 1, or between the EMC and the molding body 9, thus ensuring the normal and reliable function of MOS2 in the system power module, thereby ensuring the reliability and quality of the system power module product.

[0034] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0035] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A packaging structure for improving the layering of MOS and substrate in a system-level power module, characterized in that, The device includes a substrate and a MOSFET. The upper surface of the substrate is provided with solder joints and a solder mask layer. The MOSFET is soldered to the substrate through the solder joints. A molding compound is filled between the MOSFET and the substrate. The solder mask layer is provided with grooves, which are corresponding to the MOSFET. The depth of the grooves is greater than the maximum outer diameter of the resin particles of the molding compound, so that when the solder material remaining at the bottom of the MOSFET is removed, the gap between the MOSFET and the substrate can be fully filled by the resin particles of the molding compound.

2. The improved packaging structure for system-level power module MOS and substrate layering according to claim 1, characterized in that, The depth of the groove is greater than 20 μm.

3. The improved packaging structure for system-level power module MOS and substrate layering according to claim 1, characterized in that, The groove is formed by partially or completely removing the corresponding position of the green oil layer along the thickness direction.

4. The improved packaging structure for system-level power module MOS and substrate layering according to claim 1, characterized in that, The green varnish layer includes a first green varnish layer and a second green varnish layer. The first green varnish layer is bonded to the substrate of the substrate, and the second green varnish layer is bonded to the first green varnish layer. The groove is formed in the second green varnish layer.

5. The improved packaging structure for system-level power module MOS and substrate layering according to claim 4, characterized in that, The thickness of the second green oil layer is set to be 20 μm or more.

6. The improved packaging structure for system-level power module MOS and substrate layering according to any one of claims 1-5, characterized in that, The depth of the groove is minimum near the solder joint of the substrate and gradually increases as it moves away from the solder joint of the substrate.

7. The improved packaging structure for system-level power module MOS and substrate layering according to claim 6, characterized in that, The depth of the groove is set sequentially from the solder joint position of the substrate outwards to 25μm, 30μm, 35μm, and 40μm.

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