A power supply SIP package chip heat dissipation package structure

Abstract

The utility model discloses a power supply SIP encapsulation chip heat dissipation packaging structure, including substrate, inductance, main control chip, MOSFET chip, plastic package body and metal heat dissipation fin, inductance has at least one and is installed on the substrate outer surface, main control chip and MOSFET chip are WLCSP encapsulation chip, and are installed on the substrate front, and the plastic package body covers inductance, main control chip and MOSFET chip on the substrate, and the metal heat dissipation fin part is embedded in the plastic package body, and another part exposes the plastic package body outer surface, and the metal heat dissipation fin embedded portion is contacted through high heat dissipation conductive glue with the inductance back and the MOSFET chip front. The MOSFET chip of adopting WLCSP encapsulation eliminates the thermal resistance of original package, so that the metal heat dissipation fin directly contacts the MOSFET chip front heat dissipation through high heat conduction glue, and the heat generation part is shortened to the heat dissipation path of outside.

Description

Technical Field

[0001] This utility model specifically relates to a heat dissipation packaging structure for a power supply SIP packaged chip. Background Technology

[0002] As electronic devices become smaller, thinner, and higher-performance, metal-oxide-semiconductor field-effect transistors (MOSFETs) and inductors are the core power devices in power management system-in-in-chip (SIPs), generating a significant amount of heat during operation. If this heat cannot be dissipated in time, the chip junction temperature will rise, severely impacting system reliability, efficiency, and lifespan.

[0003] After the main control chip, MOSFET chip, and inductor are installed, a metal clip is mounted on the top surface of the MOSFET and inductor before encapsulation, ensuring the metal clip is exposed. This allows the MOSFET and inductor, which have very high heat dissipation, to conduct heat away from the molded body through the metal clip. Figure 1 As shown.

[0004] This technology has better heat dissipation than the metal clip fully encapsulated structure, but the MOSFET itself is a pre-packaged PDFN chip. The metal clip only contacts the PDFN molding compound and does not directly contact the chip, nor does it directly contact the heat source of the chip (silicon wafer). Therefore, its heat dissipation performance is not optimal. Utility Model Content

[0005] The technical problem to be solved by this invention is how to remove the molding compound on existing chips so that the metal heat sink can directly contact the heat source of the chip for heat dissipation.

[0006] To address the aforementioned technical problems, this utility model proposes a heat dissipation packaging structure for a power SIP packaged chip. The technical solution adopted is as follows: it includes a substrate, an inductor, a main control chip, a MOSFET chip, a molding compound, and a metal heat sink. At least one inductor is provided and mounted on the front side of the substrate. The main control chip and the MOSFET chip are WLCSP packaged chips and flip-chip mounted on the front side of the substrate. The metal heat sink is bonded to the front side of the inductor and the back side of the MOSFET chip using a high thermal conductivity adhesive. The molding compound encapsulates the inductor, main control chip, MOSFET chip, and metal heat sink on the substrate.

[0007] By incorporating a metal heat sink embedded in the plastic package, the heat sink is made in direct contact with the inductor and WLCSP packaged MOSFET chip on the substrate. This allows the heat generated by the inductor and MOSFET chip during operation to be dissipated directly through the metal heat sink.

[0008] In a preferred embodiment of the present invention, the metal heat sink includes a main body, which has a height difference between the two ends of the contact surface with the MOSFET chip and the inductor. The lower end of the contact surface is in contact with the back of the MOSFET chip, and the upper end of the contact surface is in contact with the front of the inductor.

[0009] By setting contact surfaces of metal heat sinks at different heights, the metal heat sinks can be adapted to the height of chips and inductors on the substrate and fit against their heat sources to achieve heat dissipation.

[0010] In a preferred embodiment of the present invention, the metal heat sink further includes conductive pillars disposed on the main body and connecting the back side of the MOSFET chip to the GND plane of the substrate.

[0011] By setting conductive pillars, the MOSFET chip is connected to the GND plane of the substrate, enabling the conductive pillars on the metal heat sink to achieve electrical performance while assisting in heat dissipation. A grounding path is provided through the large-area metal heat sink and low-inductive conductive pillars.

[0012] In a preferred embodiment of the present invention, the metal heat sink has an exposed surface that is exposed to the plastic encapsulation.

[0013] Heat dissipation is achieved by exposing the metal heat sink to the plastic encapsulation, allowing the exposed surface to contact the atmosphere.

[0014] In a preferred embodiment of the present invention, the exposed surface of the metal heat sink has a deep hole that runs along its thickness direction and corresponds to the back of the chip and the front of the inductor.

[0015] Deep holes of a specific depth are created in the metal heat sink to release thermal stress.

[0016] In a preferred embodiment of the present invention, the exposed surface of the metal heat sink and the outer surface of the plastic encapsulation body are on the same plane.

[0017] By placing the exposed surface of the metal heat sink on the same plane as the outer surface of the molded package, the space occupied by the metal heat sink is reduced, enabling the miniaturization of the SIP.

[0018] In a preferred embodiment of the present invention, the main control chip and the MOSFET chip are provided with a bottom filling protective layer.

[0019] By adding a bottom filler protective layer to the bottom of the main control chip and MOSFET chip, the bottom filler protective layer effectively absorbs the stress caused by the mismatch of thermal expansion coefficients between the chip and the substrate, improves the fatigue resistance of the solder joint, and ensures the long-term reliability of the product.

[0020] In a preferred embodiment of the present invention, a ball is provided on the side of the substrate away from the chip.

[0021] By setting up the ball, an external electrical and mechanical connection interface is formed, similar to an old-fashioned pin.

[0022] The advantages of this utility model compared with the prior art are: 1) The MOSFET chip using WLCSP packaging eliminates the thermal resistance of the original package, allowing the metal heat sink to directly contact the back of the MOSFET chip for heat dissipation through high thermal conductivity adhesive, thus shortening the heat dissipation path from the heat-generating part to the outside.

[0023] 2) The deep holes on the metal heat sink and the conductive pillars formed thereon not only dissipate heat, but also electrically connect the back of the MOSFET chip (usually the drain) to the GND plane of the substrate, simplifying wiring and providing a low-inductance grounding path. At the same time, the GND plane of the substrate is usually a huge copper layer with an area much larger than the chip itself. When the conductive pillars make electrical connections, they can dissipate the heat of the chip more evenly through the substrate.

[0024] 3) The bottom filler protective layer effectively absorbs the stress caused by the mismatch of thermal expansion coefficients between the flip chip and the substrate, improves the fatigue resistance of the solder joints, and ensures the long-term reliability of the product. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of an existing power supply SIP chip; Figure 2 This is a schematic diagram of the structure of the main control chip and MOSFET chip of the power supply SIP chip of this utility model after flip-chip assembly; Figure 3 This is a schematic diagram of the power supply SIP chip after all components are installed. Figure 4 This is a schematic diagram of the structure of the plastic-encapsulated power SIP chip of this utility model; Figure 5 This is a schematic diagram of the structure of the metal heat sink of this utility model.

[0026] Explanation of reference numerals in the attached diagram: 1. Substrate; 2. Main control chip; 3. MOSFET chip; 4. Inductor; 5. Bottom filler protective layer; 6. Metal heat sink; 61. Conductive pillar; 62. Deep hole; 7. High heat dissipation and conductive adhesive; 8. Molded enclosure; 9. Ball packing. Detailed Implementation

[0027] The existing power supply SIP chip consists of an inductor 4, a main control chip 2, and a MOSFET chip 3 mounted on a substrate 1, such as... Figure 1 As shown, this embodiment improves its heat dissipation packaging structure.

[0028] The following will refer to the appendix in the embodiments of this utility model. Figure 1-4The technical solutions in the embodiments of this utility model will be described in detail below.

[0029] Example 1

[0030] like Figure 2 , 3 As shown in Figures 4 and 5, a power supply SIP package chip heat dissipation packaging structure includes a substrate 1, an inductor 4, a main control chip 2, a MOSFET chip 3, a molding compound 8, and a metal heat sink 6, wherein... like Figure 2 and Figure 3 As shown: The main control chip 2 and MOSFET chip 3 are WLCSP packaged chips. The WLCSP packaged main control chip 2 and MOSFET chip 3 are flip-chip soldered to the front side of the substrate 1 using SMT equipment or FC equipment, so that the back side of the MOSFET chip 3, which is the heat source, is directly away from the substrate, so as to facilitate direct contact and heat dissipation with the metal heat sink 6.

[0031] By using WLCSP packaging technology to eliminate the thermal resistance of the original package (WLCSP packaging is an existing technology), the size of the components is greatly reduced. Inductor 4 is soldered to the front side of substrate 1 using SMT equipment.

[0032] like Figure 3 and 4 As shown: After the main control chip 2 and MOSFET chip 3 are soldered, a liquid underfill adhesive (usually an epoxy resin-based material) is applied along one or more edges of the chip using a precision dispensing device between the chip and the substrate 1. The adhesive fills the narrow gaps at the bottom of the chip, completely filling the space between each solder ball. Heating and curing at a specific temperature turns the adhesive into a hard solid, forming the underfill protective layer 5.

[0033] The bottom filler protective layer 5 effectively absorbs the stress caused by the mismatch in thermal expansion coefficients between the flip chip and the substrate, improves the fatigue resistance of the solder joints, and ensures the long-term reliability of the product.

[0034] like Figure 3 , 4As shown in Figure 5: The metal heat sink 6 is a custom-made heat sink, made entirely of copper. One side of its main body forms a contact surface with a height difference; the high-end contact surface is in contact with the front of the inductor 4, and the low-end contact surface is in contact with the back of the MOSFET chip 3. The side of its main body away from the contact surface is the exposed surface outside the plastic package. Conductive pillars 61 extend from the metal heat sink 6 perpendicular to its main body. The exposed surface of the metal heat sink 6 has holes of a specific depth along its thickness direction; these holes are deep holes 62. These deep holes 62 are used to improve the thermal stress of the package, which is converted from the MOSFET chip 3 to the W... The LCSP packaged chip has deep holes 62 corresponding to the front of the inductor 4 and the back of the MOSFET chip 3 on the substrate 1. Since the MOSFET chip 3 is converted into a WLCSP packaged chip, its back side has GND polarity. The metal heat sink 6 is attached to the back side of the MOSFET chip 3 and the front side of the inductor 4. The conductive pillars 61 of the metal heat sink 6 are connected to the GND plane of the substrate 1 to simplify the circuit and transfer the heat from the hot upper surface of the inductor 4 and the MOSFET chip 3 to the upper surface of the package, so that the back polarity of the MOSFET chip 3 is connected to the GND of the substrate.

[0035] The installation steps for the metal heat sink 6 are as follows: Beforehand, a high thermal conductivity adhesive 7 is applied to the back of the inductor 4 and the MOSFET chip 3 and at the connection point of the GND plane of the substrate 1. Then, the metal heat sink 6 is attached to the front of the inductor 4 and the back of the MOSFET chip 3, while the conductive post 61 is attached to the GND plane of the substrate 1, so that the conductive post 61 conducts the MOSFET chip 3 and the GND plane of the substrate 1. Finally, the high heat dissipation and conductivity adhesive 7 is solidified to fix the metal heat sink 6 to the front of the inductor 4, the back of the MOSFET chip 3, and the substrate 1.

[0036] Since the GND plane of substrate 1 is usually a huge copper layer with an area much larger than the chip itself, and the conductive post 51 is made of copper, when the metal heat sink 6 absorbs heat, part of the heat is dissipated directly through the exposed surface, and the other part is dissipated through the GND plane of substrate 1 through the conductive post 51. While electrically connecting the MOSFET chip 3 and the GND plane of substrate 1, the conductive post 51 can dissipate the heat of the chip more evenly through the substrate.

[0037] The metal heat sink 6 can be directly attached to the heat source on the back of the MOSFET chip 3 through a high heat dissipation and conductive adhesive, and the metal heat sink 6 dissipates heat from the MOSFET chip 3 and the inductor 4. Meanwhile, the conductive pillars 61 on the metal heat sink 6 can connect the back side (usually the drain) of the MOSFET chip 3 with the GND plane of the substrate 1, simplifying wiring and diffusing the heat on the metal heat sink 6 into the GND plane (auxiliary heat dissipation path) to form a three-dimensional heat dissipation effect.

[0038] The metal heat sink 6 has multiple deep holes 62 on its heat dissipation surface, which correspond to the front of the inductor 4 and the back of the MOSFET chip 3, respectively. This increases the release of thermal stress on the metal heat sink 6, the back of the inductor 4 and the MOSFET chip 3, and further enhances the heat dissipation performance of the components.

[0039] like Figure 5 As shown: The molding compound 8 covers all components on the substrate 1, while making the exposed surface of the metal heat sink 6 coplanar with the molding compound 8. After the molding compound 8 is melted, it is a liquid epoxy molding compound (EMC). The substrate 1 is placed in a pre-made mold. The upper cavity of the mold contacts and seals the heat dissipation exposed surface of the metal heat sink 6. The molten liquid epoxy molding compound (EMC) is injected into the mold cavity under extremely high pressure using injection molding equipment to fill every gap. Then, it is rapidly cured at high temperature to form the molding compound 8. The substrate 1 is then removed to form a power SIP package chip.

[0040] The above embodiments are only for illustrating the technical concept of this utility model and should not be used to limit the protection scope of this utility model. Any modifications made to the technical solution based on the technical concept proposed by this utility model shall fall within the protection scope of this utility model.

Claims

1. A heat dissipation packaging structure for a power supply SIP packaged chip, characterized in that: The device includes a substrate (1), an inductor (4), a main control chip (2), a MOSFET chip (3), a molding compound (8), and a metal heat sink (6). At least one inductor (4) is mounted on the front side of the substrate (1). The main control chip (2) and the MOSFET chip (3) are WLCSP packaged chips and flip-chip mounted on the front side of the substrate (1). The metal heat sink (6) is bonded to the front side of the inductor (4) and the back side of the MOSFET chip (3) by a high thermal conductivity adhesive (7). The molding compound (8) covers the inductor (4), the main control chip (2), the MOSFET chip (3), and the metal heat sink (6) on the substrate (1).

2. The heat dissipation packaging structure for a power SIP packaged chip according to claim 1, characterized in that: The metal heat sink (6) includes a main body, which has a height difference between the two ends of the contact surface of the main body and the MOSFET chip (3) and the inductor (4). The lower end of the contact surface is attached to the back of the MOSFET chip (3), and the upper end of the contact surface is attached to the front of the inductor (4).

3. The heat dissipation packaging structure for a power SIP packaged chip according to claim 2, characterized in that: The metal heat sink (6) also includes a conductive post (61) disposed on the main body and connecting the back of the MOSFET chip (3) to the GND plane of the substrate (1).

4. The heat dissipation packaging structure for a power SIP packaged chip according to claim 3, characterized in that: The metal heat sink (6) has an exposed surface that is exposed to the plastic encapsulation (8).

5. The heat dissipation packaging structure for a power supply SIP packaged chip according to claim 4, characterized in that: The exposed surface of the metal heat sink (6) has a deep hole (62) that runs along its thickness direction and corresponds to the back of the MOSFET chip (3) and the front of the inductor (4).

6. The heat dissipation packaging structure for a power SIP packaged chip according to claim 1, characterized in that: The main control chip (2) and the MOSFET chip (3) are provided with a bottom filling protective layer (5).

7. The heat dissipation packaging structure for a power SIP packaged chip according to claim 1, characterized in that: The substrate (1) has a ball (9) on its back side.

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