A vertical stacked chip package structure based on multiple cooperative heat dissipation paths

Abstract

This application provides a vertically stacked chip packaging structure based on multiple synergistic heat dissipation paths, including a heat sink cover with a flat top and microchannels for circulating coolant at the bottom; a substrate with a flat top and heat-dissipating solder balls at the bottom; a signal chip located between the heat sink cover and the substrate, with a thermal interface layer between the signal chip and the heat sink cover forming a first heat dissipation path; and a power chip located between the power chip and the substrate, connected to the substrate via high bumps to form a second heat dissipation path. According to the technical solution provided in this application, by setting microchannels within the heat sink cover, liquid cooling of the chip is effectively achieved. Furthermore, through the synergistic effect with the first and second heat dissipation paths, a three-dimensional, multi-layered heat dissipation system is constructed, effectively dispersing and dissipating the heat generated by the high-power-density chip, significantly reducing the chip junction temperature, and preventing thermal failure.

Description

Technical Field

[0001] This application relates to the field of integrated circuit packaging technology, specifically to a vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths. Background Technology

[0002] With the rapid development of artificial intelligence, high-performance computing and 5G communication, semiconductor packaging technology has entered the era of three-dimensional integration. 2.5D / 3D packaging achieves vertical interconnection of chips through through silicon vias (TSVs) and interposers, significantly improving integration density and signal transmission rate. However, the co-packaging of high-performance chips (such as GPUs and TPUs) and high-bandwidth memory (HBM) faces severe technical challenges.

[0003] Modern high-density integrated packaging in three dimensions faces thermal management failure issues. High-density stacking leads to a surge in heat flux density, with the local heat flux density of modern GPU chips exceeding 1 kW / cm². However, the thermal conductivity of traditional silicon interposers is only 150-180 W / (m•K), causing heat to accumulate beneath the logic chip. Actual measurement data shows that when HBM2e is integrated with a 7nm GPU through a silicon interposer, the chip junction temperature reaches 110-125℃, exceeding the safety threshold (105℃), which can cause thermal throttling or even burnout. The significant differences in thermal expansion coefficients between silicon, microbumps, and the organic substrate generate shear stress during temperature cycling, leading to TSV fracture and solder joint fatigue. Simultaneously, due to inefficient heat dissipation paths, existing solutions rely on external heat sinks or thermal interface materials (TIMs), resulting in high thermal resistance. Furthermore, the homogeneous materials of the interposer, as the primary heat conduction path, cannot meet the demands of high power density. Therefore, these problems urgently need to be addressed. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths.

[0005] This application provides a vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths, including... The heat dissipation cover has a flat top and a microchannel at the bottom for circulating coolant. The substrate has a flat top and heat dissipation solder balls at the bottom. A signal chip is located between the heat sink cover and the substrate, and a thermal interface layer is provided between the signal chip and the heat sink cover to form a first heat dissipation path; A power chip is located between the signal chip and the substrate, and is connected to the substrate by a high bump to form a second heat dissipation path.

[0006] Furthermore, The bottom of the heat dissipation cover is provided with an embedded groove; The microchannel is disposed inside the heat dissipation cover plate, at the bottom of the groove; The thermal interface layer is embedded in the groove, and its end face abuts against the signal chip.

[0007] Furthermore, An intermediary layer is also provided between the signal chip and the power chip; The intermediate layer is provided with through-hole and arrayed thermal TSVs for heat transfer between the signal chip and the power chip.

[0008] Furthermore, The signal chip and the interposer layer are connected by microbumps; The microbumps are installed at the thermal TSV, forming a cross heat dissipation path between the signal chip and the power chip.

[0009] Furthermore, A heat dissipation pillar is also provided between the power chip and the substrate; The number of heat dissipation columns includes multiple columns, which are parallel to each other; The substrate has matching insertion holes corresponding to the heat dissipation pillars for insertion and installation with the heat dissipation pillars to form an auxiliary heat dissipation path.

[0010] Furthermore, The heat dissipation column has a square columnar structure and its height is relatively higher than that of the high bump, which is used to provide mechanical support for the power chip.

[0011] Furthermore, Conductive adhesive is also provided between the insertion hole and the heat dissipation column; The conductive adhesive is evenly applied to the sidewall of the insertion hole.

[0012] Furthermore, The number of the high bumps includes multiple bumps, which are arranged in an array; The high bump abuts against the power chip and signal chip through plastic deformation, thereby achieving electrical connection between the power chip and signal chip.

[0013] The advantages and positive effects of this application are: This technical solution effectively achieves liquid cooling of the chip by setting microchannels inside the heat sink cover. Then, through the synergistic effect with the first and second heat dissipation paths, a three-dimensional, multi-layered heat dissipation system is constructed, which effectively disperses and dissipates the heat generated by the high power density chip, significantly reduces the chip junction temperature, and avoids thermal failure. Attached Figure Description

[0014] Figure 1 A schematic diagram of a vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths provided in an embodiment of this application; Figure 2 This is a schematic diagram of the substrate of the vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths provided in the embodiments of this application.

[0015] The text labels in the figure represent: 100-heat sink cover; 110-microchannel; 200-substrate; 210-heat sink solder ball; 220-intercalation hole; 300-signal chip; 310-thermal interface layer; 320-microbump; 400-power chip; 410-high bump; 420-heat sink pillar; 500-intermediate layer; 510-through silicon via. Detailed Implementation

[0016] To enable those skilled in the art to better understand the technical solution of this application, the application will be described in detail below with reference to the accompanying drawings. The description in this section is only exemplary and explanatory, and should not be used to limit the scope of protection of this application.

[0017] Please refer to Figures 1-2 This embodiment provides a vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths, including a heat dissipation cover interposer 100, the top of which is a flat plate structure and the bottom of which is provided with a microchannel interposer 110 for circulating coolant; a substrate interposer 200, the top of which is a flat plate structure and the bottom of which is provided with a heat dissipation solder ball interposer 210; a signal chip interposer 300, located between the heat dissipation cover interposer 100 and the substrate interposer 200, and with a thermal interface layer interposer 310 between it and the heat dissipation cover interposer 100, forming a first heat dissipation path; and a power chip interposer 400, located between the signal chip interposer 300 and the substrate interposer 200, and connected to the substrate interposer 200 through a high bump interposer 410, forming a second heat dissipation path.

[0018] In this embodiment, the heat dissipation cover 100 serves as the upper component of the structure. Its top is a flat plate structure, providing stable support and a heat dissipation interface. The bottom is provided with microchannels 110 for circulating coolant to flow, achieving active liquid cooling. When the circulating coolant flows in the microchannels 110, it can effectively absorb and carry away heat, thereby reducing the temperature of the overall structure.

[0019] In this embodiment, the substrate 200 is located at the bottom of the structure, and its top is also a flat structure used to support the components above; the bottom is provided with heat dissipation solder balls 210; the heat dissipation solder balls 210 not only provide electrical connection function, but also serve as part of the heat dissipation path to conduct heat to the external circuit board or heat dissipation environment.

[0020] In this embodiment, the signal chip 300 is disposed between the heat dissipation cover plate 100 and the substrate 200, and a thermal interface layer 310 is provided between the signal chip 300 and the heat dissipation cover plate 100. The thermal interface layer 310 is made of a high thermal conductivity material, which can effectively fill the gap between the signal chip 300 and the heat dissipation cover plate 100, reduce the contact thermal resistance, and thus form a first heat dissipation path.

[0021] Specifically, heat is transferred from the signal chip 300 to the heat dissipation cover 100 through the thermal interface layer 310, and then dissipated through the coolant in the microchannel 110.

[0022] In this embodiment, the power chip 400 is located between the signal chip 300 and the substrate 200, and the power chip 400 and the substrate 200 are connected by a high bump 410; the high bump 410 has high thermal conductivity and electrical conductivity, which not only realizes the transmission of electrical signals, but also forms a second heat dissipation path.

[0023] Specifically, heat is conducted from the power chip 400 to the substrate 200 through the high bump 410, and then dissipated through the heat dissipation solder balls 210.

[0024] In this embodiment, the first heat dissipation path and the second heat dissipation path work together to construct a three-dimensional, multi-layered heat dissipation system. When the signal chip 300 and the power chip 400 are working, they generate heat. The heat is discharged simultaneously through the first heat dissipation path and the second heat dissipation path, effectively dispersing the heat flux density and avoiding heat accumulation. The circulating coolant in the microchannel 110 enhances the overall heat dissipation efficiency, significantly reduces the chip junction temperature, and prevents thermal failure.

[0025] In a preferred embodiment, the bottom of the heat dissipation cover 100 is provided with an embedded groove; the microchannel 110 is disposed inside the heat dissipation cover 100 and located at the bottom of the groove; the thermal interface layer 310 is embedded in the groove and its end face abuts against the signal chip 300.

[0026] In this embodiment, the bottom of the heat dissipation cover 100 is provided with an integrally formed embedded groove. The depth of the groove is optimized to accommodate the thermal interface layer 310 and ensure sufficient contact pressure with the signal chip 300.

[0027] In this embodiment, a microchannel 110 is provided inside the heat dissipation cover 100, directly below the groove. The microchannel 110 adopts a serpentine or grid-like layout, forming a continuous fluid passage inside for circulating coolant. When the coolant flows in the microchannel 110, it can directly absorb the heat conducted from above, achieving efficient heat exchange.

[0028] In this embodiment, the thermal interface layer 310 is completely embedded in the groove at the bottom of the heat dissipation cover plate 100, and its material is a thermal interface material with high thermal conductivity; the lower end surface of the thermal interface layer 310 directly abuts against the top surface of the signal chip 300, forming a tight physical contact; this embedded design not only improves structural stability, but also significantly reduces interface thermal resistance, ensuring that heat can be quickly transferred from the signal chip 300 to the heat dissipation cover plate 100.

[0029] In this embodiment, an optimized first heat dissipation path is constructed through the coordinated operation of the groove, microchannel 110 and thermal interface layer 310. When the signal chip 300 is working, the heat generated is first conducted to the heat dissipation cover plate 100 through the thermal interface layer 310, and then quickly carried away by the circulating coolant in the microchannel 110. This integrated heat dissipation design effectively improves heat dissipation efficiency and is particularly suitable for high-power chip application scenarios with high temperature control requirements.

[0030] In a preferred embodiment, an interposer layer 500 is further provided between the signal chip 300 and the power chip 400; the interposer layer 500 is provided with through-silicon vias 510 arranged in an array for heat transfer between the signal chip 300 and the power chip 400.

[0031] In this embodiment, the packaging structure includes, in the vertical stacking direction, a heat dissipation cover plate 100, a signal chip 300, an interposer layer 500, a power chip 400, and a substrate 200 in sequence; wherein, the interposer layer 500 is disposed between the signal chip 300 and the power chip 400, serving as an important heat conduction and mechanical support layer.

[0032] In this embodiment, the interposer 500 is made of a high thermal conductivity material and has multiple through-silicon vias 510 that penetrate the substrate. These through-silicon vias 510 are evenly arranged in a regular array throughout the entire area of ​​the interposer 500, forming dense heat conduction channels. The through-silicon vias 510 are filled with a high thermal conductivity material, which can effectively improve the thermal conductivity of the interposer 500 in the thickness direction.

[0033] In this embodiment, the interposer 500 and the through-silicon vias 510 therein constitute an efficient thermal coupling path between chips. When the heat generated by the signal chip 300 is conducted downward through the interposer 500, or when the heat generated by the power chip 400 is conducted upward, the array of through-silicon vias 510 can quickly equalize the temperature difference between the two, effectively reduce the thermal gradient between chips, and improve the heat dissipation uniformity of the overall package.

[0034] In a preferred embodiment, the signal chip 300 and the interposer 500 are connected by microbumps 320; the microbumps 320 are correspondingly installed at the through silicon via 510, forming a cross heat dissipation path between the signal chip 300 and the power chip 400.

[0035] In this embodiment, in the vertically stacked chip packaging structure, the signal chip 300 and the interposer layer 500 are physically connected and electrically interconnected through multiple microbumps 320; these microbumps 320 are arranged in a regular array between the bottom surface of the signal chip 300 and the top surface of the interposer layer 500 to form a stable connection interface.

[0036] In this embodiment, the intermediate layer 500 is provided with multiple sets of through-silicon vias 510 penetrating its upper and lower surfaces. These through-silicon vias 510 are uniformly distributed in a dense array. The mounting positions of the microbumps 320 correspond to the distribution positions of the through-silicon vias 510, so that each microbump 320 can form a thermal coupling with a through-silicon via 510 in the vertical direction.

[0037] In this embodiment, the corresponding mounting configuration of microbumps 320 and through-silicon vias 510 not only ensures stable electrical connections between chips, but also constructs an efficient cross heat dissipation path, significantly improving the uniformity of heat distribution when multiple chips work together in a vertical stacked structure, and providing a more reliable thermal management solution for high power density packaging.

[0038] In a preferred embodiment, a heat dissipation pillar 420 is further provided between the power chip 400 and the substrate 200; the number of heat dissipation pillars 420 includes a plurality of them, and they are parallel to each other; the substrate 200 is provided with matching insertion holes 220 corresponding to the heat dissipation pillars 420 for insertion and installation with the heat dissipation pillars 420 to form an auxiliary heat dissipation path.

[0039] In this embodiment, a plurality of heat dissipation pillars 420 are provided between the power chip 400 and the substrate 200; these heat dissipation pillars 420 are arranged in a parallel manner and are evenly distributed between the bottom surface of the power chip 400 and the top surface of the substrate 200 to form a set of auxiliary heat dissipation paths.

[0040] In this embodiment, the top surface of the substrate 200 is provided with corresponding insertion holes 220 for each heat sink 420; the size and position of these insertion holes 220 are precisely matched with the heat sink 420, so that the heat sink 420 can be stably inserted into them to achieve mechanical connection and thermal coupling.

[0041] In this embodiment, by connecting the heat sink 420 to the insertion hole 220, an additional heat conduction channel is established between the power chip 400 and the substrate 200. This design significantly increases the downward heat dissipation area of ​​the power chip 400, effectively sharing the heat load of the traditional heat dissipation path through the high bump, and forming an auxiliary heat dissipation path.

[0042] In a preferred embodiment, the heat dissipation column 420 has a square columnar structure and its height is relatively higher than that of the high bump 410, which is used to provide mechanical support for the power chip 400.

[0043] In this embodiment, the heat dissipation column 420 adopts a four-corner columnar structure design; the cross-section of this four-corner columnar structure is rectangular or square, with four straight side surfaces and clear edges; compared with the cylindrical structure, the four-corner columnar structure provides a larger surface area to volume ratio, which is beneficial to enhance heat conduction efficiency.

[0044] In this embodiment, the height of the heat sink 420 is specially designed to be higher than that of the high bump 410. This height difference allows the heat sink 420 to contact the corresponding component before the high bump 410 when the power chip 400 is mounted on the substrate 200, thus bearing the main mechanical support role. The top of the heat sink 420 is firmly connected to the bottom surface of the power chip 400, while the bottom end forms a stable contact with the substrate 200.

[0045] In a preferred embodiment, conductive adhesive is further provided between the insertion hole 220 and the heat dissipation column 420; the conductive adhesive is evenly applied to the side wall of the insertion hole 220.

[0046] In this embodiment, a conductive adhesive layer is provided at the connection interface between the heat dissipation column 420 and the insertion hole 220 on the substrate 200; the conductive adhesive is composed of a polymer matrix and conductive fillers uniformly dispersed therein, which has good electrical and thermal conductivity, while maintaining appropriate bonding strength.

[0047] In this embodiment, when the heat sink 420 is inserted into the insertion hole 220, its outer surface is in full contact with the conductive adhesive coated on the inner sidewall of the insertion hole. The conductive adhesive forms three important functional connections between the heat sink 420 and the insertion hole 220: first, it provides a stable mechanical connection to enhance the overall stability of the structure; second, it establishes an electrical connection channel to realize an additional electrical signal transmission path between the power chip 400 and the substrate 200; and third, it forms an auxiliary heat conduction path to further improve heat dissipation efficiency.

[0048] In a preferred embodiment, the number of the high bumps 410 includes a plurality of them, and they are arranged in an array; the high bumps 410 abut against the power chip 400 and the signal chip 300 through plastic deformation, thereby realizing the electrical connection between the power chip 400 and the signal chip 300.

[0049] In this embodiment, a plurality of high bumps 410 are provided between the power chip 400 and the substrate 200. These high bumps 410 are arranged in a regular array between the bottom surface of the power chip 400 and the top surface of the substrate 200 to form a dense array of connection points. The array arrangement ensures the uniform distribution of connection points, which is beneficial to the uniform conduction of current and heat.

[0050] In this embodiment, the high bump 410 is made of a conductive material with good plasticity, and its height and diameter are precisely designed to meet the dual requirements of electrical connection and mechanical support. During the packaging process, the high bump 410 undergoes a specific plastic deformation process, which is achieved by applying appropriate pressure and temperature.

[0051] In this embodiment, during the plastic deformation process, the upper surface of the high bump 410 forms a tight physical contact with the bottom surface of the power chip 400, while its lower surface is firmly connected to the top surface of the substrate 200. This abutting connection achieved through plastic deformation ensures low resistance characteristics between the contact interfaces, providing a stable electrical connection path between the power chip 400 and the signal chip 300.

[0052] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of textual expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. A vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths, characterized in that, include The heat dissipation cover (100) has a flat top and a microchannel (110) at the bottom for circulating coolant. The substrate (200) has a flat top and heat dissipation solder balls (210) at the bottom. A signal chip (300) is located between the heat dissipation cover plate (100) and the substrate (200), and a thermal interface layer (310) is provided between the signal chip (300) and the heat dissipation cover plate (100) to form a first heat dissipation path; A power chip (400) is located between the signal chip (300) and the substrate (200), and is connected to the substrate (200) by a high bump (410) to form a second heat dissipation path.

2. The vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths according to claim 1, characterized in that, The bottom of the heat dissipation cover (100) is provided with an embedded groove; The microchannel (110) is disposed inside the heat dissipation cover (100) and located at the bottom of the groove; The thermal interface layer (310) is embedded in the groove, and its end face abuts against the signal chip (300).

3. The vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths according to claim 1, characterized in that, An intermediary layer (500) is also provided between the signal chip (300) and the power chip (400). The interposer layer (500) is provided with through-silicon vias (510) arranged in an array for heat transfer between the signal chip (300) and the power chip (400).

4. The vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths according to claim 3, characterized in that, The signal chip (300) and the interposer layer (500) are connected by microbumps (320); The microbumps (320) are installed at the through silicon vias (510) to form a cross heat dissipation path between the signal chip (300) and the power chip (400).

5. The vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths according to claim 1, characterized in that, A heat dissipation column (420) is also provided between the power chip (400) and the substrate (200). The number of heat dissipation columns (420) includes multiple columns, which are parallel to each other; The substrate (200) is provided with matching insertion holes (220) corresponding to the heat dissipation column (420) for insertion and installation with the heat dissipation column (420) to form an auxiliary heat dissipation path.

6. The vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths according to claim 5, characterized in that, The heat dissipation column (420) has a square column structure and its height is relatively higher than that of the high bump (410), which is used to provide mechanical support for the power chip (400).

7. The vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths according to claim 5, characterized in that, Conductive adhesive is also provided between the insertion hole (220) and the heat dissipation column (420); The conductive adhesive is evenly applied to the sidewall of the insertion hole (220).

8. The vertically stacked chip packaging structure based on multiple collaborative heat dissipation paths according to claim 5, characterized in that, The number of the high bumps (410) includes multiple ones, and they are arranged in an array; The high bump (410) abuts against the power chip (400) and the signal chip (300) through plastic deformation, thereby realizing the electrical connection between the power chip (400) and the signal chip (300).

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