Semiconductor package structure and electronic device

Abstract

The application provides a semiconductor packaging structure and an electronic device. The semiconductor packaging structure comprises a substrate, a target chip located on one side of the substrate, a first packaging layer located on the side of the substrate close to the target chip and wrapping the target chip and the substrate, wherein the side of the target chip away from the substrate is flush with a first surface of the first packaging layer, a receiving groove located in the first packaging layer and extending from the first surface to a second surface, wherein the orthographic projection of the receiving groove on the substrate surrounds the orthographic projection of the target chip on the substrate, a reinforcing ring located in the receiving groove, the reinforcing ring comprising opposite third and fourth surfaces, and the third surface of the reinforcing ring is flush with the first surface of the first packaging layer. By arranging the receiving groove in the first packaging layer and embedding the rigid reinforcing ring in the receiving groove, the heat dissipation can be increased, the internal stress of the semiconductor packaging structure can be offset, the risk of ball mounting or element mounting caused by warping can be reduced, and the heat dissipation performance and reliability of the semiconductor packaging structure are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure and an electronic device. Background Technology

[0002] With the increasing demands of artificial intelligence and high-speed data communication, the power consumption of chips in electronic devices has increased dramatically. This results in chips generating a significant amount of heat during operation. If this heat cannot be dissipated in a timely manner, it will affect the chip's performance and lifespan. Furthermore, because the substrate, chip, and packaging layer are made of different materials, the substrate used to support the chip is prone to warping and deformation. This deformation reduces the reliability of ball-mounting and mounting other components on the substrate, thereby affecting the reliability of the entire semiconductor packaging structure and the electronic devices that include it. Utility Model Content

[0003] In order to at least overcome the above-mentioned shortcomings in the prior art, the purpose of this application is to provide a semiconductor packaging structure and an electronic device, the semiconductor packaging structure comprising: substrate; The target chip located on one side of the substrate; A first encapsulation layer is located on the side of the substrate closer to the target chip and encapsulates the target chip and the substrate. The first encapsulation layer includes a first surface and a second surface opposite to each other. The side of the target chip away from the substrate is flush with the first surface of the first encapsulation layer. A receiving groove located within the first encapsulation layer and extending from the first surface to the second surface; wherein the orthographic projection of the receiving groove on the substrate surrounds the orthographic projection of the target chip on the substrate; A reinforcing ring located within the receiving groove, the reinforcing ring comprising opposing third and fourth surfaces; wherein the third surface of the reinforcing ring is flush with the first surface of the first encapsulation layer.

[0004] In one possible implementation, the semiconductor package structure further includes an adhesive layer located on the fourth side of the reinforcing ring and at the bottom of the receiving groove, for fixing the reinforcing ring to the receiving groove; Wherein, the orthographic projection of the adhesive layer on the substrate covers the orthographic projection of the reinforcing ring on the substrate.

[0005] In one possible implementation, the depth of the receiving groove in the direction perpendicular to the substrate does not exceed the height of the target chip.

[0006] In one possible implementation, the substrate includes opposing fifth and sixth surfaces, and a plurality of conductive pillars extending from the fifth surface to the sixth surface; The target chip includes a chip body and multiple pins located on the same side of the chip body; The chip body is electrically connected to at least one of the conductive pillars via at least one of the pins.

[0007] In one possible implementation, the semiconductor packaging structure further includes a second packaging layer located in the gap between the chip body and the substrate; The orthographic projection of the first encapsulation layer on the substrate at least partially surrounds the orthographic projection of the second encapsulation layer on the substrate.

[0008] In one possible implementation, the semiconductor package structure further includes a first redistribution layer and a second redistribution layer; The first redistribution layer is located on the side of the substrate away from the target chip, and the second redistribution layer is located between the substrate and the target chip. The first metal trace in the first redistribution layer is electrically connected to the pin of the target chip via the conductive pillar and the second metal trace in the second redistribution layer.

[0009] In one possible implementation, the material of the first encapsulation layer includes an epoxy molding compound.

[0010] In one possible implementation, the material of the second encapsulation layer includes epoxy resin.

[0011] In one possible implementation, the reinforcing ring is made of a material that is thermally conductive.

[0012] Based on the same inventive concept, this application also provides an electronic device, including the semiconductor packaging structure described in any of the foregoing claims.

[0013] Compared with the prior art, this application has the following beneficial effects: This application provides a semiconductor packaging structure and an electronic device. The semiconductor packaging structure, by setting a receiving groove in the first packaging layer and embedding a rigid reinforcing ring in the receiving groove, can not only increase heat dissipation, but also offset the internal stress caused by the mismatch of thermal expansion coefficients between different materials, ensuring that the semiconductor packaging structure remains flat, thereby reducing the risk of poor ball placement or component mounting due to warping, and improving the heat dissipation performance and reliability of the semiconductor packaging structure. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is one of the schematic diagrams of the semiconductor packaging structure provided in this embodiment; Figure 2 This is a top view of the semiconductor package structure provided in this embodiment; Figure 3 This is the second schematic diagram of the semiconductor packaging structure provided in this embodiment; Figure 4 This is the third schematic diagram of the semiconductor packaging structure provided in this embodiment.

[0016] Icons: Semiconductor package structure-10; Substrate-100; Target chip-200; First packaging layer-310; Reinforcing ring-400; Receiving groove-401; Adhesive layer-410; Chip body-210; Pin-220; Second packaging layer-320; First redistribution layer-510; Second redistribution layer-520. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0020] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0022] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0023] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0024] The inventors discovered that with the increasing demands of artificial intelligence and high-speed data communication, the power consumption of chips within electronic devices has increased dramatically. This leads to a significant amount of heat generated during chip operation. If this heat cannot be dissipated in a timely manner, it will affect the chip's performance and lifespan. Furthermore, because the substrate, chip, and packaging layer are made of different materials, the substrate used to support the chip is prone to warping and deformation. This deformation reduces the reliability of ball-mounting and mounting other components on the substrate, thereby affecting the reliability of the entire semiconductor packaging structure and the electronic devices containing that structure.

[0025] In view of this, this embodiment provides a solution that can reduce the risks of the above-mentioned problems. The solution provided in this embodiment will be described in detail below.

[0026] This application provides a semiconductor packaging structure 10, please refer to... Figure 1 It includes a substrate 100 with a receiving groove 401, a target chip 200, a first packaging layer 310, and a reinforcing ring 400.

[0027] Optionally, the material of the substrate 100 may include a rigid material, such as glass or quartz; or the material of the substrate 100 may include a flexible material, such as polyimide (Pi).

[0028] The target chip 200 is located on one side of the substrate 100.

[0029] Optionally, the substrate 100 and the target chip 200 may also include other functional layers and redistribution layers.

[0030] Optionally, a plurality of conductive structures electrically connected to the substrate 100 may be provided on the side of the substrate 100 away from the target chip 200, and / or a plurality of components electrically connected to the substrate 100 may be provided; the conductive structures and / or components may be electrically connected to the target chip 200 via the substrate 100.

[0031] Please refer to Figure 2 The first encapsulation layer 310 is located on the side of the substrate 100 close to the target chip 200 and encapsulates the target chip 200 and the substrate 100. The first encapsulation layer 310 includes a first surface and a second surface opposite to each other. The side of the target chip 200 away from the substrate 100 is flush with the first surface of the first encapsulation layer 310.

[0032] In this embodiment, the first encapsulation layer 310 can protect the target chip 200 and the substrate 100 from external corrosion or damage, while also improving the heat dissipation capacity of the semiconductor packaging structure 10 and providing it with mechanical support.

[0033] The receiving groove 401 is located within the first packaging layer 310 and extends from the first surface to the second surface; wherein the orthographic projection of the receiving groove 401 on the substrate 100 surrounds the orthographic projection of the target chip 200 on the substrate 100.

[0034] Optionally, a receiving groove 401 is formed on the substrate 100 by laser ablation.

[0035] In this embodiment, the shape and depth of the receiving groove 401 match the shape and height of the reinforcing ring 400.

[0036] The reinforcing ring 400 is located within the receiving groove 401, and the reinforcing ring 400 includes a third surface and a fourth surface opposite to each other; wherein the third surface of the reinforcing ring 400 is flush with the first surface of the first encapsulation layer 310.

[0037] Optionally, the reinforcing ring 400 can be made of a material with high thermal conductivity and high rigidity, such as copper or aluminum, so as to effectively suppress the warping of the substrate 100 while optimizing the heat dissipation of the semiconductor packaging structure 10.

[0038] In this embodiment, the reinforcing ring 400 is located within the pre-set receiving groove 401 on the substrate 100. This not only improves the overall heat dissipation capacity of the semiconductor packaging structure 10 but also, to a certain extent, counteracts the internal stress caused by the mismatch in thermal expansion coefficients between different materials. In particular, it suppresses the warping tendency of the substrate 100 during the cooling process of the first packaging layer 310, ensuring that the semiconductor packaging structure 10 remains flat. This improves the accuracy of subsequently setting conductive structures or mounting components on the side of the substrate 100 away from the target chip 200, thereby reducing the risk of poor ball placement or component mounting due to warping and enhancing the reliability of the semiconductor packaging structure 10.

[0039] For example, the semiconductor package structure 10 in this embodiment can be formed by the following fabrication method.

[0040] First, a carrier is provided, the material of which may include glass. A substrate 100 is bonded to one side of the carrier, which can be done by photosensitive bonding adhesive. A target chip 200 is connected to one side of the substrate 100. Specifically, the target chip 200 can be connected to the side of the substrate 100 away from the carrier by flip chip bonding (FC). A first encapsulation layer 310 is formed, which at least encapsulates the target chip 200 and the substrate 100. Specifically, the target chip 200, the substrate 100 and the carrier can be placed in a preheated mold. Molten material of the first encapsulation layer 310 is injected into the cavity under high temperature and pressure to uniformly encapsulate the target chip 200 and the substrate 100. After pressure holding and curing, a dense protective shell is formed. Finally, the product is demolded and polished to complete the encapsulation.

[0041] Next, a receiving groove 401 is formed on the first encapsulation layer 310 by laser ablation process. Specifically, the material of the first encapsulation layer 310 can be locally melted or vaporized by laser at a preset position, and the residue can be blown away with the help of auxiliary gas, thereby etching out the receiving groove 401; the reinforcing ring 400 is fixedly connected to the receiving groove 401; and the carrier is removed.

[0042] Thus, the semiconductor package structure 10 formed by this manufacturing method has better heat dissipation performance and reduces the warping of the substrate 100, thereby reducing the risk of poor ball placement or component mounting caused by warping.

[0043] In one possible implementation, please refer to Figure 3 The semiconductor package structure 10 further includes an adhesive layer 410 located on the fourth surface of the reinforcing ring 400 and the bottom of the receiving groove 401, for fixing the reinforcing ring 400 to the receiving groove 401; wherein the orthographic projection of the adhesive layer 410 on the substrate 100 covers the orthographic projection of the reinforcing ring 400 on the substrate 100.

[0044] In this embodiment, the reinforcing ring 400 can be bonded to the receiving groove 401 of the first encapsulation layer 310 by the adhesive layer 410. The adhesive layer 410 can be a single-component epoxy resin adhesive with high filler and high thermal conductivity. The high thermal conductivity adhesive layer 410 can improve the heat dissipation performance of the semiconductor encapsulation structure 10, and the high filler adhesive layer 410 can improve the connection reliability between the reinforcing ring 400 and the first encapsulation layer 310.

[0045] For example, the semiconductor package structure 10 in this embodiment can be formed by the following fabrication method.

[0046] First, a reinforcing ring 400 is provided; then, the reinforcing ring 400 is bonded to the receiving groove 401 using adhesive. When applying the adhesive, a measured amount of adhesive can be applied to the fourth side of the reinforcing ring 400 using a dispensing machine. The adhesive is then heated and cured, forming a rigid whole between the reinforcing ring 400 and the bottom of the receiving groove 401. Next, the adhesive is cured to form an adhesive layer 410; the reinforcing ring 400 is fixedly connected to the bottom of the receiving groove 401 of the first encapsulation layer 310 via the adhesive layer 410.

[0047] It should be noted that, in addition to fixing the reinforcing ring 400 to the receiving groove 401 through the adhesive layer 410, the reinforcing ring 400 can also be embedded in the receiving groove 401 in other ways, which are not specifically limited here.

[0048] In one possible implementation, in the direction perpendicular to the substrate 100, please refer to... Figure 1 The depth of the accommodating groove 401 does not exceed the height of the target chip 200.

[0049] Thus, the reinforcing ring 400 disposed in the receiving groove 401 can better suppress the warping of the substrate 100, thereby reducing the risk of poor ball placement or component mounting caused by warping.

[0050] In one possible implementation, please refer to Figure 1 The substrate 100 includes a fifth and a sixth opposing surface, and a plurality of conductive pillars extending from the fifth surface to the sixth surface.

[0051] Optionally, the conductive pillars may be made of copper. Copper has high electrical and thermal conductivity, which can effectively reduce interconnect resistance and signal transmission loss, and also improve the heat dissipation performance of the semiconductor package structure 10.

[0052] The target chip 200 includes a chip body 210 and a plurality of pins 220 located on the same side of the chip body 210.

[0053] It should be understood that the target chip 200 is a packaged functional unit, whose circuitry is integrated within the chip body 210, and the multiple pins 220 are metal contacts led out from the internal circuitry of the chip body 210 and arranged outside the chip body 210 through the packaging process.

[0054] The chip body 210 is electrically connected to at least one of the conductive pillars via at least one of the pins 220.

[0055] In this embodiment, the chip body 210 is electrically connected to the conductive pillar via pin 220, and the target chip 200 is electrically connected to other components or external circuits via the substrate 100, thereby realizing functions such as signal transmission.

[0056] In one possible implementation, please refer to Figure 4 The semiconductor packaging structure 10 further includes a second packaging layer 320 located in the gap between the chip body 210 and the substrate 100.

[0057] Optionally, when connecting the target chip 200 on the substrate 100, it can be achieved by flip chip bonding (FC).

[0058] Therefore, in this embodiment, the material of the second encapsulation layer 320 needs to be filled into the gap between the target chip 200 and the substrate 100 through capillary action, and completely cover the pins 220 of the target chip 200. In this way, after curing, the second encapsulation layer 320 can enhance the mechanical strength of the semiconductor package structure 10, thereby effectively dispersing the thermomechanical stress caused by the mismatch of thermal expansion coefficients between the chip body 210, pins 220 and substrate 100 materials, suppressing solder joint fatigue fracture caused by thermal cycling, and improving the impact resistance of the semiconductor package structure 10, ensuring the long-term reliability of the mechanical and electrical connections between the target chip 200 and the substrate 100.

[0059] The orthographic projection of the first encapsulation layer 310 on the substrate 100 at least partially surrounds the orthographic projection of the second encapsulation layer 320 on the substrate 100.

[0060] Thus, by forming the first encapsulation layer 310 after forming the second encapsulation layer 320, which encapsulates the target chip 200, the substrate 100, and the second encapsulation layer 320, the possibility of the target chip 200 being corroded or impacted by external media can be reduced. In addition, mechanical stress can be further dispersed and the warping of the target chip 200 and the substrate 100 can be synergistically suppressed, thereby improving the overall performance of the semiconductor packaging structure 10.

[0061] In one possible implementation, please refer to Figure 4The semiconductor package structure 10 further includes a first redistribution layer 510 and a second redistribution layer 520; wherein, the first redistribution layer 510 is located on the side of the substrate 100 away from the target chip 200, the second redistribution layer 520 is located between the substrate 100 and the target chip 200, and a first metal trace in the first redistribution layer 510 is electrically connected to the pin 220 of the target chip 200 via the conductive pillar and the second metal trace in the second redistribution layer 520.

[0062] In this embodiment, the first wiring layer 510 includes a first insulating structure and a first metal trace located within the first insulating structure, and the second wiring layer 520 includes a second insulating structure and a second metal trace located within the second insulating structure. The target chip 200 is electrically connected to the substrate 100 via the first metal trace, and then electrically connected to other conductive structures and / or components via the second metal trace. The first wiring layer 510 and the second wiring layer 520 can achieve high-density interconnection within a limited space, simplifying the packaging structure. This allows the semiconductor packaging structure 10 in this embodiment to improve signal transmission integrity and reduce the overall power consumption of the electronic device when applied in an electronic device.

[0063] In one possible implementation, the material of the first encapsulation layer 310 includes epoxy molding compound (EMC).

[0064] In this embodiment, EMC can be used as the material for the first encapsulation layer 310. EMC material has good mechanical strength, which can effectively resist external physical impacts and stresses; its insulation properties ensure stable transmission of circuit signals and prevent short circuits; at the same time, through formulation optimization, EMC can achieve good high temperature and high humidity resistance to resist the corrosion of the external environment. In addition, EMC technology is mature and suitable for large-scale rapid molding, which can improve packaging efficiency and reduce production costs.

[0065] It should be noted that, in addition to epoxy molding compound, the material of the first encapsulation layer 310 may also include other materials, which are not specifically limited here.

[0066] In one possible implementation, the material of the second encapsulation layer 320 includes epoxy resin.

[0067] In this embodiment, epoxy resin can be used as the material for the second encapsulation layer 320. After curing, the epoxy resin can form a filling layer between the bottom of the target chip 200, the solder balls, and the substrate 100, uniformly dispersing mechanical stress and thus protecting the solder joints. Furthermore, its matching coefficient of thermal expansion with the target chip 200 and the substrate 100 can absorb thermal stress generated by temperature changes, preventing solder joint fatigue cracking due to thermal mismatch, thereby extending the lifespan of the electronic device including this semiconductor package structure 10.

[0068] It should be noted that, in addition to epoxy resin, the material of the first encapsulation layer 310 may also include other materials, which are not specifically limited here.

[0069] In one possible implementation, the reinforcing ring 400 is made of a material that is thermally conductive.

[0070] In this way, the reinforcing ring 400 can quickly absorb and diffuse the heat generated by the target chip 200 and the substrate 100 during operation, while reducing the temperature gradient caused by local heat accumulation in the first packaging layer 310, thereby reducing the resulting warping and improving the reliability of the semiconductor packaging structure 10.

[0071] In addition, to improve the warping resistance of the reinforcing ring 400, the material of the reinforcing ring 400 can also be a material with high rigidity.

[0072] Based on the same inventive concept, this application also provides an electronic device including the semiconductor packaging structure 10 described in any of the preceding claims. Since the aforementioned semiconductor packaging structure 10 has strong heat dissipation capabilities, it can also offset internal stress caused by the mismatch in thermal expansion coefficients between different materials, reducing the risk of poor ball placement or component mounting due to warping; therefore, the electronic device in this embodiment has high product yield and reliability.

[0073] In summary, this application provides a semiconductor packaging structure 10 and an electronic device. The semiconductor packaging structure 10 includes: a substrate 100; a target chip 200 located on one side of the substrate 100; a first packaging layer 310 located on the side of the substrate 100 near the target chip 200 and encapsulating the target chip 200 and the substrate 100, the first packaging layer 310 including opposing first and second surfaces; wherein the side of the target chip 200 away from the substrate 100 is flush with the first surface of the first packaging layer 310; a receiving groove 401 located within the first packaging layer 310 and extending from the first surface to the second surface; wherein the orthographic projection of the receiving groove 401 on the substrate 100 surrounds the orthographic projection of the target chip 200 on the substrate 100; and a reinforcing ring 400 located within the receiving groove 401, the reinforcing ring 400 including opposing third and fourth surfaces; wherein the third surface of the reinforcing ring 400 is flush with the first surface of the first packaging layer 310. By providing a receiving groove 401 in the first packaging layer 310 and embedding a rigid reinforcing ring 400 in the receiving groove 401, heat dissipation can be increased, and internal stress caused by the mismatch of thermal expansion coefficients between different materials can be offset, ensuring that the semiconductor packaging structure 10 remains flat, thereby reducing the risk of poor ball placement or component mounting due to warping, and improving the heat dissipation performance and reliability of the semiconductor packaging structure 10.

[0074] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0075] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor packaging structure, characterized in that, include: substrate; The target chip located on one side of the substrate; A first encapsulation layer is located on the side of the substrate closer to the target chip and encapsulates the target chip and the substrate. The first encapsulation layer includes a first surface and a second surface opposite to each other. The side of the target chip away from the substrate is flush with the first surface of the first encapsulation layer. A receiving groove located within the first encapsulation layer and extending from the first surface to the second surface; wherein the orthographic projection of the receiving groove on the substrate surrounds the orthographic projection of the target chip on the substrate; A reinforcing ring located within the receiving groove, the reinforcing ring comprising opposing third and fourth surfaces; wherein the third surface of the reinforcing ring is flush with the first surface of the first encapsulation layer.

2. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor packaging structure also includes an adhesive layer located on the fourth side of the reinforcing ring and at the bottom of the receiving groove, for fixing the reinforcing ring to the receiving groove; Wherein, the orthographic projection of the adhesive layer on the substrate covers the orthographic projection of the reinforcing ring on the substrate.

3. The semiconductor packaging structure according to claim 1, characterized in that, In a direction perpendicular to the substrate, the depth of the receiving groove does not exceed the height of the target chip.

4. The semiconductor packaging structure according to claim 1, characterized in that, The substrate includes a fifth and a sixth opposing surface, and a plurality of conductive pillars extending from the fifth surface to the sixth surface; The target chip includes a chip body and multiple pins located on the same side of the chip body; The chip body is electrically connected to at least one of the conductive pillars via at least one of the pins.

5. The semiconductor packaging structure according to claim 4, characterized in that, The semiconductor packaging structure further includes a second packaging layer located in the gap between the chip body and the substrate; The orthographic projection of the first encapsulation layer on the substrate at least partially surrounds the orthographic projection of the second encapsulation layer on the substrate.

6. The semiconductor packaging structure according to claim 4, characterized in that, The semiconductor packaging structure further includes a first redistribution layer and a second redistribution layer; The first redistribution layer is located on the side of the substrate away from the target chip, and the second redistribution layer is located between the substrate and the target chip. The first metal trace in the first redistribution layer is electrically connected to the pin of the target chip via the conductive pillar and the second metal trace in the second redistribution layer.

7. The semiconductor packaging structure according to claim 1, characterized in that, The material of the first encapsulation layer includes epoxy molding compound.

8. The semiconductor packaging structure according to claim 5, characterized in that, The material of the second encapsulation layer includes epoxy resin.

9. The semiconductor packaging structure according to claim 1, characterized in that, The reinforcing ring is made of a material that has thermal conductivity.

10. An electronic device, characterized in that, Includes the semiconductor packaging structure according to any one of claims 1-9.

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