Semiconductor package structure

Abstract

The application provides a semiconductor package structure, comprising: a redistribution layer having a solder pad; a first chip and a support structure horizontally arranged on the redistribution layer, wherein the support structure defines a plurality of holes exposing the solder pad on the redistribution layer; and a dispensing layer connected between the first chip, the support structure and the redistribution layer. The application defines a placement position for the DRAM by pre-placing the support structure on the redistribution layer and providing holes in the support structure for exposing the solder pad on the redistribution layer. The DRAM can be placed after the molding is completed, thereby avoiding the risk of damage of the DRAM caused by the loss of other components or materials, significantly improving the availability of the DRAM, enabling better fan-out of the DRAM, enhancing the overall package stability, reducing the risk of structural failure and manufacturing cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and specifically to a semiconductor packaging structure. Background Technology

[0002] The current structural feature of fan-out multi-chip module (FOMCM) is to integrate dynamic random access memory (DRAM) with system-on-a-chip (SoC die) in a single package to improve integration and performance.

[0003] refer to Figure 1 , Figure 1 This is a schematic diagram of the longitudinal cross-section of a current-technical FOMCM structure. (Example) Figure 1 As shown, the FOMCM structure includes a redistribution layer (RDL) 03, a system-on-a-chip (SoC) 02 and a DRAM 01 arranged side-by-side on the redistribution layer 03, an underfill adhesive 04 filling the spaces between the three, and a molding compound 05 encapsulating the SoC 02, DRAM 01, and underfill adhesive 04. This FOMCM structure integrates the SoC 02 and DRAM 01 into a single molded package.

[0004] However, during the manufacturing process, if any component or circuitry within the FOMCM structure is damaged, DRAM01 will also be lost. This is because, in the integrated molded structure, DRAM01 is encapsulated within the molding material 05 and soldered to the redistribution layer 03. Later in the manufacturing process, it becomes impossible to remove DRAM01 from the structure for reuse. Since DRAM01 is expensive, significantly more so than other components or materials such as the system-on-a-chip 02, this results in material waste, significantly increasing the risk of loss and manufacturing costs. Utility Model Content

[0005] The main objective of this application is to provide a semiconductor packaging structure that improves the availability of DRAM, enhances overall packaging stability, and reduces the risk of structural failure and manufacturing costs.

[0006] This application discloses a semiconductor packaging structure, comprising: a redistribution layer having solder pads; a first chip and a support structure horizontally arranged on the redistribution layer, wherein the support structure defines a plurality of holes that expose the solder pads on the redistribution layer; and an adhesive layer connecting the first chip, the support structure, and the redistribution layer.

[0007] In some alternative implementations, the support structure and the first chip do not overlap in the vertical direction.

[0008] In some alternative embodiments, the support structure includes a support body and an adhesive layer, the adhesive layer being connected between the support body and the redistribution layer.

[0009] In some alternative embodiments, the semiconductor package structure further includes a metal layer filling the holes, the metal layer being electrically connected to the bonding pads.

[0010] In some alternative embodiments, the semiconductor package structure further includes a molding layer that covers the sidewalls and bottom of the aperture and exposes the solder pads.

[0011] In some alternative embodiments, the molding layer fills the gap between the metal layer and the support structure.

[0012] In some alternative implementations, the molding layer further covers the first chip, the support structure, and the dispensing layer, and defines a cavity above the support structure, the cavity exposing the support structure and the hole.

[0013] In some alternative embodiments, the semiconductor package structure further includes a second chip disposed on the support structure and electrically connected to the metal layer.

[0014] In some alternative embodiments, the semiconductor package structure further includes: a filler layer that fills the cavity and covers the second chip, the second chip being located within the cavity.

[0015] In some alternative embodiments, the upper surface of the molding layer and the upper surface of the filler layer are substantially flush, the first chip is exposed in the molding layer, and the second chip is completely embedded in the filler layer.

[0016] In some alternative embodiments, the semiconductor package structure further includes: a plurality of bumps electrically connected between the first chip and the redistribution layer; the adhesive layer fills the gap between the first chip and the redistribution layer, covers the plurality of bumps, and extends to the sidewalls of the first chip and the sidewalls of the support structure.

[0017] In some alternative implementations, the width of the cavity is smaller than the width of the support structure.

[0018] In some alternative implementations, two adjacent holes are connected to each other and separated by the molding layer.

[0019] In some alternative implementations, the adhesive layer covers the sidewalls and bottom of the hole and exposes the solder pad.

[0020] In some alternative embodiments, the adhesive layer fills the gap between the metal layer and the support structure.

[0021] In some alternative embodiments, the metal layer is tin or a tin alloy.

[0022] In some alternative implementations, the height of the support structure is greater than the spacing between the first chip and the redistribution layer.

[0023] In some alternative implementations, the second chip is a dynamic random access memory (DRAM).

[0024] As described above, in order to solve the technical problem that the failure of any component or circuit inside the FOMCM will lead to the loss of DRAM, resulting in an excessively high risk of loss, this application proposes a semiconductor packaging structure. By pre-inserting a support structure on the redistribution layer, and the support structure is used to expose the holes of the solder pads on the redistribution layer, the support structure is used to reserve a place for DRAM. Thus, it is possible to place the DRAM after the molding is completed and the structure after molding is confirmed to be good. This can avoid the risk of DRAM being damaged along with other components or materials, reduce material waste, significantly improve the availability of DRAM, and at the same time enable better fan-out of DRAM, simultaneously enhance the overall package stability, and reduce the risk of structural failure and manufacturing costs. Attached Figure Description

[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0026] Figure 1 This is a schematic diagram of the longitudinal cross-section of a current-technical FOMCM structure;

[0027] Figure 2 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 2a according to an embodiment of this application;

[0028] Figure 3 yes Figure 2 An enlarged schematic diagram of the dashed box area in the semiconductor package structure 2a shown;

[0029] Figure 4 yes Figure 2 A top view of the support structure in the semiconductor package structure 2a shown;

[0030] Figure 5 yes Figure 2 Another top view of the support structure in the semiconductor package structure 2a shown;

[0031] Figure 6 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 6a according to an embodiment of this application;

[0032] Figure 7 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 7a according to an embodiment of this application;

[0033] Figure 8 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 8a according to an embodiment of this application;

[0034] Figures 9 to 10 This is a schematic diagram of the manufacturing steps of a semiconductor packaging structure according to an embodiment of this application.

[0035] Explanation of reference numerals / symbols in the attached diagram:

[0036] 01: DRAM; 02: System-on-a-Chip; 03: Redistribution Layer; 04: Underfill Adhesive; 05: Mold Material; 10: Redistribution Layer; 101: Solder Pad; 11: First Chip; 1101: Bump; 12: Support Structure; 1201: Hole; 121: Support Body; 122: Adhesive Layer; 13: Dispensing Layer; 14: Mold Material; 15: Cavity; 16: Electrical Connector; 17: Metal Layer; 18: Second Chip; 19: Filler Layer; 20: Carrier; 21: Carrier; 100: Packaging Unit. Detailed Implementation

[0037] The specific embodiments of this application will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this application and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0038] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0039] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0040] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0041] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0042] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0043] It should also be noted that the longitudinal section corresponding to the embodiment of this application can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0044] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] refer to Figures 2 to 4 , Figure 2 This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging structure 2a according to an embodiment of this application. Figure 3 yes Figure 2 An enlarged schematic diagram of the dashed box area in the semiconductor package structure 2a shown; Figure 4 yes Figure 2 A top view of the support structure in the semiconductor package structure 2a shown.

[0046] like Figures 2 to 4 As shown, the semiconductor packaging structure 2a of this application embodiment includes:

[0047] Redundancy layer 10 has solder pads 101;

[0048] The first chip 11 and the support structure 12 are arranged horizontally on the redistribution layer 10. The support structure 12 defines a plurality of holes 1201, which expose the solder pads 101 on the redistribution layer 10.

[0049] The adhesive layer 13 is connected between the first chip 11, the support structure 12 and the redistribution layer 10.

[0050] Here, the redistribution layer 10 can be composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies; this application does not specifically limit this. For example, it can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. The dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or their alloys.

[0051] Here, the first chip 11 can be a system-on-a-chip (SoC die). In a fan-out multi-chip module (FOMCM), the system-on-a-chip can be a core unit that integrates core computing and control functions, specifically including bare chips such as CPU (Central Processing Unit) and GPU (Graphics Processing Unit).

[0052] Here, the dispensing layer 13 can be an underfill (UF), specifically a capillary underfill (CUF), a molded underfill (MUF), or a non-conductive paste (NCP). The dispensing layer 13 can fill the space between the bottom surface of the first chip 11 and the top surface of the redistribution layer 10, the side surface of the first chip 11, the side surface of the support structure 12, and even the top surface of the support structure 12.

[0053] Here, the support structure 12 can be made of a high-strength, rigid reinforcing material such as metal or ceramic to suppress the risk of deformation. Multiple holes 1201 on the support structure 12 extend from its upper surface to its lower surface. The holes 1201 include, but are not limited to, cylindrical holes. Here, the support structure 12 can also be referred to as an exposed-pore reinforcing material.

[0054] Here, the support structure 12 can be positioned on the redistribution layer 10 to accommodate the dynamic random access memory (DRAM), which will then support the DRAM. The holes 1201 on it serve as connection channels between the DRAM and the redistribution layer 10. This avoids placing the DRAM on the redistribution layer 10 early in the manufacturing process. Instead, by using the placement position defined by the support structure 12, after molding is complete, the molding material above the support structure 12 and inside its holes 1201 is removed using laser drilling or etching processes, exposing the underlying solder pads 101. After confirming the structure is in good condition, the DRAM is then placed, thus avoiding the risk of DRAM being damaged along with other components, improving DRAM availability, and ultimately increasing yield and reducing scrap.

[0055] In some alternative embodiments, the support structure 12 and the first chip 11 are arranged side by side in the horizontal direction, so they do not overlap in the vertical direction. This avoids interference between the DRAM and the first chip 11 when the DRAM is subsequently installed.

[0056] In some alternative implementations, the support structure 12 and the first chip 11 do not contact each other, but are spaced apart. This further avoids interference between the DRAM of the subsequent components and the first chip 11.

[0057] In some alternative embodiments, the support structure 12 includes a support body 121 and an adhesive layer 122, the adhesive layer 122 connecting the support body 121 and the redistribution layer 10. Here, the support body 121 can be made of a high-strength, rigid reinforcing material such as metal or ceramic to suppress the risk of deformation. The adhesive layer 122 can be made of an organic-based adhesive, such as epoxy resin, or an inorganic adhesive; this application is not limited to this.

[0058] In some optional embodiments, the semiconductor package structure 2a of this application embodiment further includes: a plurality of bumps 1101 electrically connected between the first chip 11 and the redistribution layer 10, thereby realizing the electrical connection between the first chip 11 and the redistribution layer 10. Here, the bumps 1101 include, but are not limited to, solder bumps.

[0059] In some alternative embodiments, the adhesive layer 13 fills the gap between the first chip 11 and the redistribution layer 10, covers a plurality of bumps 1101, and extends to the sidewalls of the first chip 11 and the support structure 12. This achieves a good connection reinforcement effect and a protection effect for the bumps 1101.

[0060] In some optional embodiments, the semiconductor packaging structure 2a of this application embodiment further includes: a molding layer 14, covering the first chip 11 and the support structure 12, and an adhesive layer 13. Here, the molding layer 14 can be formed of various molding compounds. Exemplarily, molding compounds may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc. Exemplarily, the molding layer 14 may specifically be an epoxy molding compound (EMC).

[0061] In some alternative embodiments, the first chip 11 is exposed above the molding layer 14, or in other words, the upper surface of the first chip 11 is substantially flush with the upper surface of the molding layer 14. This allows the first chip 11 to be exposed for heat dissipation, improving heat dissipation performance.

[0062] In some alternative embodiments, the molding layer 14 defines a cavity 15 above the support structure 12, the cavity 15 exposing the support structure 12 and its holes 1201. Here, the defined cavity 15 can be used for subsequent placement of DRAM. Here, the cavity 15 and the holes 1201 can be formed by first performing overall molding to form a full-layer molding layer 14, and then removing the material of the molding layer 14 above the support structure 12 and inside its holes 1201 by methods such as laser drilling or etching.

[0063] In some alternative embodiments, the molding layer 14 further covers the sidewalls and bottom of the aperture 1201, exposing the solder pads 101 located at the bottom of the aperture 1201. Subsequently, the aperture 1201 will be filled with conductive material to electrically connect the solder pads 101 of the redistribution layer 10 to the DRAM above. Here, by covering the sidewalls and bottom of the aperture 1201 with the molding layer 14, and using the molding layer 14 as an insulating layer, short circuits can be avoided between the conductive material filled in the aperture 1201 and the support structure 12. Here, the thickness of the molding layer 14 material remaining on the sidewalls and bottom of the aperture 1201 is not limited, as long as it can expose the solder pads 101 for bonding and provide insulation.

[0064] In some alternative embodiments, the width of the cavity 15 is smaller than the width of the support structure 12. This allows a sealing layer 14 to be positioned above the support structure 12 at its edge, thus providing better fixation for the support structure 12.

[0065] In some alternative embodiments, the height of the support structure 12 is greater than the spacing between the first chip 11 and the redistribution layer 10. In other words, the upper surface of the support structure 12 is higher than the lower surface of the first chip 11. This ensures that damage to the dispensing layer 13 is reduced during the manufacturing process, such as during the formation of the cavity 15, and ensures that the dispensing layer 13 secures the connection to the first chip 11 and protects the bump 1101.

[0066] In some alternative implementations, refer to Figure 4 Multiple solder pads 101 are arranged in an array, and correspondingly, multiple holes 1201 are arranged in an array to expose the solder pads 101 respectively. The inner walls and bottom of the holes 1201 are covered by a molding seal layer 14, but the solder pads 101 are exposed from the molding seal layer 14. Adjacent holes 1201 are spaced apart by a certain distance and do not contact each other to avoid interference / short circuit risks.

[0067] In some alternative implementations, refer to Figure 5 When the spacing between two adjacent solder pads 101 is small, the corresponding two adjacent holes 1201 may connect to each other because the spacing is too close. However, after the molding process and the process of opening the cavity 15, the molding layer 14 retained on the side wall of the hole 1201 can fill the position where the two adjacent holes 1201 are connected, so that the two adjacent holes 1201 are separated by the molding layer 14, thereby preventing the conductive materials filled in the two adjacent holes 1201 from contacting each other and short-circuiting.

[0068] In some optional embodiments, the semiconductor package structure 2a of this application embodiment further includes an electrical connector 16 disposed on the side surface of the redistribution layer 10 facing away from the molding layer 14. For example, the electrical connector 16 may be a C4 (Controlled Collapsed Chip Connection) bump.

[0069] As described above, the semiconductor packaging structure 2a of the present application embodiment has been briefly described.

[0070] This application pre-installs a support structure 12 at the designated placement position for DRAM on the redistribution layer 10. The support structure 12 has holes 1201 to expose the solder pads 101 on the redistribution layer 10. This defines the placement position for the DRAM using the support structure 12, thereby shifting the DRAM bonding to the redistribution layer 10 from before molding to after molding. Specifically, after molding and die cutting, the molding layer 14 above the support structure 12 and within its holes 1201 can be removed using laser drilling or etching to expose the solder pads 101. Electrical testing confirms the good structure after molding before the DRAM is placed in. This avoids the risk of DRAM damage due to the loss of other components or materials, significantly improves DRAM availability, allows for better fan-out of the DRAM, increases product yield, enhances overall packaging stability, and reduces structural failure risk and manufacturing costs.

[0071] Next, refer to Figure 6 , Figure 6 This is a longitudinal cross-sectional view of a semiconductor packaging structure 6a according to an embodiment of this application. Figure 6 The semiconductor package structure 6a shown is similar to Figure 2 The semiconductor package structure 2a shown differs in that:

[0072] In the semiconductor package structure 6a, the sidewalls and bottom of the hole 1201 are covered by a dispensing layer 13, exposing the solder pad 101. This is because, when the dispensing layer 13 is set in the manufacturing process, the dispensing layer 13 can be made to cover the support structure 12, thereby achieving the coverage of the sidewalls and bottom of the hole 1201 by the dispensing layer 13.

[0073] Next, refer to Figure 7 , Figure 7 This is a longitudinal cross-sectional view of a semiconductor packaging structure 7a according to an embodiment of this application. Figure 7 The semiconductor package structure 7a shown is similar to Figure 2 The semiconductor packaging structure 2a shown and Figure 6 The semiconductor package structure 6a shown differs in that:

[0074] In the semiconductor package structure 7a, in a portion of the holes 1201, the sidewalls and bottom of the holes 1201 are covered by a dispensing layer 13, exposing the solder pads 101; in another portion of the holes 1201, the sidewalls and bottom of the holes 1201 are covered by a molding layer 14, exposing the solder pads 101. This is because, when the dispensing layer 13 is set in the manufacturing process, the dispensing layer 13 can cover a portion of the support structure 12, and the uncovered portion is subsequently covered by the molding layer 14, thereby ensuring that the sidewalls and bottom of a portion of the holes 1201 are covered by the dispensing layer 13, while the sidewalls and bottom of another portion of the holes 1201 are covered by the molding layer 14.

[0075] Next, refer to Figure 8 , Figure 8 This is a longitudinal cross-sectional view of a semiconductor packaging structure 6a according to an embodiment of this application. Figure 8 The semiconductor package structure 8a shown is similar to Figure 2 The semiconductor package structure 2a shown differs in that:

[0076] In the semiconductor package structure 8a, a metal layer 17 is further included, which fills the hole 1201, and further, the metal layer 17 is electrically connected to the solder pad 101 exposed at the bottom of the hole 1201.

[0077] Here, the metal layer 17 can be tin or a tin alloy. In terms of manufacturing process, tin-based solder, such as tin balls, can be melted and filled into the cavity 1201, and the metal layer 17 can be formed after solidification.

[0078] Here, there is a gap between the metal layer 17 and the support structure 12, which is filled by the molding seal layer 14 attached to the sidewalls and bottom of the hole 1201. In other words, the space occupied by the molding seal layer 14 attached to the sidewalls and bottom of the hole 1201 is the gap between the metal layer 17 and the support structure 12.

[0079] In some alternative embodiments, the adhesive layer 13 may fill the gap between the metal layer 17 and the support structure 12, such as... Figure 6 As shown; or, alternatively: in one part of the holes 1201, the gap between the metal layer 17 and the support structure 12 is filled by the adhesive layer 13; in the other part of the holes 1201, the gap between the metal layer 17 and the support structure 12 is filled by the molding seal layer 14, as shown. Figure 7 As shown.

[0080] In some optional implementations, the semiconductor packaging structure 8a of this application embodiment further includes: a second chip 18 disposed on the support structure 12 and electrically connected to the metal layer 17.

[0081] Here, the second chip 18 can be a dynamic random access memory (DRAM).

[0082] In some alternative implementations, the bottom of the second chip 18 has multiple connection pads ( Figure 8 (Not shown in the image) Multiple connection pads are electrically connected to the metal layer 17 in multiple holes 1201, and then connected to multiple solder pads 101 on the redistribution layer 10 through the metal layer 17, thereby realizing the electrical interconnection between the second chip 18 and the redistribution layer 10.

[0083] In some optional embodiments, the semiconductor packaging structure 8a of this application further includes: a filler layer 19 covering the second chip 18. Here, the filler layer 19 may be an underfill adhesive or a molding compound, etc., and this application is not limited thereto.

[0084] In some alternative embodiments, the second chip 18 is located within the cavity 15, and the cavity 15 is filled with an adhesive layer 19. This protects the second chip 18.

[0085] In some alternative embodiments, the upper surface of the molding layer 14 and the upper surface of the filler layer 19 are substantially flush, the first chip 11 is exposed in the molding layer 14, and the second chip 18 is completely embedded in the filler layer 19.

[0086] Next, refer to Figures 9 to 10 , Figures 9 to 10 This is a schematic diagram illustrating the manufacturing steps of a semiconductor packaging structure according to an embodiment of this application. Figures 9 to 10 As shown, the manufacturing process of the semiconductor packaging structure of this application may include the following steps.

[0087] Step S1: Provide a carrier 20 and fabricate a redistribution layer 10 on the carrier 20. The redistribution layer 10 includes solder pads 101 located on its surface. There may be multiple solder pads 101.

[0088] Step S2: Provide a support structure 12, which includes a support body 121 and an adhesive layer 122. In this step, the support body 121 is fixed to a first region (e.g., the right side) of the redistribution layer 10 via the adhesive layer 122. Here, the support structure 12 may include a plurality of holes 1201, each hole 1201 exposing a solder pad 101.

[0089] Step S3: Provide a first chip 11, which may be a system-on-a-chip. Position the first chip 11 with its active side facing the redistribution layer 10, and attach it to the second region (e.g., the left side) of the redistribution layer 10 using flip-chip bonding (FCB). The electrical connection between the two is achieved through bumps 1101. Then, fill with underfill adhesive (UF) as a dispensing layer 13, which connects the first chip 11, the support structure 12, and the redistribution layer 10.

[0090] Step S4: Perform molding to form a molding layer 14 covering the upper surface of the first chip 11, the support structure 12, the dispensing layer 13 and the redistribution layer 10.

[0091] Step S5: Trim the molding layer 14 and remove the carrier 20. At this time, the redistribution layer 10 is supported by the molding layer 14.

[0092] Step S6: An electrical connector 16 is disposed on the surface of the redistribution layer 10 facing away from the molding layer 14. For example, C4 bumps can be disposed as electrical connectors 16 by physical vapor deposition (PVD) technology and C4 bump metallization process.

[0093] Step S7: On the side of the redistribution layer 10 where the electrical connector 16 is located, another carrier 20 is provided as a support structure. Then, the molding layer 14 is thinned by, for example, panel grinding, so that the first chip 11 is exposed in the molding layer 14, and the upper surface of the first chip 11 is substantially flush with the upper surface of the molding layer 14. Thus, a packaging unit 100 including the redistribution layer 10, the first chip 11, and the support structure 12 is obtained.

[0094] It is worth noting that the above steps S1-S7 can be performed using a panel-level process, and many packaging units 100 will be formed on a single panel.

[0095] Step S8: The monomerization operation is completed by cutting to obtain an independent single packaging unit 100, and then the carrier 20 is removed.

[0096] Step S9: Provide a carrier 21, which may include multiple grooves. Place multiple packaging units 100 into the multiple grooves on the carrier 21 respectively, wherein the side surface of the packaging unit 100 with the electrical connector 16 faces the carrier 21. Here, the carrier 21 is used to support and position the multiple packaging units 100.

[0097] Step S10: The molding layer 14 above the support structure 12 and inside the hole 1201 are removed by laser drilling or chemical etching, thereby forming a cavity 15 defined by the molding layer 14 above the support structure 12, exposing the support structure 12 and its hole 1201, thus exposing the solder pad 101 below through the hole 1201. Here, a certain thickness of molding layer 14 material is retained on the sidewalls and bottom of the hole 1201, so that the redistribution layer 10 at the bottom only exposes the solder pad 101 and not other parts.

[0098] Step S11: Clean and dry the packaging unit 100.

[0099] Step S12: Remove the packaging unit 100 from the carrier 21, thus obtaining the following... Figure 2 The semiconductor package structure 2a is shown. The semiconductor package structure 2a can be shipped as a finished product, and the user can then install the required components in the cavity 15.

[0100] Step S13: Optionally, a second chip 18 (e.g., DRAM) can be further disposed within the cavity 15. The bottom of the second chip 18 may have solder balls, which can be melted and filled into the cavity 1201 through processes such as reflow soldering, and solidified to form a metal layer 17 connecting the second chip 18 and the solder pad 101. Here, since the sidewalls and bottom of the cavity 1201 retain a certain thickness of molding layer 14 material, the internal metal layer 17 will not short-circuit with the support structure 12 (when it is a conductive material).

[0101] Then, a filler layer 19 can be further provided within the cavity 15 to encapsulate and protect the second chip 18, and to fill the cavity 15 completely. Thus, the desired result is obtained. Figure 8 The semiconductor package structure 8a shown is illustrated.

[0102] Although this application has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this application as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this application and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this application. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this application.

Claims

1. A semiconductor packaging structure, characterized in that, include: Redundancy layer with solder pads; A first chip and a support structure are horizontally arranged on the redistribution layer, wherein the support structure defines a plurality of holes that expose the solder pads on the redistribution layer. A dispensing layer connects the first chip, the support structure, and the redistribution layer.

2. The semiconductor packaging structure according to claim 1, characterized in that, The support structure includes a support body and an adhesive layer, wherein the adhesive layer connects the support body and the redistribution layer.

3. The semiconductor packaging structure according to claim 1, characterized in that, Further includes: A metal layer is filled into the cavity, and the metal layer is electrically connected to the solder pad.

4. The semiconductor packaging structure according to claim 3, characterized in that, Further includes: A sealing layer covers the sidewalls and bottom of the hole and exposes the solder pads.

5. The semiconductor packaging structure according to claim 4, characterized in that, The molding layer fills the gap between the metal layer and the support structure.

6. The semiconductor packaging structure according to claim 4, characterized in that, The molding layer further covers the first chip, the support structure, and the dispensing layer, and defines a cavity above the support structure, the cavity exposing the support structure and the hole.

7. The semiconductor packaging structure according to claim 6, characterized in that, Further includes: The second chip is disposed on the support structure and electrically connected to the metal layer.

8. The semiconductor packaging structure according to claim 7, characterized in that, Further includes: A filler layer is used to fill the cavity and cover the second chip, which is located inside the cavity.

9. The semiconductor packaging structure according to claim 8, characterized in that, The upper surface of the molding layer and the upper surface of the filler layer are substantially flush. The first chip is exposed in the molding layer, and the second chip is completely embedded in the filler layer.

10. The semiconductor packaging structure according to claim 1, characterized in that, Further includes: Multiple bumps are electrically connected between the first chip and the redistribution layer; The adhesive layer fills the gap between the first chip and the redistribution layer, covers the plurality of bumps, and extends to the sidewalls of the first chip and the sidewalls of the support structure.

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