Guide hole covering structure

Abstract

The present disclosure relates to a via wrap structure that prevents the top via from chemically reacting with residue or other contaminants by reducing metal atom migration and line growth, solving the reliability problem of local silicon interposers in semiconductor packages, thereby improving long-term reliability. The via wrap structure integrates multiple barrier layers including SiOCH, SiOx, SiON, SiNx, CuOx, Ta, Ti, TaN, TiN, Mo, MoN, TaC, TiC, TaCN, or TiCN, alone or in any combination, to enhance electrical performance and long-term reliability. The method of forming the wrap or barrier structure involves combining wrap layer deposition, patterning, wet etching, isotropic or non-isotropic dry etching processes, flowable dielectric deposition or spin-on dielectric, and chemical mechanical planarization (CMP) to ensure robust and reliable connections.

Description

Technical Field

[0001] The embodiments of this utility model relate to semiconductor technology, and more particularly to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] In semiconductor packaging technology, the need for multi-level connections between processors and memory is constantly increasing to achieve wide signal bandwidth and reduce signal latency. Various connection schemes can include copper-to-copper, copper-to-bump, copper-to-microbump with underfill, or oxide-to-oxide bonding. However, copper vias (because copper is one of the most common via materials) directly exposed to polished tape can introduce reliability issues due to copper migration, copper wire growth, and copper loss. Individual or arbitrary combinations of copper migration, copper wire growth, and copper loss can lead to performance degradation, electrical failures, and compromised long-term reliability of the packaged device. Copper atoms can migrate along the via interface or remain on the polished tape, accumulating at specific locations and forming copper wires, which can potentially cause short circuits or alter electrical characteristics.

[0003] However, connecting copper vias between the redistribution layer (RDL) in the local silicon interposer and the RDL in the semiconductor package presents additional challenges. The transition from one substrate to another introduces additional challenges, such as differences in coefficient of thermal expansion (CTE) and stress distribution, exacerbating via-related failure risks. Electromigration driven by the movement of copper atoms under current can lead to copper wire growth, porosity, or cracks, resulting in circuit failure and impacting long-term reliability. Existing solutions, such as post-cleaning processes or polymer protective layers, often leave residues or introduce additional thermal mismatches and stresses, further exacerbating reliability issues. Addressing these problems is crucial for ensuring the robustness and lifespan of semiconductor packages. Utility Model Content

[0004] According to one embodiment of the present invention, a via covering structure is provided, comprising: a top via formed above a redistribution layer; and a conformal covering material blanket layer formed above the sidewall of the top via, which exposes the top surface of the top via such that other interconnects are formed on the top surface of the top via.

[0005] In some embodiments, the via covering structure further includes a metal liner.

[0006] In some embodiments, the via covering structure is formed as a self-aligned spaced covering structure.

[0007] In some embodiments, the self-aligned spacing covering structure is formed on the sidewall of the top guide hole.

[0008] In some embodiments, the guide hole covering structure is formed as a tapered foot covering structure.

[0009] In some embodiments, the tapered foot covering structure is formed on the sidewall of a top guide hole.

[0010] In some embodiments, the guide hole covering structure is formed as an L-shaped foot covering structure.

[0011] In some embodiments, the L-shaped foot covering structure is formed on the sidewall of a top guide hole.

[0012] In some embodiments, the via covering structure is formed as a blanket covering structure.

[0013] In some embodiments, the blanket covering structure is formed on the sidewall of the top guide hole and extends continuously above the redistribution layer. Attached Figure Description

[0014] The embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this utility model.

[0015] Figure 1A A top view is shown of an exemplary intermediate local silicon interposer die with a via structure designed to connect to another LSI die or other package.

[0016] Figure 1B It shows along Figure 1A The image shows a vertical cross-sectional view of an exemplary local silicon interposer grain taken along line A-A', which can be used during the fabrication of interconnects in packages as described in this invention.

[0017] Figure 2 This is a series of vertical cross-sectional schematic diagrams depicting the sequence of process steps for forming intermediate covering structures of various types and embodiments of the desired structure that can be ultimately produced, according to one aspect of the present invention.

[0018] Figure 3 This is a series of vertical cross-sectional schematic diagrams depicting subsequent process steps for forming the coating structure of various embodiments according to one aspect of the present invention, which may include flowable oxides or spin-coated dielectrics consistent with the structures of various embodiments of the present invention.

[0019] Figure 4 This is a series of vertical cross-sectional schematic diagrams depicting subsequent process steps for forming the coating structure of various embodiments according to one aspect of the present invention, which may include a flowable oxide or spin-coated dielectric that is consistent with the structure of various embodiments by partial etch-back.

[0020] Figure 5These are a series of vertical cross-sectional schematic diagrams depicting the subsequent process steps that form the covering structures of various embodiments.

[0021] Figure 6A This is an illustrative top view of the local silicon interposer after various dielectric deposits have been completed on the surface of the top via and the local silicon interposer.

[0022] Figure 6B This illustrates the process of depositing various dielectrics along the surface of the top via and local silicon interposer after completing the deposition of these dielectrics. Figure 6A The vertical cross-sectional view of the vias and redistribution layer of the local silicon interposer taken by line A-A'.

[0023] Figure 7A This is an exemplary top view of a localized silicon interlayer after the abrasive tape has been attached to the surface of a continuous coating layer formed through multiple deposition steps.

[0024] Figure 7B This is an illustrative vertical cross-sectional view of a local silicon interposer taken along line A-A' in Figure 7, after the abrasive tape has been attached to the surface of the continuous coating layer formed through multiple deposition steps.

[0025] Figure 8A This is an exemplary top view of a localized silicon interlayer after the polishing tape has been peeled off from the surface of a continuous coating layer formed through multiple deposition steps.

[0026] Figure 8B This is an illustrative vertical cross-sectional view of a local silicon interposer taken along line A-A' in Figure 8 after the polishing strip is peeled off from the surface of the continuous coating layer formed through multiple deposition steps.

[0027] Figure 9A This is an exemplary top view of a local silicon interlayer after the deposition of a flowable oxide or dielectric on the surface of a continuous coating layer formed through multiple coating layer deposition steps.

[0028] Figure 9B After the deposition of flowable oxides or dielectrics on the surface of a continuous coating layer formed through multiple coating layer deposition steps is completed, along... Figure 9A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0029] Figure 10A This is an illustrative top view of the encapsulation structure on a localized silicon interlayer after chemical mechanical polishing (CMP) of a flowable oxide or spin-coated dielectric stopped on the top surface of a top via.

[0030] Figure 10B After chemical mechanical polishing (CMP) of a flowable oxide or spin-coated dielectric that stops on the top surface of the top guide hole, Figure 10AAn illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0031] Figure 11A yes Figure 10A and Figure 10B An illustrative top view of the encapsulation structure on a localized silicon interlayer after partial etch-back of a flowable oxide or spin-coated dielectric, as shown.

[0032] Figure 11B yes Figure 10A and Figure 10B After partial etchback of the flowable oxide or spin-coated dielectric shown, along... Figure 11A An illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0033] Figure 12A yes Figure 10A and Figure 10B An illustrative top view of the encapsulation structure on a local silicon interlayer after complete etch-back of the flowable oxide or spin-coated dielectric shown.

[0034] Figure 12B yes Figure 10A and Figure 10B After complete etchback of the flowable oxide or spin-coated dielectric shown, along Figure 12A An illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0035] Figure 13A This is an exemplary top view of the local silicon interposer after the anisotropic etching of various dielectric layers on the surface of the top via and the formation of spacers around the top via.

[0036] Figure 13B The diagram illustrates the anisotropic etching of various dielectric layers on the surfaces of the top via and the local silicon interposer, followed by the formation of spacers around the top via, and then... Figure 13A An illustrative vertical cross-sectional view of the top guide hole taken by line A-A'.

[0037] Figure 14A This is an illustrative top view of the local silicon interposer after the abrasive tape on the surface of the top via, spacer, and local silicon interposer has been attached.

[0038] Figure 14B After the abrasive tape is attached to the surface of the top via, spacer, and local silicon interposer, it is along... Figure 14A An illustrative cross-sectional view of a local silicon interposer taken by line A-A'.

[0039] Figure 15AThis is an illustrative top view of the local silicon interposer after the polishing tape has been peeled off from the surface of the top via, spacer, and local silicon interposer.

[0040] Figure 15B After the polishing tape is peeled off from the surface of the top via, spacer cover, and local silicon interposer, along... Figure 15A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0041] Figure 16A This is an illustrative top view of the local silicon interposer after the deposition of flowable oxides or spin-coated dielectrics on the surfaces of the spacer, top vias, and local silicon interposer.

[0042] Figure 16B After the flowable oxide or spin-coated dielectric is deposited on the surface of the spacer, top via, and local silicon interposer, along... Figure 16A An illustrative cross-sectional view of a local silicon interposer taken by line A-A'.

[0043] Figure 17A This is an illustrative top view of the coating structure on a localized silicon interposer after chemical mechanical polishing (CMP) of a flowable oxide or spin-coated dielectric stopped on the top vias and spacers.

[0044] Figure 17B After chemical mechanical polishing (CMP) of the flowable oxide or spin-coated dielectric stopping on the top guide hole and spacer cover, along... Figure 17B An illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0045] Figure 18A yes Figure 17A and Figure 17B An illustrative top view of the encapsulation structure on a localized silicon interlayer after partial etch-back of a flowable oxide or spin-coated dielectric, as shown.

[0046] Figure 18B yes Figure 17A and Figure 17B After partial etchback of the flowable oxide or spin-coated dielectric shown, along... Figure 18A An illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0047] Figure 19A yes Figure 17A and Figure 17B An illustrative top view of the encapsulation structure on a local silicon interlayer after complete etch-back of the flowable oxide or spin-coated dielectric shown.

[0048] Figure 19B yes Figure 17A and Figure 17B After complete etchback of the flowable oxide or spin-coated dielectric shown, along Figure 19A An illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0049] Figure 20A This is an exemplary top view of the local silicon interposer after various dielectrics have been deposited on the surface of the top via and the local silicon interposer, and after the photoresist patterning on the top via has been completed.

[0050] Figure 20B After the deposition of various dielectrics on the surface of the top via and the local silicon interposer, and the photoresist patterning on the top via is completed, along... Figure 20A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0051] Figure 21A This is an illustrative top view of the local silicon interposer after isotropic ion etching or wet etching following photoresist patterning on the surface of the top via and the local silicon interposer.

[0052] Figure 21B After isotropic ion etching or wet etching following photoresist patterning on the top via and local silicon interposer surface, along... Figure 21A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0053] Figure 22A This is an illustrative top view of the local silicon interposer after the photoresist has been stripped from the surface of the top via and the local silicon interposer.

[0054] Figure 22B After stripping the photoresist from the surface of the top via and the local silicon interposer, along... Figure 22A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0055] Figure 23A This is an exemplary top view of a local silicon interposer after the abrasive tape on the surface of the top via formed by wet etching or isotropic ion etching has been attached.

[0056] Figure 23B After the abrasive tape is attached to the surface of the top guide hole formed by wet etching or isotropic ion etching, along... Figure 23A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0057] Figure 24A This is an exemplary top view of the local silicon interposer after the surface of the covering structure has been stripped of the polishing tape formed by isotropic etching or wet etching.

[0058] Figure 24B After the polishing strip is peeled off from the surface of the local silicon interposer and the overlay structure formed by isotropic etching or wet etching, along... Figure 24A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0059] Figure 25A This is an illustrative top view of the local silicon interposer and the surface of the encapsulated structure formed by wet etching or isotropic dry etching, after the complete deposition of flowable oxides or spin-coated dielectrics.

[0060] Figure 25B After the flowable oxide or spin-coated dielectric is completely deposited on the surface of the local silicon interposer and coating structure formed by wet etching or isotropic dry etching, it flows along... Figure 25B An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0061] Figure 26A This is an illustrative top view of the encapsulation structure on a localized silicon interposer after chemical mechanical polishing (CMP) of a flowable oxide or spin-coated dielectric stopped on a top via.

[0062] Figure 26B After chemical mechanical polishing (CMP) of the flowable oxide or spin-coated dielectric that stops at the top guide hole, along... Figure 26A An illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0063] Figure 27A yes Figure 26A and Figure 26B An illustrative top view of the encapsulation structure on a localized silicon interlayer after partial etch-back of a flowable oxide or spin-coated dielectric, as shown.

[0064] Figure 27B yes Figure 26A and Figure 26B After partial etchback of the flowable oxide or spin-coated dielectric shown, along... Figure 27A An illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0065] Figure 28A yes Figure 26A and Figure 26B An illustrative top view of the encapsulation structure on a local silicon interlayer after complete etch-back of the flowable oxide or spin-coated dielectric shown.

[0066] Figure 28B yes Figure 26A and Figure 26BAfter complete etchback of the flowable oxide or spin-coated dielectric shown, along Figure 28A An exemplary cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0067] Figure 29A This is an illustrative top view of the local silicon interposer after photoresist patterning on the surface of the top via and the local silicon interposer, followed by anisotropic reactive ion etching or dry etching.

[0068] Figure 29B After photoresist patterning on the surface of the top via and local silicon interposer, reactive ion etching or dry etching is performed along... Figure 29A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0069] Figure 30A This is an illustrative top view of the local silicon interposer after the photoresist has been stripped from the surface of the top via and the local silicon interposer.

[0070] Figure 30B After stripping the photoresist from the surface of the top via and the local silicon interposer, along... Figure 30A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0071] Figure 31A This is an illustrative top view of a local silicon interposer after the abrasive tape on the surface of the top via formed by anisotropic reactive ion etching or dry etching has been attached.

[0072] Figure 31B After the abrasive tape is attached to the surface of the top guide hole formed by reactive ion etching or dry etching, along the... Figure 31A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0073] Figure 32A This is an exemplary top view of the local silicon interposer after the surface polishing tape has been removed from the local silicon interposer and overlay structure formed by reactive ion etching or dry etching.

[0074] Figure 32B It is the process of peeling off the polishing tape attached to the surface of the localized silicon interposer and overlay structure formed by reactive ion etching or dry etching, along... Figure 32A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0075] Figure 33A This is an exemplary top view of the local silicon interposer and the surface of the encapsulated structure after the deposition of flowable oxides or spin-coated dielectrics on the surface formed by anisotropic reactive ion etching or dry etching.

[0076] Figure 33B After the deposition of flowable oxides or spin-coated dielectrics on the surface of local silicon interposers and covering structures formed by anisotropic reactive ion etching or dry etching, along... Figure 33A An illustrative vertical cross-sectional view of a local silicon interposer taken by line A-A'.

[0077] Figure 34A This is an illustrative top view of the encapsulation structure on a localized silicon interposer after chemical mechanical polishing (CMP) of a flowable oxide or spin-coated dielectric stopped on a top via.

[0078] Figure 34B After chemical mechanical polishing (CMP) of the flowable oxide or spin-coated dielectric that stops at the top guide hole, along... Figure 34A An exemplary cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0079] Figure 35A yes Figure 34A and Figure 34B An illustrative top view of the encapsulation structure on a localized silicon interlayer after partial etch-back of a flowable oxide or spin-coated dielectric, as shown.

[0080] Figure 35B yes Figure 34A and Figure 34B After partial etchback of the flowable oxide or spin-coated dielectric shown, along... Figure 35A An illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0081] Figure 36A yes Figure 34A and Figure 34B An illustrative top view of the encapsulation structure on a local silicon interlayer after complete etch-back of the flowable oxide or spin-coated dielectric shown.

[0082] Figure 36B yes Figure 34A and Figure 34B After complete etchback of the flowable oxide or spin-coated dielectric shown, along Figure 36A An illustrative vertical cross-sectional view of the encapsulation structure on a local silicon interposer, taken by line A-A'.

[0083] Figure 37 It is a three-dimensional perspective view taken after the formation of the representative claim structure is completed, measuring the distance between the coverings, the height, the thickness of the coverings, and the diameter of the guide holes.

[0084] Figure 38This is a process flow diagram illustrating the steps of forming a local silicon interposer having a top via including a barrier structure, according to various embodiments of the present invention.

[0085] Figure 39 This is a process flow diagram illustrating the steps of forming a local silicon interposer having a top via including a barrier structure, according to various embodiments of the present invention.

[0086] Figure 40 This is a process flow diagram illustrating the steps of forming a local silicon interposer having a top via including a barrier structure, according to various embodiments of the present invention.

[0087] The reference numerals in the attached figures are explained as follows:

[0088] 1: Coating layer

[0089] 2: Light Obscuration

[0090] 3: Cutting the outline

[0091] 4: Undercut profile

[0092] 5: Grinding belt

[0093] 6: Dielectric

[0094] 40:Substrate

[0095] 50: Semiconductor material layer

[0096] 60, 90: Guide holes

[0097] 70: Deep trench capacitor

[0098] 80: Redistribution layer

[0099] 110, 111, 112, 113, 120, 121, 122, 123, 130, 131, 132, 133, 140, 141, 142, 143: Encapsulation structure

[0100] 500: Intermediary Layer

[0101] S0, S1, S2, S3, S4, S1A, S2A, S3A, S4A, S1B, S2B, S3B, S4B, S1C, S2C, S3C, S4C, 3802, 3804, 3806, 3808, 3810, 3812, 3814, 3816, 3902, 3904, 3906: Steps 3800, 3900, 4000: Method Detailed Implementation

[0102] Numerous embodiments or examples are provided below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, embodiments of the present invention may repeat reference values ​​and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0103] Furthermore, spatially relative terms such as "below," "under," "lower," "above," and "higher" may be used to facilitate the description of the relationship between one or more components or features in the drawings and another component or feature(s). The spatially relative terms are intended to include different orientations of the device in use or operation, as well as the orientations described in the drawings. Generally, unless otherwise explicitly stated, all devices of this invention are rotatable, and the spatially relative terms used herein are similarly interpreted accordingly. Unless otherwise explicitly stated, each element having the same reference numerals is assumed to have the same material composition and a thickness within the same thickness range.

[0104] Various embodiments of this invention propose solutions to problems caused by metal migration and wire growth by introducing an integrated dielectric barrier into a via barrier structure (also known as a cladding structure) to prevent metal migration and wire growth. The via barrier structure enhances electrical performance and improves the reliability of semiconductor packages, making them suitable for high-performance computing (HPC).

[0105] Various embodiments of this invention target high-performance computing (HPC) architectures, in which silicon interposers stack memory, CPU, and GPU to enhance the overall performance and bandwidth of a computer chip. High-performance applications such as artificial intelligence (AI) utilize heterogeneous integration where logic chips and numerous memory chips are contained within a single package. The concept of heterogeneous integration plays a crucial role in high-performance computing (HPC) architectures. In this case, the silicon interposer acts as a bridge and enhances the overall performance and bandwidth of the computer chip. Notably, this approach is particularly well-suited for artificial intelligence (AI) applications, which leverage seamless coordination between logic chips and a large number of memory chips.

[0106] Metallic vias (e.g., copper vias) can be used in interposers because materials such as copper, gold, silver, and tungsten are excellent conductors that allow for efficient signal transmission between different redistribution layers within a package. During interposer interconnection, metallic vias may be exposed to chemical reactions in subsequent processing. This exposure can make the vias susceptible to electromigration, where the movement of metal atoms under current flow can lead to metal wire growth, porosity, or cracks, potentially causing circuit failures and affecting the long-term reliability of the device. Appropriate barrier layers can help prevent metal wire formation, avoiding impacts on long-term device reliability and ensuring electrical performance.

[0107] According to one embodiment of this utility model, a via (e.g., a copper via) with a cladding or barrier structure for use in an interposer and a method thereof are disclosed. The cladding or barrier structure can be formed using different types of oxides, metal substrates, and integration schemes to create an oxide cladding structure. The cladding or barrier structure prevents the metal material from reacting with the abrasive belt. Otherwise, metal material reaction could lead to the migration of metal atoms and / or the growth of undesirable or unintended metal lines. Such migration and / or undesirable or unintended metal line growth could be detrimental to the long-term reliability and electrical requirements of the device. The integration of the cladding layer not only mitigates the impact of undesirable or unintended metal lines that could lead to related reliability problems but also ensures an overall low dielectric constant and stress engineering opportunities across different types of interposers.

[0108] Figure 1A A top view of an interposer 500 used in a semiconductor package is shown, illustrating the layout of the top via 90. Figure 1A The placement and distribution of the top vias 90 in the interposer layer 500 are highlighted, which facilitates vertical electrical connections between different layers and components of the semiconductor package. Figure 1A The top view clearly illustrates how the top vias 90 are patterned to ensure optimal signal routing and power distribution across the interposer layer 500. In this embodiment, the distance between adjacent top vias 90 can be, but is not limited to, about 1 to 500 micrometers. Such a distance provides design flexibility to accommodate various routing requirements. The height of the top vias 90 can be, but is not limited to, about 1 to 100 micrometers, while their width can vary, but is not limited to, about 1 to 100 micrometers. These dimensions can be selected to optimize electrical performance and reliability while maintaining the structural integrity of the interposer layer.

[0109] See Figure 1BA first exemplary structure according to an embodiment of the present invention is described. An exemplary structure of the unit area (UA) of the interposer 500 includes a substrate 40. Generally, the substrate 40 comprises and / or is substantially composed of at least one material selected from insulating materials, semiconductor materials, and metallic materials. In one embodiment, the substrate 40 may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 40 may include a semiconductor material layer 50 at least on its upper portion. The semiconductor material layer 50 may be a surface portion of an intrinsically semiconductor substrate, or may be a top semiconductor layer of a semiconductor on insulator (SOI) substrate. In one embodiment, the semiconductor material layer 50 may include a single-crystal semiconductor material, such as single-crystal silicon. In one embodiment, the substrate 40 may include a single-crystal silicon substrate.

[0110] A deep trench capacitor 70 may be formed within the interposer 500. The deep trench capacitor 70 may function as a memory device (such as a DRAM memory cell). The memory device may be designed to optimize memory performance and integration within a high-density semiconductor package. The deep trench capacitor 70 may be formed by forming trenches that are etched deep into the silicon substrate and filled with a high-dielectric-constant material and metal electrodes.

[0111] A local silicon interposer (LSI) 500 can integrate vias 60 to facilitate high-speed and reliable electrical connections between various integrated circuits (ICs) in advanced semiconductor packages. The vias 60 in the LSI 500 can be vertically formed within the interposer substrate 40. The vias 60 are formed by patterning and etching cavities within the substrate 40 and depositing a conductive material (such as copper) within the cavities. An optional barrier layer liner (not shown) can also be conformally deposited into the etched cavities to line them before depositing the conductive material. The vias 60 can be used as channels for electrical signals and power distribution. By providing direct electrical paths between redistribution layers (RDLs) of different ICs, the vias 60 can reduce signal delay and increase bandwidth. This characteristic is highly advantageous for high-performance computing applications. In subsequent processing, the vias 60 can be included in independent contact areas at the bottom of the LSI 500.

[0112] The local silicon interposer 500 may also include a redistribution layer (RDL) 80. The redistribution layer 80 provides rerouting of electrical interconnects to facilitate high-density and high-performance packaging solutions. The fabrication process of the redistribution layer 80 typically involves depositing a dielectric layer on the interposer substrate 40, followed by patterning, etching, and connecting conductive interconnects that may be formed within the dielectric layer. The conductive interconnects can be formed from plated copper or any conductive material. The conductive material can be planarized and patterned to define RDL traces, and then covered with other dielectric layers to provide insulation and protection. This process can be repeated to create multiple layers within the redistribution layer 80, enabling complex routing schemes. The redistribution layer 80 present in the local silicon interposer 500 offers several advantages, including the ability to achieve fine-pitch interconnects, improved signal integrity through shorter and more direct routing paths, and enhanced integration density by allowing dies to be vertically stacked. Top vias 90 may be formed as part of the redistribution layer (RDL) 80, facilitating vertical interconnects between different layers and components within the semiconductor package. As part of the redistribution layer 80, these top vias 90 provide robust and highly conductive pathways to ensure efficient signal transmission and power delivery across various integrated circuits. By establishing direct and reliable connections between the redistribution layer 80 and other packaged components, the top vias 90 improve the overall functionality and performance of high-density and high-speed semiconductor device applications, such as artificial intelligence, data centers, and high-performance computing. In some embodiments, a blanket layer of conductive material (e.g., copper) may be deposited or plated over the top layer of the redistribution layer 80. The blanket layer may be masked, patterned, and etched to form the individual top vias 90. In alternative embodiments, a dielectric layer may be deposited over the top layer of the redistribution layer 80 and patterned using a photolithography process. The pattern may be transferred to the dielectric layer and subsequently etched to form cavities over the redistribution layer 80. Conductive metal material may be deposited or plated in the cavities to form the top vias 90. In one embodiment, an interposer comprising a combination of vias 60 and the redistribution layer 80 formed within a semiconductor substrate to achieve high-performance electrical connections. This device can further integrate deep trench capacitors 70, which enhances the overall functionality of the device by providing additional memory integration within the local silicon interposer 500.

[0113] Figure 2 A series of fabrication steps are shown for intermediate building blocks of cladding structures 110, 120, 130, and 140 formed on a top via 90 as part of a local silicon interposer (LSI) die. Various interposer structures 500 illustrate different types of intermediate cladding layers that can be used to form interposer structures of various embodiments. For example, four separate embodiments of interposer structures 500 can be formed. In step S0, an initial local silicon interposer structure (e.g., as shown in the diagram) is provided. Figure 1B(as shown in LSI500). This process begins with a cladding layer comprising any number of oxide, metal substrates, or combination layers, which may be deposited over the top via 90 and redistribution layer 80 of the interposer 500, including the deep trench capacitor 70 and via 60. This cladding layer (also referred to as a barrier layer) provides basic barrier and insulation. In the first intermediate embodiment structure shown in step S1, the blanket cladding structure 110 can be formed by conformally depositing the cladding layer over the top via 90 and redistribution layer 80 of the interposer 500. In step S2, the blanket cladding structure 120, which may be referred to as the self-aligned spacer cladding structure 120, can be formed around the top via 90 to ensure proper alignment and protection by first depositing the cladding layer over the top via 90 and redistribution layer 80 of the interposer 500, and then performing a directional anisotropic etching process that leaves spacer material only on the sidewalls of the top via 90. Instead of step S2, a blanket covering structure 130 can be formed in step S3, or an additional blanket covering structure 140 can be formed in step S4. Both steps S3 and S4 can be performed on the blanket covering structure 110 of the first embodiment in step S1. Both steps S3 and S4 may involve applying photoresist patterning to define areas for subsequent etching processes, thereby forming individual tapered foot covering structures 130 and L-shaped foot covering structures 140. To form the tapered foot covering structure 130, in step S3, wet etching can be used to etch away the exposed area defined by the photoresist, thereby forming an undercut below the photoresist. This undercut will form a tapered foot shape at the foot of the covering structure, forming the tapered foot covering structure 130. Instead of the tapered foot covering structure 130 formed by step S3, the L-shaped foot covering structure 140 can be formed in step S4, which involves anisotropic reactive ion etching (RIE) or dry etching for a directional process. These orientation processes vertically etch the exposed areas to form an "L" shape at the foot of the overlay structure, creating an L-shaped foot overlay structure 140, and providing greater precision and control.

[0114] Figure 3The subsequent process steps S1A, S2A, S3A, and S4A following steps S1, S2, S3, and S4 are described. Steps S1A, S2A, S3A, and S4A may each form a blanket overlay structure 111, a self-aligned spacer overlay structure 121, a tapered lead overlay structure 131, or an L-shaped lead overlay structure 141, representing various embodiment structures. Before the subsequent process steps, a protective tape or polishing tape 5 may be attached to protect the top via 90 during subsequent processing steps, particularly during back-side polishing and processing of the die or wafer. These subsequent process steps may involve additional processes on the back side of the through-silicon via (TSV), including, if necessary, further oxide deposition, patterning, and etching to complete the TSV formation. The covering structure (e.g., covering structures 111, 121, 131, 141) covers the top guide hole 90 to ensure that the top guide hole 90 is well protected from any chemical reaction generated by the abrasive belt 5, thereby enhancing the long-term reliability of the device.

[0115] In step S1A, the intermediate blanket covering structure 110 in the first embodiment is further processed. The blanket covering structure 111 can be formed by depositing dielectric 6 around the top via 90 in the intermediate blanket covering structure 110 and planarizing the flowable or spin-coated dielectric 6. The flowable or spin-coated dielectric 6 can be deposited on... Figure 2 In step S1, the intermediate blanket coating layer covers the structure 110. Chemical mechanical polishing (CMP) can be performed on the dielectric 6 and part of the coating layer until the top surface of the top via 90 is exposed. The conformal coating layer may remain only on the sidewalls of the top via 90 and the surface of the redistribution layer 80, together with the flowable oxide or spin-coated dielectric 6, to ensure proper alignment and protection of the device.

[0116] In alternative step S2A, further processing can be performed. Figure 2 The self-aligned spacer coating structure 120 in step S2. The coating structure 121 can be formed by planarizing the portion of the flowable or spin-coated dielectric 6 above the top via 90 and the coating layer above the top of the via 90. Figure 2 In step S2, a flowable or spin-coated dielectric 6 may be deposited over the self-aligned spacer cover structure 120. Chemical mechanical polishing (CMP) may be performed over a portion of the dielectric 6 and cover layer until the top surface of the top via 90 is exposed. In the self-aligned spacer cover structure 121, the conformal cover layer remains only on the sidewalls of the top via 90, which, combined with the flowable oxide or spin-coated dielectric 6, ensures proper alignment and protection of the device.

[0117] In step S3A, further processing can be performed. Figure 2The tapered foot covering structure 130 in step S3. The tapered foot covering structure 131 can be formed around the top via 90 by planarizing a portion of the flowable or spin-coated dielectric 6 above the top via 90 and a portion of the conformal covering layer. The flowable or spin-coated dielectric 6 can be deposited on... Figure 2 Above the tapered foot overlay structure 130 in step S3, chemical mechanical polishing (CMP) can be performed to planarize the top of the dielectric 6 and the top surface of the overlay layer exposed to the top via 90. The resulting structure is a tapered foot overlay structure 131, wherein the conformal overlay layer remains only on the sidewalls of the top via 90, and may include flowable oxide or spin-coated dielectric 6 formed between the vias 90 to ensure proper alignment and protection of the device.

[0118] In step S4A, further processing is performed. Figure 2 In step S4, the L-shaped lead-covering structure 140 is formed. An L-shaped lead-covering structure 141 is formed around the top via 90 by planarizing a flowable or spin-coated dielectric 6 above the top via 90. The flowable or spin-coated dielectric 6 can be deposited on... Figure 2 Above the L-shaped foot cover structure 140 in step S4. Chemical mechanical polishing (CMP) can be performed on the top surface of the dielectric 6 and the cover layer until the top surface of the top via 90 is exposed. The resulting structure is an L-shaped foot cover structure 141, wherein the cover layer remains only on the sidewalls of the top via 90 and may include flowable oxide or rotating dielectric 6 formed between the vias 90 to ensure proper alignment and protection of the device.

[0119] Figure 4 The following are the subsequent process steps S1B, S2B, S3B, and S4B following steps S1A, S2A, S3A, and S4A, respectively. Steps S1B, S2B, S3B, and S4B may each form a blanket-covered structure 112, a self-aligned spacer-covered structure 122, a tapered-feet-covered structure 132, or an L-shaped-feet-covered structure 142, representing various embodiment structures. These subsequent processes may include partial etchback of a flowable or spin-coated dielectric 6 by wet etching or isotropic etching to ensure proper exposure and cleanliness of the top via 90.

[0120] In step S1B, further processing is performed. Figure 3 In step S1A, the blanket coating structure 111 is used to form the blanket coating structure 112. By further planarizing the flowable or spin-coated dielectric 6 and partially etching back the flowable or spin-coated dielectric 6, the blanket coating structure 112 can be formed around the top via 90, thereby exposing the top via 90. The conformal coating layer remains only on the sidewalls of the top via 90 and the surface of the redistribution layer 80, which, together with the flowable oxide or spin-coated dielectric 6 recessed by the etch-back process, ensures proper alignment and protection of the device.

[0121] In step S2B, further processing is performed. Figure 3 In step S2A, the self-aligned spacer cover structure 121 is used to form the self-aligned spacer cover structure 122. The self-aligned spacer cover structure 122 can be formed around the top via 90 by further planarizing the flowable or spin-coated dielectric 6 and partially etching back the flowable or spin-coated dielectric 6, thereby exposing the top via 90. The resulting structure can be the self-aligned spacer cover structure 122, wherein the cover layer remains only on the sidewalls of the top via 90, which, combined with the flowable oxide or spin-coated dielectric 6 recessed by the etch-back process, ensures proper alignment and protection of the device.

[0122] In step S3B, further processing is performed. Figure 3 In step S3A, the tapered foot covering structure 131 is formed to create a tapered foot covering structure 132. By further planarizing the flowable or spin-coated dielectric 6 and partially etching back the flowable or spin-coated dielectric 6, the tapered foot covering structure 132 is formed around the top via 90, thereby exposing the top via 90. The resulting structure can be a tapered foot covering structure 132, wherein the covering layer remains only on the sidewall of the top via 90, which, combined with the flowable oxide or spin-coated dielectric 6 recessed by the etch-back process, ensures proper alignment and protection of the device.

[0123] In step S4B, further processing is performed. Figure 3 In step S4A, the L-shaped lead-covering structure 141 is formed to create the L-shaped lead-covering structure 142. By further planarizing the flowable or spin-coated dielectric 6 and partially etching back the flowable or spin-coated dielectric 6, the L-shaped lead-covering structure 142 is formed around the top via 90, thereby exposing the top via 90. The resulting structure may be referred to as the "L"-shaped lead-covering structure 142, wherein the covering layer remains only on the sidewall of the top via 90, which, combined with the flowable oxide or spin-coated dielectric 6 recessed by the etch-back process, ensures proper alignment and protection of the device.

[0124] Figure 5 Explanation in Figure 4 Subsequent process steps S1C, S2C, S3C, and S4C following steps S1B, S2B, S3B, and S4B form a blanket overlay structure 113, a self-aligned spacer overlay structure 123, a tapered foot overlay structure 133, or an L-shaped foot overlay structure 143, representing various embodiment structures. These subsequent processes may include completely etching back the flowable or spin-coated dielectric 6 by wet etching or isotropic etching to ensure proper exposure and cleaning of the top via 90.

[0125] In step S1C, further processing is performed. Figure 4The blanket covering structure 112 is used to form the blanket covering structure 113. The blanket covering above the via 90 can be removed by chemical mechanical polishing (CMP) by planarizing the flowable or spin-coated dielectric 6, and the flowable or spin-coated dielectric 6 can be completely removed, forming the blanket covering structure 113 around the top via 90, thereby exposing the top via 90. In the blanket covering structure 113, the conformal blanket covering remains only on the sidewalls of the top via 90 and on the surface of the redistribution layer 80, ensuring proper alignment and protection of the device.

[0126] In step S2C, further processing is performed. Figure 4 A self-aligned spacer cover structure 122 is formed to create a self-aligned spacer cover structure 123. The cover layer above the via 90 can be removed by chemical mechanical polishing (CMP) by planarizing the flowable or spin-coated dielectric 6, and the flowable or spin-coated dielectric 6 can be completely removed, forming the self-aligned spacer cover structure 123 around the top via 90, thereby exposing the top via 90. In the self-aligned spacer cover structure 123, the cover layer remains only on the sidewall of the top via 90, ensuring proper alignment and protection of the device.

[0127] In step S3C, further processing is performed. Figure 4 A tapered foot cover structure 132 is formed to create a tapered foot cover structure 133. The cover layer can be removed from above the via 90 by planarizing the flowable or spin-coated dielectric 6 and completely removing the flowable or spin-coated dielectric 6, thus forming the tapered foot cover structure 133 around the top via 90, exposing the top via 90. In the tapered foot cover structure 133, the cover layer remains only on the sidewall of the top via 90, ensuring proper alignment and protection of the device.

[0128] In step S4C, further processing is performed. Figure 4 The L-shaped foot covering structure 142 is used to form the L-shaped foot covering structure 143. The covering structure 140 can be removed from above the via 90 by planarizing the flowable or spin-coated dielectric 6 and completely removing the flowable or spin-coated dielectric 6, forming the L-shaped foot covering structure 143 around the top via 90, thereby exposing the top via 90. In the L-shaped foot covering structure 143, the covering layer remains only on the sidewall of the top via 90, ensuring proper alignment and protection of the device.

[0129] Refer to step S1, Figure 6A A top view illustrating the deposition of a coating layer comprising multiple layers of blanket-like oxide and metal liner on the top guide hole 90 and redistribution layer 80 to form blanket-covered coating layer 1. Figure 6B Show along Figure 6AThe vertical cross-sectional view taken along line A-A' in the diagram details the formation of the blanket-like cladding structure 110 formed around the top guide hole 90. The cladding may include, but is not limited to, various metal substrates (such as CuO) on the guide hole surface. x The coating consists of Ta, Ti, TaN, TiN, TiC, TaC, TiCN, TaCN, Mo, or MoN, followed by an oxide layer. This coating may also include, but is not limited to, SiOCH. x SiO x SiN x And SiON, where "x" ranges from 0.1 to less than 1. The thickness of these layers may vary depending on the specific application, and the order in which they are deposited may also differ. For example, cladding structures 112, 122, 132, 142, 113, 123, 133, and 143 may place SiN as the final layer of the cladding layer in contact with the spin-coated dielectric 6. This SiN thickness may be thicker than other layers in the cladding layer, resulting in different etch rates. In some applications, certain layers may be omitted entirely. For example, blanket cladding structures 110, 111, 112, and 113 may not include a metal layer. The cladding layers have characteristics including, but not limited to, less than or equal to 10. -1 (Ω-m) -1 These layers offer high barrier conductivity and provide greater than 70% sidewall coverage. The deposition processes for these layers may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) to ensure precise thickness control and uniform coverage. Metal substrates and / or oxides can be used alone or in any combination to effectively encapsulate metal vias, prevent metal atom migration (such as during metal material and wire growth), and maintain the structural integrity of the vias.

[0130] Detailed diagrams of the abrasive belt 5 attachment are shown together with the interlayer blanket covering structure 110 in the first embodiment. Figure 7A and Figure 7B middle. Figure 7A This shows a top view of the interlayer blanket covering structure 110 in the first embodiment. Figure 7B Show along Figure 7A The image shows a vertical cross-section taken along line A-A'. The polishing tape 5, to which this process is attached, provides mechanical support and protection for the precision structure of the LSI die during subsequent polishing processes, covering the top via 90 and other exposed components. This polishing tape 5 ensures that the top via 90 and the interposer structure are preserved and remain intact, free from damage or contamination from external sources.

[0131] However, there may be reliability concerns regarding the chemical interaction between the top via 90 and the polishing tape 5. Specifically, there is a risk of chemical reactions, such as the migration of metal wires or metal atoms at the interface between the top via 90 and the polishing tape residue or material. Such migration may lead to the formation of intermetallic compounds or the diffusion of atoms, potentially affecting the electrical performance and long-term reliability of the via. To mitigate these issues, the use of a covering layer in the intermediate blanket covering structures 110, 120, 130, and 140 of various embodiments may be advantageous for the top via 90. This covering layer prevents direct contact between the top via 90 and the polishing tape residue or material, thereby reducing the risk of chemical reactions and metal atom migration. By maintaining the integrity of the top via 90, this covering layer ensures that the electrical characteristics remain stable and reliable throughout the device's lifespan. The use of a covering layer in the various embodiment structures is an advantageous step in addressing potential reliability issues during the polishing process.

[0132] During the polishing process, through-silicon vias (TSVs) can be subsequently formed from the back side of the LSI die, involving the establishment of vertical interconnects. The back-side TSV process ensures efficient electrical pathways and robust mechanical support throughout the package structure. This polishing tape 5 attachment step, as part of the TSV formation process, ensures that vias 90 and redistribution layer 80 are protected, while vias 60 are accurately exposed for TSV formation and precisely aligned for seamless integration into another die or interposer.

[0133] Detailed diagrams of the peeling and polishing belt 5 and the cleaning process are shown together with the intermediate blanket covering structure 110 in the first embodiment. Figure 8A and Figure 8B middle. Figure 8A A top view of the interlayer blanket covering structure 110 in the first embodiment is shown, while Figure 8B Show along Figure 8A The image shows a vertical cross-section taken along line A-A'. The first example of the intermediate blanket covering structure 110 can be retained and remain intact during the attachment, removal, and cleaning of the abrasive belt 5. The belt removal process can begin with controlled heating to soften the adhesive of the applied protective belt or abrasive belt 5. Removal and solvent cleaning steps can then be performed. Solvents such as isopropyl alcohol (IPA) or acetone can be used to dissolve and remove the adhesive without damaging the underlying silicon, copper, or other metallic features. At any step, deionized (DI) water can be used for rinsing to remove any residual solvent, thus preventing ionic contamination. In some cases, a plasma cleaning step can be utilized. For example, oxygen or nitrogen plasma can effectively remove any residual organic contaminants at the microscopic level, ensuring an initial surface.

[0134] However, in rare cases, after the cleaning step, residue or material from the abrasive tape 5 may remain in the top via 90 and / or react with it. The use of a covering layer in the various embodiments of the overlay structure ensures that the integrity of the top via 90 is not compromised by preventing direct contact with tape residue, and that the electrical characteristics remain stable and reliable throughout the device's lifespan. The use of a covering layer in the various embodiments of the blanket overlay structure is an advantageous step in addressing potential reliability issues during the fabrication of complex semiconductor packages.

[0135] Figure 9A and Figure 9B This demonstrates the application of a flowable oxide deposition or spin-coating dielectric process to the interposer layer 500. Figure 9A A top view of the interlayer blanket covering structure 110 in the first embodiment is shown.

[0136] Figure 9B A cross-sectional view is shown taken along line A-A' of the interlayer blanket covering structure 110 in the first embodiment. Figure 8A and 8B Following the stripping and cleaning process shown, a flowable oxide deposition or spin-coating dielectric 6 can be applied to cover the surface of the interposer 500. For example, this process can begin with the preparation of a flowable oxide solution, which typically contains siloxane materials, such as tetraethyl orthosilicate (TEOS), SiOCH, or organosilicon dissolved in a suitable solvent. The flowable oxide solution can be applied to the center of the grain. The spin coater can be set to high-speed rotation, typically, but not limited to, between 1000 and 5000 RPM, depending on the desired thickness and uniformity of the oxide layer. The centrifugal force generated by the rotation evenly distributes the flowable oxide solution across the entire grain surface, filling any gaps and ensuring a uniform coating. During the spin process, the solvent in the flowable oxide solution begins to evaporate, leaving a uniform oxide film. This film serves as a planarization layer, filling the terrain and forming a smooth surface. The typical thickness of the spin-coated oxide layer ranges from a few nanometers to hundreds of micrometers. The coated interposer 500 is then subjected to a curing process to harden the oxide layer. This curing step typically involves heating the grains to a temperature between 150°C and 400°C for several minutes to several hours. Heat treatment helps to further densify the oxide layer and improve its mechanical properties.

[0137] Figure 10A and Figure 10B The blanket covering structure 111 is illustrated and detailed diagrams of the formation and exposure of the blanket covering structure 111 are depicted. The blanket covering structure 111 may include a dielectric 6 to ensure the exposure of the top via 90. Figure 10A A top view of the blanket-covered structure 111 is shown after the top guide hole 90 has been exposed via a chemical mechanical polishing (CMP) step S1A. Figure 10BShow along Figure 10A The image shows a vertical cross-section taken along line A-A'. After the flowable oxide deposition or spin-coating of dielectric 6, chemical mechanical planarization (CMP), which stops at the top via 90 in step S1A, is applied to remove a portion of the dielectric 6 and the overlay layer above the top surface of the via 90. CMP step S1A removes excess dielectric 6 and planarizes the surface. The CMP slurry may contain abrasives, such as silica or alumina, suspended in a chemical reaction solution. The reaction solution may include oxidants (e.g., hydrogen peroxide) and complexing agents to facilitate the removal of dielectric 6 and to planarize the surface. During CMP step S1A, the wafer can be pressed onto a rotating polishing pad while the slurry is being prepared. This action mechanically removes the dielectric 6, a portion of the overlay layer, and any other residue from the surface of the top via 90. The process can be carefully monitored to ensure it stops precisely at the top via 90, exposing the top via 90 while maintaining a smooth and uniform surface. Following the initial CMP step, a touch-up CMP may be performed to ensure complete exposure of the top via 90 and remove any remaining dielectric material 6, or further processing may be performed to remove any metallic backing from the overlay material blanket on the top via 90. Figure 6B As shown, the blanket overlay structure 111 may not include a metal substrate in the overlay. Alternatively, the dielectric 6 and the blanket overlay material on the top surface of the top via 90 can be removed by blanket anisotropic and / or isotropic dry etching, alone or in any combination. The process produces a well-defined and planarized blanket overlay structure 111, in which the top via 90 is exposed and ready for further integration. For example, copper-to-copper (Cu-to-Cu) interconnects can be integrated to facilitate complex packaging technologies such as high-bandwidth memory (HBM) packages. This approach can also be applied to other intermediate overlay structures in other embodiments, such as 120, 130, and 140, forming intermediate overlay structures 121, 131, and 141 in the embodiments, respectively, ensuring uniformity and consistency of the interposer 500 across different regions.

[0138] Figure 11A and Figure 11BThe blanket coating structure 112 is illustrated and detailed diagrams of its formation and exposure are depicted. The blanket coating structure 112 may include recessed dielectric 6, ensuring exposure of the top via 90. An oxide etch-back step S1B is performed after the chemical mechanical polishing (CMP) in step S1A. The etch-back step S1B involves selectively removing the spin-coated dielectric 6 to form the blanket coating structure 112. The etch-back can be achieved using a wet etchant that selectively attacks the dielectric 6 but not the top via 90. The etchant used may be, but is not limited to, buffered oxide etchant (BOE) or similar chemical solutions, such as diluted HF (DHF). The etch-back step S1B ensures complete exposure of the top via 90, thereby creating a clean and well-defined interface for further processing of the dielectric 6 and further recessing of the dielectric 6. The coating structure 112 is achieved through partial etch-back. The difference in etching rates between the blanket coating and the dielectric 6 allows the dielectric 6 to be etched faster than the blanket coating. The difference in etch rate between the flowable dielectric 6 and the blanket-coated layer is attributed to variations in their processing conditions, material properties, and chemical reactivity. The blanket-coated layer in the blanket-coated structure 112 can be processed at higher temperatures ranging from 200°C to 400°C, exhibiting a denser and more robust structure than the spin-coated dielectric 6. Increased density leads to a slower etch rate when exposed to chemical etchants such as buffered oxide etchants (BOE). Conversely, the flowable oxide processed at lower temperatures from room temperature to 200°C retains lower density and more porosity, resulting in a higher etch rate under the same etch conditions. The material properties and varying reactivity to etchants ensure that the blanket layer provides greater protection and stability, while the dielectric 6 is easier to pattern and remove during fabrication. Due to the differences in material properties and processing conditions, the etch rate of the dielectric 6 can be 2 to 4 times higher than that of the blanket layer, but is not limited to this. Alternatively, a high contrast in etch rates can be achieved by placing the SiN layer as the outermost layer of the blanket layer. Under the same etchant, the SiN etching rate is more than twice as slow as that of spin-coated dielectric 6. The blanket overlay structure 112 may not include a metal substrate within the overlay. This selective etch-back step S1B exposes the top via 90 while retaining the blanket overlay on the sidewalls of the blanket overlay structure 112 during the etch-back step S1B, allowing various interconnect schemes to be used on the top surface of the top via. For example, in the use of microbumps and reflow packages with polymer underfill, the space regions created by the etch-back can be beneficial for high-bandwidth memory (HBM) packages. This method can also be applied to other intermediate overlay structures in other embodiments, such as 121, 131, and 141, forming intermediate overlay structures 122, 132, and 142 in the embodiments, respectively, ensuring uniformity and consistency of the interposer 500 across different regions.

[0139] Figure 12A and Figure 12BThis diagram illustrates the blanket overlay structure 113 and depicts a detailed view after the complete etch-back (i.e., removal) step S1C of the dielectric 6 above the surface of the redistribution layer 80. After step S1A, the etch-back step S1C can be applied to realize the blanket overlay structure 113, removing the dielectric 6 above the surface of the redistribution layer (RDL) 80 while exposing the top surface of the top via 90 and maintaining a conformal overlay on the sidewalls of the top via 90 above the redistribution layer 80 and the local silicon interposer 500, allowing various interconnect schemes to be used on the top surface of the top via. For example, in the use of microbumps and reflow packages with polymer underfill, the space region created by the etch-back may be beneficial for high-bandwidth memory (HBM) packages. The blanket overlay structure 113 may not include the metal substrate in the intermediate blanket overlay structure 110. This method can also be applied to intermediate covering structures in other embodiments, such as 121, 131 and 141, to form intermediate covering structures 122, 132 and 142 in the embodiments, respectively, to ensure the uniformity and consistency of the intermediate layer 500 across different regions.

[0140] Refer to step S2. Figure 13A and Figure 13B This illustration shows the formation of a self-aligned spacer intermediate cladding structure 120 after an isotropic directional reactive ion etching or dry etching process, and illustrates the configuration and arrangement of the self-aligned spacer intermediate cladding structure 120 around the top via 90. Figure 13B Presented along Figure 13A The cross-sectional view taken along line A-A' details the formation of the self-aligned spacer cladding structure 120 around the top guide hole 90. First, as detailed in step S1, this can be achieved by... Figure 6B A blanket of cladding material is conformally deposited over the top via 90 and redistribution layer 80 to form the intermediate blanket cladding structure 110 in the first embodiment. Following the conformal deposition of the blanket cladding material, an anisotropic dry etching process can be used to remove the cladding material from the horizontal surface while preserving and maintaining the vertical sidewalls, forming a self-aligned spaced intermediate cladding structure 120. The etching chemicals used in this process typically involve, but are not limited to, fluorocarbon gases such as CF4, CHF3, or C4F8, which selectively etch oxide materials and stop at the underlying metal substrate. Different etching chemicals can be used to etch the metal substrate, such as Ti, TiN, Ta, TaN, TaC, TiC, TaCN, TiCN, or MoN. Chlorine or bromine gases, such as Cl2, BCl3, or HBr, can be used due to their effectiveness in etching metallic materials, and the etching process should be carefully controlled to stop at the surface of the redistribution layer (RDL) 80 to prevent damage to the underlying layer. After the dry etching process, selective chemical wet cleaning can be performed to remove any residual etching byproducts and ensure surface cleanliness.

[0141] Detailed diagrams of the abrasive belt 5 attachment and the self-aligned interlayer covering structure 120 are shown together. Figure 14A and Figure 14B . Figure 14A A top view of the self-aligned interval intermediate covering structure 120 is shown, and Figure 14B Showing along Figure 14A The vertical cross-sectional view taken along line A-A' in Figure 7. The process of attaching the polishing tape 5 provides mechanical support and protection for the precision structure of the LSI grain during subsequent polishing processes, covering the top via 90 and other exposed components. For the sake of brevity, the method steps discussed above with respect to Figure 7 can be briefly described.

[0142] Detailed diagrams of the peeling and cleaning process of the abrasive belt 5 are shown together with the self-aligned interstitial covering structure 120. Figure 15A and Figure 15B . Figure 15A A top view of the self-aligned interval intermediate covering structure 120 is shown, and Figure 15B Showing along Figure 15A The vertical cross-sectional view taken along line A-A'. During the attachment, detachment, and cleaning of the abrasive belt 5, the self-aligned spacer intermediate covering structure 120 remains intact. For simplicity, it is related to the above regarding... Figure 8A and Figure 8B Similar methods and steps can be briefly described.

[0143] Figure 16A and Figure 16B This demonstrates the application of a flowable oxide deposition or spin-coating dielectric process to the interposer layer 500. Figure 16A A top view of dielectric 6 on interposer layer 500 is shown. Figure 16B A cross-sectional view is shown taken along line A-A' of the self-aligned intermediate covering structure 120. In such a way... Figure 15A and Figure 15B Following the stripping and cleaning process described above, a flowable oxide deposition or spin-coating dielectric 6 can be applied to cover the surface of the interposer 500. For the sake of brevity, method steps similar to those discussed above with respect to Figure 9 can be briefly described.

[0144] Figure 17A and Figure 17B The self-aligned spacer cladding structure 121 is illustrated, and detailed diagrams of the formation and exposure of the self-aligned spacer cladding structure 121 are depicted. The self-aligned spacer cladding structure 121 may include a dielectric 6 to ensure that the top via 90 is exposed. Figure 17A A top view showing the structure after the top guide hole 90 has been exposed via chemical mechanical polishing (CMP) step S2A, and Figure 17B It shows along Figure 17AThe image shows a vertical cross-section taken along line A-A'. After the flowable oxide deposition or spin-coating of dielectric 6, a chemical mechanical planarization (CMP) step S2A, stopped at the top via 90, is applied to remove portions of dielectric 6 and the overlay. CMP step S2A is used to remove excess portions of dielectric 6 and planarize the surface of dielectric 6. For brevity, method steps similar to those discussed above with respect to Figure 10 can be briefly described.

[0145] Figure 18A and Figure 18B The self-aligned spacer inter-cladding structure 122 is illustrated, and a detailed diagram of the formation and exposure of the self-aligned spacer inter-cladding structure 122 is depicted, which may include recessed dielectric 6 to ensure the exposure of the top via 90. Following the chemical mechanical polishing (CMP) step S2A, an oxide etch-back step S2B is performed. The etch-back step S2B involves selectively removing portions of the spin-coated dielectric 6 to expose the self-aligned spacer inter-cladding structure 122, including the recessed dielectric 6. This can be achieved using a wet etch chemical that selectively attacks the dielectric 6 but not the top via 90. For brevity, method steps similar to those discussed above with respect to Figure 11 can be briefly described.

[0146] Figure 19A and Figure 19B The self-aligned spacer cover structure 123 is explained, and a detailed view is depicted after step S2C, which removes the dielectric 6 on the surface of the redistribution layer 80. After step S2A, the etch-back step S2C can be applied to realize the self-aligned spacer cover structure 123, completely removing the dielectric 6 on the surface of the redistribution layer (RDL) 80 while exposing the top surface of the top via 90. The self-aligned spacer cover structure 123 covers the sidewalls of the top via 90 without damaging the redistribution layer 80.

[0147] In another embodiment, after step S1, Figure 20A and Figure 20B This describes the intermediate stages of forming the tapered foot intermediate covering structure 130 and the L-shaped foot intermediate covering structure 140. Steps S3 and S4 can be performed using a photoresist 2 patterning process on the intermediate blanket covering layer 1 of the first embodiment. Figure 20A A top view showing the aperture distribution is provided, in which the photoresist 2 is patterned. Figure 20B Depicting along Figure 20A The cross-sectional view taken along line A-A' illustrates the structure after the photoresist is patterned to cover a specific area. Figure 20A and Figure 20BIn this process, a layer of photoresist 2 can be coated over the entire surface and then exposed to a light source through a mask to transfer the desired pattern. This step may include, but is not limited to, using positive or negative photoresist depending on the specific application requirements. The patterned photoresist is used as a mask for subsequent etching processes, protecting the underlying layers during material removal in the exposed areas. In one embodiment, the photoresist can be developed to form openings corresponding to vias, thereby allowing precise etching of the underlying oxide and metal layers, such as... Figure 2 As shown. The patterned photoresist 2 ensures that only the exposed areas are etched away, while the protected areas remain intact. This photoresist patterning is a common step in the process flow, branching off to subsequent steps S3 and S4.

[0148] Refer to step S3. Figure 21A and Figure 21B The patterning of photoresist 2 and wet etching steps S3 are explained, detailing the formation of the tapered foot intermediate covering structure around the top guide hole 90. Figure 21A A top view is provided showing the removal of the coating layer on the surface of the redistribution layer 80 after the photoresist patterning step, while Figure 21B Depicting along Figure 21A The cross-sectional view taken along line A-A' illustrates the structure after the wet etching process. After photoresist patterning, a wet etching step S3 is used to etch the blanket material covering layer of the intermediate blanket covering structure 110 in the first embodiment. Wet etching chemicals may include, but are not limited to, diluted hydrofluoric acid (DHF) or buffered oxide etchant (BOE) for oxide materials and selective etchants for metal substrates, such as ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), or hydrochloric acid (HCl). This wet chemical etching process creates the undercut profile 4 of the covering layer 1 beneath the patterned photoresist, thereby creating a covering structure around the top via 90, as shown... Figure 21B As shown. The wet etching process can be carefully controlled to ensure that the material is removed precisely without damaging the underlying top via 90 or redistribution layer (RDL) 80, thereby producing the desired tapered foot intermediate overlay structure 130 after step S3.

[0149] Figure 22A Top view and layout are provided after wet etching step S3 and photoresist stripping. Figure 22B Depicting along Figure 22A The vertical cross-sectional view taken by line A-A' in the figure illustrates the desired tapered foot encapsulation structure 130 after the photoresist 2 is stripped. Figure 22B The structure highlights the elimination of the coating layer from the surface of the redistribution layer 80, ensuring that the surface is exposed and free of any residual material.

[0150] Detailed diagrams of the abrasive belt 5 attachment and the tapered foot intermediate covering structure 130 are shown together. Figure 23A and Figure 23B middle. Figure 23A A top view of the tapered foot intermediate covering structure 130 is shown, while Figure 23B Show along Figure 23A The image shows a vertical cross-section taken along line A-A'. The process with the polishing tape 5 attached provides mechanical support and protection for the precision structure of the LSI grain during subsequent polishing processes, covering the top via 90 and other exposed components. For brevity, the method steps similar to those discussed above with respect to Figure 7 can be briefly described.

[0151] Detailed diagrams of the peeling and cleaning process of the abrasive belt 5 are shown together with the tapered foot intermediate covering structure 130. Figure 24A and Figure 24B . Figure 24A A top view of the tapered foot intermediate covering structure 130 is shown, while Figure 24B Showing along Figure 24A The vertical cross-sectional view is taken along line A-A'. During the attachment, detachment, and cleaning of the abrasive belt 5, the intermediate covering structure 130 of these tapered feet remains intact. For the sake of brevity, the methodological steps similar to those discussed above with respect to Figure 8 can be briefly described.

[0152] Figure 25A and Figure 25B This demonstrates the application of a flowable oxide deposition or spin-coating dielectric process to the interposer layer 500. Figure 25A A top view of the cladding structure 130 in the middle of each tapered foot is shown. Figure 25B A cross-sectional view is shown, taken along line A-A' of the cladding structure 130 in the middle of each tapered foot. (As shown in...) Figure 24A and Figure 24B Following the stripping and cleaning process described above, a flowable oxide deposition or spin-coating dielectric 6 can be applied to cover the surface of the interposer 500. For the sake of brevity, method steps similar to those discussed above with respect to Figure 9 can be briefly described.

[0153] Figure 26A and Figure 26B The tapered lead intermediate cover structure 131 is illustrated, and a detailed diagram of the formation and exposure of the tapered lead intermediate cover structure 131 is depicted. The tapered lead intermediate cover structure 131 may include a dielectric 6 to ensure that the top via 90 is exposed. Figure 26A A top view showing the structure after the top guide hole 90 has been exposed via chemical mechanical polishing (CMP) step S3A, and Figure 26B It shows along Figure 26AThe image shows a vertical cross-section taken along line A-A'. After the flowable oxide deposition or spin-coating of dielectric 6, a chemical mechanical planarization (CMP) step S3A, stopped at the top via 90, is applied to remove dielectric 6 and the overlay. CMP step S3A is used to remove excess portions of dielectric 6 and planarize the surface of dielectric 6. For brevity, method steps similar to those discussed above with respect to Figure 10 can be briefly described.

[0154] Figure 27A and Figure 27B The tapered lead intermediate covering structure 132 is illustrated, and a detailed diagram is depicted showing the formation and exposure of the tapered lead intermediate covering structure 132 in conjunction with the recessed dielectric 6, ensuring the exposure of the top via 90. Following the chemical mechanical polishing (CMP) step S3A, an oxide etching-back step S3B is performed. The etching-back step S3B involves selectively removing the spin-coated dielectric 6 to expose the tapered lead intermediate covering structure 132, which may include the recessed dielectric 6. This can be achieved using a wet etching chemical that selectively attacks the dielectric 6 but not the top via 90. For brevity, method steps similar to those discussed above with respect to Figure 11 can be briefly described.

[0155] Figure 28A and Figure 28B The tapered lead overlay structure 133 is described, and a detailed view is depicted after the complete removal of the dielectric 6 on the surface of the redistribution layer 80 in step S3C. After step S3A, the tapered lead overlay structure 133 can be implemented by applying a complete etch-back step S3C to remove the dielectric 6 on the surface of the redistribution layer (RDL) 80, while exposing the top surface of the top via 90, covering the sidewalls of the top via 90 with the overlay layer 1 without damaging the redistribution layer 80.

[0156] In the fourth embodiment of the covering structure, such as Figure 20A and Figure 20B As shown, the patterning of photoresist 2 is an intermediate stage in forming the L-shaped foot intermediate covering structure 140. Referring to step S4, Figure 29A and Figure 29B The photoresist patterning combined with the dry etching step S4 is depicted, illustrating the precision required to achieve clear features. Figure 29A A top view of the patterned photoresist 2 is provided, while Figure 29B Provided along Figure 29AThe vertical cross-sectional view taken along line A-A' illustrates the result of the dry etching process. The etching chemicals used in this process can include, but are not limited to, fluorocarbon gases such as CF4, CHF3, or C4F8, which selectively etch oxide materials and stop on the underlying metal substrate. Different etching chemicals can be used to etch the metal substrate, such as Ti, TiN, Ta, TaN, TaC, TiC, TaCN, TiCN, or MoN. Chlorine or bromine gases, such as Cl2, BCl3, or HBr, are often used due to their effectiveness in etching metal materials, and the etching process is carefully controlled to stop on the surface of the redistribution layer 80 to prevent damage to the underlying layer. In this embodiment, dry etching is used to precisely cut through the oxide and metal substrates, ensuring a clean vertical cut profile 3 of the L-shaped foot intermediate overlay structure 140. The use of anisotropic etching step S4 allows for highly directional material removal, resulting in square ends on the L-shaped foot intermediate overlay structure 140. This process ensures that the vertical sidewalls remain intact and that the etching does not undercut the photoresist mask. By carefully controlling the etching chemicals and parameters, such as gas composition and plasma power, the etching rate can be finely tuned to achieve the desired profile without damaging the top via 90 and the redistribution layer 80 in the local silicon interposer 500. After the dry etching process, selective chemical wet cleaning can be performed to remove any residual etching byproducts and ensure surface cleanliness.

[0157] Figure 30A and Figure 30B The process of stripping patterned photoresist is described. Clean removal of photoresist 2 may involve, but is not limited to, using wet chemical stripping agents or plasma ashing to completely remove residual photoresist 2. Figure 30A A top view is provided showing the top surface of the L-shaped foot intermediate overlay structure 140 and the redistribution layer (RDL) 80 after the photoresist has been stripped. Figure 30B Provided along Figure 30A The vertical cross-sectional view taken by line A-A' in the figure details the result after the photoresist is stripped away and the L-shaped foot intermediate covering structure 140 around the top guide hole 90 is exposed.

[0158] Detailed diagrams of the abrasive belt 5 attachment and the L-shaped foot intermediate covering structure 140 are shown together. Figure 31A and Figure 31B middle. Figure 31A A top view of the L-shaped foot intermediate covering structure 140 is shown, while Figure 31B Show along Figure 31A The image shows a vertical cross-section taken along line A-A'. The process with the polishing tape 5 attached provides mechanical support and protection for the precision structure of the LSI grain during subsequent polishing processes, covering the top via 90 and other exposed components. For brevity, the method steps similar to those discussed above with respect to Figure 7 can be briefly described.

[0159] Detailed diagrams of the peeling and cleaning process of the abrasive belt 5 are shown together with the L-shaped foot intermediate covering structure 140. Figure 32A and Figure 32B . Figure 32A A top view of the L-shaped foot intermediate covering structure 140 is shown, while Figure 32B Showing along Figure 32A The vertical cross-sectional view is taken along line A-A'. During the attachment, detachment, and cleaning of the abrasive belt 5, the L-shaped foot intermediate covering structure 140 remains intact. For the sake of brevity, the method steps similar to those discussed above with respect to Figure 8 can be briefly described.

[0160] Figure 33A and Figure 33B This demonstrates the application of a flowable oxide deposition or spin-coating dielectric process to the interposer layer 500. Figure 33A A top view of the overlay structure 140 in the middle of each L-shaped foot is shown. Figure 33B A cross-sectional view is shown taken along line A-A' of the overlying structure 140 in the middle of each L-shaped foot. Figure 32A and Figure 32B Following the stripping and cleaning process described above, a flowable oxide deposition or spin-coating dielectric 6 can be applied to cover the surface of the interposer 500. For the sake of brevity, method steps similar to those discussed above with respect to Figure 9 can be briefly described.

[0161] Figure 34A and Figure 34B The L-shaped lead intermediate cover structure 141 is explained, and a detailed diagram is drawn showing the formation and exposure of the L-shaped lead intermediate cover structure 141 in combination with the dielectric 6, ensuring that the top via 90 is exposed. Figure 34A A top view showing the structure after the top guide hole 90 has been exposed via chemical mechanical polishing (CMP) step S4A, and Figure 34B It shows along Figure 34A The image shows a vertical cross-section taken along line A-A'. After the flowable oxide deposition or spin-coating of dielectric 6, a chemical mechanical planarization (CMP) step S4A, stopped at the top via 90, is applied to remove dielectric 6 and the overlay. CMP step S4A is used to remove excess dielectric 6 and planarize the surface of dielectric 6. For brevity, method steps similar to those discussed above with respect to Figure 10 can be briefly described.

[0162] Figure 35A and Figure 35BThe L-shaped lead intermediate covering structure 142 is illustrated, and a detailed diagram is depicted showing the formation and exposure of the L-shaped lead intermediate covering structure 142 combined with the recessed dielectric 6, ensuring the exposure of the top via 90. Following the chemical mechanical polishing (CMP) step S4A, an oxide etching-back step S4B is performed. The etching-back step S4B involves selectively removing the spin-coated dielectric 6 to expose the L-shaped lead intermediate covering structure 142, combined with the recessed dielectric 6. This can be achieved using a wet etching chemical that selectively attacks the dielectric 6 but not the top via 90. For brevity, method steps similar to those discussed above with respect to Figure 11 can be briefly described.

[0163] Figure 36A and Figure 36B The L-shaped lead overlay structure 143 is explained, and a detailed diagram is depicted after step S4C, in which the dielectric 6 on the surface of the redistribution layer 80 is completely removed. After step S4A, a complete etch-back step S4C can be applied to realize the L-shaped lead overlay structure 143, completely removing the dielectric 6 on the surface of the redistribution layer (RDL) 80 while exposing the top surface of the top via 90, covering the sidewalls of the top via 90 with the overlay layer, without damaging the redistribution layer 80.

[0164] Figure 37 The common dimensions of the coating structure are described. The diameter "a" of the top vias can be, but is not limited to, in the range of 1 μm to 100 μm. The thickness "b" of the coating layer can be, but is not limited to, greater than 100 nm. The distance between the top vias can be, but is not limited to, in the range of 1 μm to 500 μm. The height "c" of the top vias can be, but is not limited to, in the range of 1 μm to 100 μm.

[0165] Figure 38 This is a process flow diagram illustrating the steps of forming a local silicon interposer layer having a top via including a barrier structure that protects and mitigates damage to the top via during a polishing process. Refer to the description of method 3800. Figure 2 (Step S2) Figure 3 (Step S2A) Figures 13A-17B and Figure 38 . Reference Figure 1A , Figure 1B , Figure 2 (Step S0) and Figure 38 In step 3802, a local silicon interposer layer 500 may be formed. (Refer to the above.) Figure 1A , Figure 1B , Figure 2 As discussed in (step S0), the interposer 500 may be formed as any and / or all of the TSV 60 formed in the silicon substrate 40, deep trench capacitor 70, redistribution layer 80 and top via 90.

[0166] Reference Figure 2(Step S1) Figure 6A , Figure 6B and Figure 38 In step 3804, a coating layer may be deposited over the top via 90 and the redistribution layer 80 to form the intermediate blanket coating structure 110 in the first embodiment. The blanket coating material may include any combination of various metal substrates, such as CuO on the surface of the top via. x The coating material consists of Ta, Ti, TaN, TiN, TiC, TaC, TiCN, TaCN, Mo, or MoN, followed by an oxide layer. This coating material blanket may include, but is not limited to, SiOCH2. x SiO x SiN x And SiON, where "x" ranges from 0.1 to less than 1. The thickness of these layers may vary depending on the specific application, and the order in which they are deposited may also differ.

[0167] Reference Figure 2 (Step S2) Figure 13A , Figure 13B and Figure 38 In step 3806, a dry etching process may be performed to etch the intermediate blanket covering structure 110 in the first embodiment to form a self-aligned spacer covering structure 120, which includes a top guide hole 90 having covering material remaining on the sidewalls of the top guide hole 90. In step 3808, a wet etching process may be performed to remove and a dry etching process may be performed to remove any residual etching byproducts and ensure surface cleanliness.

[0168] Reference Figure 14A , Figure 14B and Figure 38 In step 3810, the polishing belt 5 may be attached to the top guide hole and the self-aligned spacer covering structure 120. The polishing process can then be performed. In step 3812, the polishing belt 5 may be removed from the self-aligned spacer covering structure 120 after the polishing process.

[0169] Reference Figure 16A , Figure 16B and Figure 38 In step 3814, the flowable dielectric 6 can be deposited or spin-coated over the top via 90 and the self-aligned spacer overlay structure 120 and redistribution layer 80. (Refer to...) Figure 17A , Figure 17B and Figure 38 In step 3816, a CMP process can be performed to remove excess material from the top via 90, the covering material, and the flowable dielectric 6, such that the top via 90, the covering material, and the flowable dielectric 6 are coplanar. In subsequent processing steps, different amounts of the flowable dielectric 6 can be removed.

[0170] Figure 39This is a process flow diagram illustrating the steps of forming a local silicon interposer having a top via including a barrier structure that protects and mitigates damage to the top via during a polishing process. (Refer to...) Figure 2 (Steps S3 and S4) Figure 3 (Step S3A, Step S4A) Figures 20A-36B and Figure 39 This explains method 3900. For the sake of brevity, it is related to the above regarding... Figure 38 Similar methods and steps can be briefly described. (See reference...) Figure 1A , Figure 1B , Figure 2 (Step S0) and Figure 38 In step 3802, a local silicon interposer layer 500 may be formed. (Refer to...) Figure 2 (Step S1) Figure 6A , Figure 6B and Figure 38 In step 3804, a blanket covering material may be deposited over the top guide hole 90 and the redistribution layer 80 to form the intermediate blanket covering structure 110 in the first embodiment.

[0171] Reference Figure 2 (Steps S3 and S4) Figure 20A , Figure 20B and Figure 39 In step 3902, photoresist 2 may be coated over the top via 90 having the intermediate cover layer overlay structure 110 in the first embodiment. In step 3904, a pattern may be transferred to photoresist 2 using a photolithography process.

[0172] In some embodiments, refer to Figures 20A-22B In step 3906, a wet etching process can be performed to remove a portion of the coating material. The wet etching chemical may include, but is not limited to, any combination of diluted hydrofluoric acid (DHF) or buffered oxide etchant (BOE) for oxide materials and selective etchants for metal substrates, such as ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), or hydrochloric acid (HCl). This wet chemical etching process creates an undercut profile 4 of the coating layer beneath the patterned photoresist 2, thereby creating a coating structure around the top via 90, such as... Figure 21B As shown. The wet etching process can be carefully controlled to ensure that the material is removed precisely without damaging the underlying top via 90 or redistribution layer (RDL) 80, thereby producing the desired tapered foot intermediate overlay structure 130 after step S3.

[0173] In other embodiments, refer to Figures 29A-30BIn step 3906, a dry etching process can be performed to remove a portion of the coating material. The etching chemicals used in this dry etching process can include, but are not limited to, fluorocarbon gases such as CF4, CHF3, or C4F8, which selectively etch the oxide material and stop at the underlying metal substrate. Different etching chemicals can be used to etch the metal substrate, such as Ti, TiN, Ta, TaN, TaC, TiC, TaCN, TiCN, or MoN. Chlorine or bromine gases, such as Cl2, BCl3, or HBr, are often used due to their effectiveness in etching metal materials, and the etching process is carefully controlled to stop at the surface of the redistribution layer 80 to prevent damage to the underlying layer. In this embodiment, dry etching is used to precisely cut through both the oxide and metal substrates, ensuring a clean vertical cut profile 3 of the L-shaped foot intermediate coating structure 140. The use of anisotropic etching step S4 allows for highly directional material removal, resulting in square ends on the L-shaped foot intermediate coating structure 140. This process ensures that the vertical sidewalls remain intact and that the etching does not undercut the photoresist mask. By carefully controlling the etching chemicals and parameters, such as gas composition and plasma power, the etching rate can be finely tuned to achieve the desired profile without damaging the lower via 90 and redistribution layer 80 in the local silicon interposer 500. After the dry etching process, selective chemical wet cleaning can be performed to remove any residual etching byproducts and ensure surface cleanliness.

[0174] Once the tapered lead intermediate covering structure 130 or the L-shaped lead intermediate covering structure 140 is formed using a wet etching or dry etching process, steps 3810-3816 can be performed as described above.

[0175] Figure 40 This is a process flow diagram illustrating the steps of forming a local silicon interposer including a top via with an overlay structure (113, 123, 133, 143) as described in the embodiments, the overlay structure protecting and mitigating damage to the top via 90 during a polishing process. (Refer to...) Figure 2 (Step S1) Figure 3 (Step S1A) Figures 6A-10B and Figure 40 This explains method 4000. For the sake of brevity, it is related to the above regarding... Figure 38 Similar methods and steps can be briefly described. (See reference...) Figure 1A , Figure 1B , Figure 2 (Step S0) and Figure 38 In step 3802, a local silicon interposer layer 500 may be formed. (Refer to...) Figure 2 (Step S1) Figure 6A , Figure 6B and Figure 38In step 3804, a covering material blanket layer may be deposited over the top via 90 and the redistribution layer 80 to form the intermediate blanket covering structure 110 in the first embodiment. The conformal covering layer covers the surfaces of the top via 90 and the redistribution layer 80, resulting in the formation of the intermediate blanket covering structure 110 in the first embodiment.

[0176] Once the conformal covering layer is used to form the intermediate blanket covering structure 110 in the first embodiment, steps 3810-3816 can be performed as described above.

[0177] According to various embodiments of this invention, via encapsulation structures for local silicon interposer (LSI) dies benefit electrical performance and reliability in semiconductor packaging technology. Via barrier structures address reliability issues such as wire growth, metal loss, and residual reactions by ensuring the encapsulation structure, thereby enhancing the electrical performance, reliability, and long-term stability of semiconductor packaging devices. Adjustable methods for forming the encapsulation structure can meet diverse design requirements, making it suitable for various high-performance applications, including high-performance computing (HPC) and artificial intelligence (AI).

[0178] Referring to all the accompanying drawings and various embodiments of the present invention, a local silicon interposer 500 having a top via with an embodiment-covered structure (113, 123, 133, 143) can be provided. The local silicon interposer 500 may include a top via 90 formed over a redistribution layer (RDL) 80 and a conformal cover layer formed over the sidewalls of the top via 90, wherein the conformal cover layer provides a barrier between the sidewalls of the top via 90 and chemically reacted materials, residues, and contaminants, forming self-aligned spacer cover structures (121, 122, and 123), tapered foot cover structures (131, 132, and 133), and L-shaped foot cover structures (113, 123, 133, 143). Alternatively, the local silicon interposer 500 may include a via overlay structure comprising multiple layers of oxide, wherein the sidewalls of the top via 90 above the overlay material blanket encapsulation substrate 40 and all surfaces of the redistribution layer 80 (RDL) form the blanket overlay structure (111, 112, and 113). The top surface of the top via is exposed, thereby further enabling another continuation of the interconnect.

[0179] In one embodiment, the conformal coating layer may include a multilayer oxide, such as SiOCH or SiO. x SiON, SiN x or CuO xIn another embodiment, the conformal cladding layer may include a metallic liner, such as Ta, Ti, TaN, TiN, Mo, MoN, TaC, TiC, TaCN, or TiCN. In one embodiment, the conformal cladding structure includes a self-aligned spacer cladding structure 123. In one embodiment, the self-aligned spacer cladding structure 123 may be formed on the sidewall of the top via 90. In one embodiment, the conformal cladding structure may include a tapered foot cladding structure 130. In one embodiment, the tapered foot cladding structure 130 may be formed on the sidewall of the top via 90. In one embodiment, the conformal cladding structure may include an L-shaped foot cladding structure 140. In one embodiment, the L-shaped foot cladding structure 140 may be formed on the sidewall of the top via 90. In one embodiment, the conformal cladding structure is formed on the sidewall of the top via 90 and extends continuously over the redistribution layer (RDL) 80.

[0180] According to another aspect of this document, a method for forming a local silicon interposer 500 is provided, which includes depositing at least one of a conformal cladding material blanket layer and a metal substrate on the top surface of a top via 90 and a redistribution layer (RDL) 80 to form an intermediate blanket layer cladding structure (110), and etching the intermediate blanket layer cladding structure (110) above the redistribution layer (RDL) 80.

[0181] In one embodiment, a method for forming a local silicon interposer 500 may include etching an intermediate blanket overlay structure (110), wherein wet etching, isotropic etching, or anisotropic etching may be selected to remove the overlay material blanket in an uncovered area of ​​the photolithographic pattern, such that the overlay material blanket above the sidewalls of the top via 90 remains intact. In one embodiment, etching includes anisotropic etching, such that the overlay material blanket above the sidewalls of the top via 90 remains intact. In other embodiments, etching includes wet etching or isotropic etching in an uncovered area of ​​the photolithographic pattern, such that the overlay material blanket above the sidewalls of the top via 90 remains intact. In other embodiments, etching includes anisotropic oriented etching in an uncovered area of ​​the photolithographic pattern, such that the overlay material blanket above the sidewalls of the top via 90 remains intact. In other embodiments, depositing at least one of the conformal overlay material and the metal liner includes depositing a conformal overlay material blanket over the top surface of the top via 90 and the redistribution layer (RDL) 80, wherein the conformal overlay material blanket overlay material is in contact with the surfaces of the top via 90 and the redistribution layer (RDL) 80.

[0182] According to other embodiments of this document, a method for forming a via cladding structure is provided, which may include depositing at least one of a conformal oxide and a metal liner over the top surface of a top via and a redistribution layer (RDL) to form a cladding layer; depositing a flowable or spin-coated dielectric 6 over the cladding material blanket layer and the redistribution layer (RDL) 80; and removing the dielectric 6 and the cladding material blanket layer over the surface of the top via to expose the top surface of the top via 90.

[0183] In one embodiment, removing the dielectric 6 and the cladding layer above the top surface of the top via 90 includes removing the dielectric 6 by etch-back, wherein the cladding layer has a coverage of more than 70% of the sidewalls of the top via 90.

[0184] According to one embodiment of the present invention, a via covering structure is provided, comprising: a top via formed above a redistribution layer; and a conformal covering material blanket layer formed above the sidewall of the top via, which exposes the top surface of the top via such that other interconnects are formed on the top surface of the top via.

[0185] According to one embodiment of the present invention, the conformal covering material blanket layer comprises a multilayer oxide. According to one embodiment of the present invention, the via covering structure further comprises a metal liner. According to one embodiment of the present invention, the multilayer oxide comprises SiOCH and SiO. x SiON, SiN x and CuO x At least one of the following. According to one embodiment of the present invention, the metal liner includes at least one of Ta, Ti, TaN, TiN, Mo, MoN, TaC, TiC, TaCN, and TiCN. According to one embodiment of the present invention, the via covering structure is formed as a self-aligned spaced covering structure. According to one embodiment of the present invention, the self-aligned spaced covering structure is formed on the sidewall of the top via. According to one embodiment of the present invention, the via covering structure is formed as a tapered foot covering structure. According to one embodiment of the present invention, the tapered foot covering structure is formed on the sidewall of the top via. According to one embodiment of the present invention, the via covering structure is formed as an L-shaped foot covering structure. According to one embodiment of the present invention, the L-shaped foot covering structure is formed on the sidewall of the top via. According to one embodiment of the present invention, the via covering structure is formed as a blanket covering structure. According to one embodiment of the present invention, the blanket covering structure is formed on the sidewall of the top via and extends continuously above the redistribution layer (RDL).

[0186] According to one embodiment of this document, a method for forming a via covering structure is provided, comprising: depositing at least one of a conformal oxide and a metal liner over the top surface of a top via and a redistribution layer (RDL) to form a covering material blanket layer; and etching the covering material blanket layer over the redistribution layer (RDL).

[0187] According to one embodiment of this document, etching includes anisotropic etching, retaining a blanket of covering material over the sidewalls of the top via. According to one embodiment of this document, etching includes wet etching or isotropic etching in an uncovered area of ​​a photolithographic pattern, retaining a blanket of covering material over the sidewalls of the top via. According to one embodiment of this document, etching includes anisotropic directional etching in an uncovered area of ​​a photolithographic pattern, retaining a blanket of covering material over the sidewalls of the top via. According to one embodiment of this document, depositing at least one of a conformal oxide and a metal substrate includes depositing a conformal oxide over the top surface of the top via and the redistribution layer (RDL), wherein the conformal oxide is in contact with the top surface of the top via and the redistribution layer.

[0188] According to one embodiment of this document, a method for forming a via covering structure is provided, comprising: depositing at least one of a conformal oxide and a metal liner over the top surface of a top via and a redistribution layer (RDL) to form a covering material blanket layer; depositing a dielectric over the covering material blanket layer and the redistribution layer (RDL); and removing the dielectric and the covering material blanket layer over the top surface of the top via to expose the top surface of the top via.

[0189] According to one embodiment of this document, removing the dielectric and overlay material blanket above the top surface of the top via includes removing the dielectric by etch-back, wherein the overlay material blanket covers more than 70% of the sidewalls of the top via.

[0190] The components of several embodiments are outlined above to facilitate a better understanding of the embodiments of this invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this invention.

Claims

1. A guide hole covering structure, characterized in that, include: A top guide hole is formed above a redistribution layer; as well as A conformal covering material blanket is formed above the sidewall of the top guide hole, wherein a top surface of the top guide hole is exposed such that other interconnects are formed on the top surface of the top guide hole.

2. The guide hole covering structure as described in claim 1, characterized in that, It also includes a metal liner.

3. The guide hole covering structure as described in claim 1, characterized in that, The guide hole covering structure is formed as a self-aligned spaced covering structure.

4. The guide hole covering structure as described in claim 3, characterized in that, The self-aligned gap covering structure is formed on the sidewall of the top guide hole.

5. The guide hole covering structure as described in claim 1, characterized in that, The guide hole covering structure is formed as a tapered foot covering structure.

6. The guide hole covering structure as described in claim 5, characterized in that, The tapered foot covering structure is formed on the sidewall of a top guide hole.

7. The guide hole covering structure as described in claim 1, characterized in that, The guide hole covering structure is formed as an L-shaped foot covering structure.

8. The guide hole covering structure as described in claim 7, characterized in that, The L-shaped foot covering structure is formed on the sidewall of a top guide hole.

9. The guide hole covering structure as described in claim 1, characterized in that, The guide hole covering structure is formed as a blanket covering structure.

10. The guide hole covering structure as described in claim 9, characterized in that, The blanket covering structure is formed on the sidewall of the top guide hole and extends continuously above the redistribution layer.

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