Interposer, semiconductor device, and electronic apparatus

Abstract

The present disclosure relates to an intermediate connecting plate, a semiconductor device and an electronic device, the intermediate connecting plate comprising a substrate layer and a wiring layer formed on the substrate layer, the wiring layer comprising a plurality of signal lines, at least part of the signal lines having a base section and an adjustment section, the adjustment section having a cross-sectional dimension greater than that of the base section. By the above technical solution, i.e. the intermediate connecting plate of the present disclosure, the signal lines of the wiring layer comprise a base section and an adjustment section, wherein the cross-sectional dimension of the adjustment section is greater than that of the base section, and the adjustment section with a larger carrier surface dimension is used to improve the signal quality of the signal lines, especially those with a longer length. In areas where the signal lines are densely distributed, such as routing areas, the base section can be provided to meet the signal transmission requirements, and the adjustment section can be provided within the range of allowed space to improve the signal quality of the signal lines.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to an interposer, semiconductor device, and electronic device. Background Technology

[0002] An interposer is an intermediate layer structure primarily used to achieve high-density interconnects and heterogeneous integration. It can provide high-speed, low-latency signal transmission paths between devices such as memory and processors, and address the bottlenecks in interconnect density and performance of traditional packaging technologies.

[0003] In related technologies, metal signal lines are provided inside the intermediate connection board for interconnection. However, under normal circumstances, the width between the input and output ends of the signal line is constant. Therefore, as the length of the signal line increases, the signal transmission quality decreases, which in turn affects the overall performance. Utility Model Content

[0004] The purpose of this disclosure is to provide an interposer board, semiconductor device, and electronic device that can improve signal transmission quality, thereby at least partially solving the related technical problems.

[0005] To achieve the above objectives, according to a first aspect of this disclosure, an intermediary connection plate is provided, comprising: Substrate layer; and A wiring layer is formed on the substrate layer, the wiring layer including a plurality of signal lines, at least a portion of the signal lines having a base segment and an adjustment segment. The cross-sectional dimensions of the adjustment section are larger than those of the base section.

[0006] Optionally, the width of the adjustment segment is greater than the width of the base segment.

[0007] Optionally, the ratio of the width of the adjustment segment to the width of the base segment is K, where 1 <K<2。

[0008] Optionally, the number of adjustment segments for each of the signal lines may be set to one or more.

[0009] Optionally, the widths of the adjustment segments in the same signal line are the same; or At least two of the adjustment segments in the same signal line have different widths.

[0010] Optionally, the wiring layer includes a first signal line and a second signal line, wherein the length of the first signal line is greater than the length of the second signal line; The length of the adjustment segment of the first signal line is greater than the length of the adjustment segment of the second signal line.

[0011] Optionally, the signal lines extend along a first direction, and the signal lines are spaced apart along a second direction perpendicular to the first direction, wherein adjacent signal lines have different lengths along the second direction.

[0012] Optionally, the interfacing board includes multiple wiring layers spaced apart along the thickness direction of the substrate layer, and at least one of the wiring layers has a signal line having a base segment and an adjustment segment.

[0013] According to a second aspect of this disclosure, a semiconductor device is provided, including a memory, a processor, and the aforementioned interposer board. The memory and the processor are disposed on the intermediate connection board and electrically connected through the wiring layer.

[0014] According to a third aspect of this disclosure, an electronic device is provided, including the semiconductor device described above.

[0015] Through the above-described technical solution, namely the intermediate connection board of this disclosure, the signal lines of the wiring layer include a base segment and an adjustment segment. The cross-sectional size of the adjustment segment is larger than that of the base segment. Utilizing the larger cross-sectional size of the adjustment segment improves the signal quality, especially for longer signal lines. In areas with dense signal line distribution, such as routing areas, a base segment can be installed to meet signal transmission requirements, while an adjustment segment can be installed within permissible space to improve the signal quality of the signal lines.

[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the accompanying drawings...

[0018] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of an exemplary implementation of the wiring layer provided in this disclosure; Figure 3 This is a schematic diagram of yet another exemplary embodiment of the wiring layer provided in this disclosure; Figure 4 This is a schematic diagram of yet another exemplary embodiment of the wiring layer provided in this disclosure; Figure 5a This is the eye diagram before the signal line setting adjustment section provided in this disclosure; Figure 5b This is the eye diagram after the signal line settings adjustment section is provided in this publication.

[0019] Explanation of reference numerals in the attached figures 1000. Semiconductor devices; 100. Packaging module; 200. Substrate structure; 10. Intermediate connection board; 20. Memory; 30. Processor; 1. Substrate layer; 2. Wiring layer; 21. Signal line; 211. Base segment; 212. Adjustment segment; 21a. First signal line; 21b. Second signal line; 3. Microbump; 4. Solder ball. Detailed Implementation

[0020] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0021] In this disclosure, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the corresponding figures; "inner" and "outer" refer to the outline of the corresponding components themselves. The terms "first," "second," etc., used in this disclosure are for distinguishing one element from another and do not have sequential or importance. When the following description refers to the figures, unless otherwise indicated, the same numbers in different figures represent the same or similar elements.

[0022] The inventors discovered through research that the width of the metal signal line in the intermediate connection board is constant from the input end to the output end. As a result, the signal quality decreases as the length of the signal line increases. In addition, in the route area with congested wiring, the width of the signal line is not easy to adjust, which affects the signal quality.

[0023] To solve the aforementioned technical problems, in accordance with the first aspect of this disclosure, reference is made to... Figures 1 to 4 As shown, this disclosure provides an interfacing board 10, including a substrate layer 1 and a wiring layer 2, wherein the wiring layer 2 is formed on the substrate layer 1 and the wiring layer 2 includes a plurality of signal lines 21, at least some of the signal lines 21 having a base segment 211 and an adjustment segment 212, the cross-sectional dimension of the adjustment segment 212 being larger than the cross-sectional dimension of the base segment 211.

[0024] Through the above technical solution, namely the intermediate connection board 10 of this disclosure, the signal line 21 of the wiring layer 2 includes a base segment 211 and an adjustment segment 212, wherein the cross-sectional size of the adjustment segment 212 is larger than that of the base segment 211. By using the larger cross-sectional size of the adjustment segment 212, the signal quality of the signal line 21, especially the longer one, is improved. In areas where the distribution of signal lines 21 is relatively congested, such as routing areas, the base segment 211 can be set to meet the signal transmission requirements, and the adjustment segment 212 can be set within the allowable space to improve the signal quality of the signal line 21.

[0025] It is understandable that increasing the cross-sectional size of the signal line 21 at the adjustment section 212 can reduce resistance and increase the current distribution space to reduce current density, thereby reducing resistance loss and optimizing current distribution, reducing the probability of electromigration failure and improving reliability.

[0026] refer to Figure 5a and Figure 5b As shown, where, Figure 5a The eye diagram in the image is one where signal line 21 does not have an adjustment segment 212 and has a relatively small overall width. Figure 5b The eye diagram in the diagram is an eye diagram with an adjustment segment 212 set on signal line 21. The size of the "eye" opening in the diagram reflects the degree of distortion and the strength of inter-symbol interference. This disclosure uses a fixed "eye height" as a reference. The "eye width" of the right eye diagram is greater than the "eye width" of the left eye diagram. Therefore, the timing margin of the signal in the time domain is larger, which specifically reflects the stability of signal transmission and the ability to resist timing interference, and the improvement of signal quality.

[0027] In some embodiments, reference Figures 2 to 4 As shown, the width of the adjustment segment 212 is greater than the width of the base segment 211, so as to increase the cross-sectional size of the signal line 21. For example, the signal line 21 extends along a first direction, and multiple signal lines 21 are spaced apart along a second direction. In this case, the aforementioned width is the size of the signal line 21 along the second direction, where "X" in the figure represents the first direction and "Y" represents the second direction.

[0028] It is understood that the signal line 21 can be laid out by etching trenches and electroplating filling, thus the width of the signal line 21 (including the adjustment section 212 and the base section 211) is the width of the trench. In this way, by deepening the trench, the adjustment section 212 can also be formed to increase the cross-sectional area of ​​the signal line 21, in which case the depth direction of the trench is perpendicular to the plane formed by the first and second directions. Furthermore, the width of the trench and the depth of the trench can be increased simultaneously. This disclosure is not limited thereto.

[0029] It is understandable that when increasing the width of signal line 21 to form adjustment segment 212, the width needs to be reasonably set to balance adverse factors such as impedance abrupt changes. In some embodiments, refer to Figures 2 to 4As shown in the figure, the ratio of the width of the adjusting segment 212 to the width of the base segment 211 is adjusted to K, where 1<K<2. In this way, the width of the adjusting segment 212 can be constrained to reduce problems such as impedance mutation and signal reflection, manufacturing process issues, and uneven current density distribution caused by an excessively wide adjusting segment 212, ensuring that the width of the adjusting segment 212 is within a suitable range, so as to reduce the impact of the above problems on signal quality and ensure that the adjusting segment 212 with a larger width is suitable for improving signal quality.

[0030] For example, the width of the signal line 21 is one of the key factors affecting impedance. When the width of the signal line 21 suddenly increases from the base segment 211 to the adjusting segment 212, the impedance at the mutation point will decrease significantly. Any discontinuous point of impedance will cause signal reflection, and the reflected wave will superpose with the original signal, leading to distortion of the signal waveform and phenomena such as overshoot, undershoot and ringing. Moreover, reflection itself also represents the loss of signal energy, which reduces signal quality at this time.

[0031] Therefore, in order to reduce the impedance mutation caused by the above-mentioned width mutation of the signal line 21, the connection between the base segment 211 and the adjusting segment 212 can be arranged as a transition segment, wherein the width of the transition segment gradually increases from the base segment 211 to the adjusting segment 212. In this way, arranging the transition segment can avoid the size mutation between the base segment 211 and the adjusting segment 212, reduce the impact of impedance mutation caused by the width mutation of the signal line 21 on signal quality, so as to improve signal quality.

[0032] In addition, current tends to select the path with the smallest resistance. In the width transition region between the base segment 211 and the adjusting segment 212, the current distribution will change. At the entry point where current enters the adjusting segment 212 from the base segment 211, the local current density increases abnormally. During long-term operation, the migration of metal atoms at these current density hot spots is accelerated, which may lead to open circuit (formation of voids) or short circuit (formation of hills) of the wire, seriously reducing the reliability of interconnection.

[0033] Therefore, by reasonably setting the width of the adjusting segment 212, the above influence can be reduced, and the increase of the width of the adjusting segment 212 has more positive effects on improving signal quality, so that signal quality can be improved.

[0034] In some embodiments, with reference to Figures 2 to 4 As shown in the figure, the number of the adjusting segments 212 of each signal line 21 can be set to one or more. In this way, arranging a plurality of adjusting segments 212 allows reasonably increasing the cross-sectional size of the signal line 21 in the allowable space region, so that signal quality can be improved.

[0035] It can be understood that a plurality of adjusting segments 212 can be arranged adjacently or at intervals. For example, with reference to Figure 4As shown, the signal line 21 has two adjacent adjustment segments 212. Based on reasonable wiring, the two adjustment segments 212 have different widths to further increase the cross-sectional size of the signal line 21 and make reasonable use of the available space.

[0036] In some other possible embodiments not shown in the accompanying drawings, due to the influence of dense wiring areas, signal line 21 can have a base segment 211 in the dense wiring area and an adjustment segment 212 in the allowable space area. Therefore, signal line 21 can have multiple spaced adjustment segments 212 to make reasonable use of the allowable space and improve signal quality. This disclosure is not limited thereto.

[0037] In some embodiments, reference Figures 2 to 4 As shown, at least two adjustment segments 212 in the same signal line 21 have different widths, and the signal line 21 has two adjacent adjustment segments 212 with different widths. It is understood that in other embodiments, the length of the two adjustment segments 212 may also include three adjustment segments 212, and the widths of the three adjustment segments 212 may increase sequentially along the extension direction of the signal line 21 to reduce the width variation between adjacent adjustment segments 212 and reduce the effects of, for example, impedance abrupt changes and local increases in current density.

[0038] Alternatively, in some other embodiments, due to the limitations of densely wired areas, signal lines 21 can have a base segment 211 in the densely wired area and an adjustment segment 212 in the allowable space area. Therefore, signal lines 21 can have multiple spaced adjustment segments 212, and the width of the adjustment segments 212 within the same signal line 21 can be the same. It is understood that the widths of the multiple adjustment segments 212 can also be different to make more efficient use of the allowable space and improve signal quality. This disclosure is not limited thereto.

[0039] In some embodiments, reference Figures 2 to 4 As shown, the wiring layer 2 may include a first signal line 21a and a second signal line 21b, wherein the length of the first signal line 21a is greater than the length of the second signal line 21b, and the length of the adjustment segment 212 of the first signal line 21a is greater than the length of the adjustment segment 212 of the second signal line 21b. Thus, by providing a longer adjustment segment 212, the signal quality of the longer signal line 21 is improved.

[0040] It is understood that the lengths of the two signal lines 21 are compared under the premise that the widths of the two signal lines 21 are the same. As can be seen from the foregoing description of the cross-sectional dimensions of the signal lines 21, in some other embodiments, the lengths of the adjustment segments 212 of the two signal lines 21 are the same. The width of the adjustment segment 212 of the first signal line 21a can be greater than the width of the adjustment segment 212 of the second signal line 21b, or the depth of the adjustment segment 212 of the first signal line 21a can be greater than the depth of the adjustment segment 212 of the second signal line 21b. Of course, the width and depth of the adjustment segment 212 of the first signal line 21a can both be greater than the width and depth of the adjustment segment 212 of the second signal line 21b, in order to improve the signal quality. This disclosure does not impose specific limitations on this.

[0041] It is understandable that in order to improve the signal quality of the aforementioned longer signal line 21, it is necessary to adopt at least one of the following methods: increasing the length of the adjustment section 212, widening the width of the adjustment section 212, and deepening the depth of the adjustment section 212. Therefore, it is necessary to reasonably arrange the multiple signal lines 21.

[0042] In some embodiments, reference Figures 2 to 4 As shown, signal lines 21 extend along a first direction, and signal lines 21 are spaced apart along a second direction perpendicular to the first direction. Along the second direction, adjacent signal lines 21 have different lengths. For ease of description, the longer signal line 21 is designated as the first signal line 21a, and the shorter signal line 21 is designated as the second signal line 21b. Therefore, along the first direction, the front end of the second signal line 21b after it stops extending forms an allowable space, allowing the first signal line 21a to form an adjustment section 212 within this allowable space region, thereby increasing the cross-sectional size of the signal line 21.

[0043] For example, refer to Figure 2 As shown, multiple signal lines 21 can be arranged at intervals along the second direction, and along the second direction, the length of the signal lines 21 first increases and then decreases, and then increases and decreases again, so that in two adjacent signal lines 21, the front end of the shorter signal line 21 after it stops extending forms an allowable space, so that the longer signal line 21 forms an adjustment segment 212 in the allowable space area. (Reference) Figure 3 As shown, multiple signal lines 21 can be arranged at intervals along the second direction, and along the second direction, the length of the signal lines 21 first increases and then decreases. (Reference) Figure 4 As shown, multiple signal lines 21 can be arranged at intervals along the second direction, and along the second direction, two adjacent signal lines 21 have different lengths, making the longer signal line 21 suitable for forming an adjustment section 212.

[0044] Furthermore, in some other possible embodiments not shown in the accompanying drawings, the plurality of signal lines 21 may be arranged at intervals along the second direction, and the length of the signal lines 21 may gradually increase or decrease along the second direction. This disclosure is not limited thereto.

[0045] In some embodiments, reference Figure 1 As shown, the interposer board 10 includes multiple wiring layers 2 spaced apart along the thickness direction of the substrate layer 1. At least one signal line 21 of the wiring layer 2 has a base segment 211 and an adjustment segment 212. Thus, by setting multiple wiring layers 2, wiring density can be significantly improved, overcoming the limitations of a two-dimensional plane, avoiding signal crossover conflicts, and achieving hierarchical routing. Furthermore, the multiple wiring layers 2 penetrate the thickness direction of the interposer board 10 through TSVs (vertical interconnects), vertically transferring signals from the top-level chip (such as a CPU) to the bottom-level substrate (such as a PCB). Simultaneously, each wiring layer 2 is responsible for short-distance horizontal interconnections, allowing TSVs to solve the vertical conduction problem, and the multiple wiring layers 2 to solve the high-density horizontal routing problem, forming a three-dimensional interconnect network of "vertical penetration + horizontal layering," shortening the signal path.

[0046] According to the second aspect of this disclosure, reference to Figure 1 As shown, a semiconductor device 1000 is provided, including a memory 20, a processor 30, and the aforementioned interposer 10. The memory 20 and processor 30 are disposed on the interposer 10 and electrically connected via a wiring layer 2. Exemplarily, the interposer 10 may include a plurality of microbumps 3 for connecting to the memory 20 and processor 30. Furthermore, the interposer 10 may also include a plurality of solder balls 4 for connecting to a substrate or PCB board, etc. The memory 20 may include, for example, DRAM, SRAM, ROM, etc., and the processor 30 may include, for example, a CPU, GPU, IPU, etc. This disclosure does not specifically limit the application of this technology.

[0047] According to a third aspect of this disclosure, an electronic device is provided, including the aforementioned semiconductor device 1000. This electronic device possesses all the beneficial effects of the aforementioned semiconductor device 1000, which will not be elaborated further herein. Furthermore, this electronic device may be, for example, a computer, a mobile phone, a tablet, etc. This disclosure is not limited thereto.

[0048] The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings. However, the present disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0049] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0050] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. An intermediary connection plate, characterized in that, include: Substrate layer; as well as A wiring layer is formed on the substrate layer, the wiring layer including a plurality of signal lines, at least a portion of the signal lines having a base segment and an adjustment segment. The cross-sectional dimensions of the adjustment section are larger than those of the base section.

2. The intermediary connecting plate according to claim 1, characterized in that, The width of the adjustment segment is greater than the width of the base segment.

3. The intermediary connecting plate according to claim 2, characterized in that, The ratio of the width of the adjustment segment to the width of the base segment is K, where 1 <K<2。 4. The intermediary connecting plate according to claim 1, characterized in that, The number of adjustment segments for each signal line is set to one or more.

5. The intermediary connecting plate according to claim 4, characterized in that, The widths of the adjustment segments in the same signal line are the same; or At least two of the adjustment segments in the same signal line have different widths.

6. The intermediary connecting plate according to claim 1, characterized in that, The wiring layer includes a first signal line and a second signal line, wherein the length of the first signal line is greater than the length of the second signal line; The length of the adjustment segment of the first signal line is greater than the length of the adjustment segment of the second signal line.

7. The intermediary connecting plate according to claim 1, characterized in that, The signal lines extend along a first direction and are spaced apart along a second direction perpendicular to the first direction. Along the second direction, two adjacent signal lines have different lengths.

8. The intermediary connecting plate according to any one of claims 1-7, characterized in that, The interfacing board includes multiple wiring layers spaced apart along the thickness direction of the substrate layer, and at least one of the wiring layers has a base segment and an adjustment segment for its signal lines.

9. A semiconductor device, characterized in that, Includes a memory, a processor, and an intermediary connection board as described in any one of claims 1-8. The memory and the processor are disposed on the intermediate connection board and electrically connected through the wiring layer.

10. An electronic device, characterized in that, Includes the semiconductor device as described in claim 9.

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