A packaging structure

Abstract

The application provides a packaging structure, which comprises a first chip, the first chip comprising a connecting component, the connecting component comprising three first electric connecting pieces, the first chip having an active surface and a passive surface arranged oppositely, and the connecting component being arranged on the active surface; a dielectric layer, the dielectric layer covering the first chip; and a first lead hole, the first lead hole being electrically connected with the connecting component; wherein the three first electric connecting pieces of the connecting component are arranged linearly, and the first lead hole is electrically connected with two first electric connecting pieces located at two ends among the three first electric connecting pieces arranged linearly. The application has the advantages that the use of shorter lead holes instead of higher electric columns is realized by thinning the chip, the manufacturing difficulty and cost are reduced, the solder pad structure is used for electric connection on the back surface of the chip, the connection area is large, the mechanical strength is high, the probability of poor connection is reduced, and the electric column has better electrical performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more specifically, to a packaging structure. Background Technology

[0002] With the improvement of computing power, semiconductor packaging products continue to develop towards miniaturization and high integration. Chip stacking is one of the most common packaging structures today. As the number of chips in a stacked packaging structure increases, fan-out packaging, 2.5D and 3D packaging structures have been developed. Existing 3D packaging structures typically employ technologies such as back-side power pads, nTSVs (nanoscale through-silicon vias), and Si substrates.

[0003] Figure 1 A schematic diagram of a prior art packaging structure is shown. Figure 2 As shown Figure 1 The diagram shows an enlarged view of portion A, a component of a prior art packaging structure. (See diagram for example.) Figures 1 to 2 As shown, the packaging structure includes a first packaging layer 901, a substrate 902, a second packaging layer 903, a circuit layer 904, a via 905, a chip 906, and an electrical connector 907. The chip 906 is disposed on the substrate 902, and the first packaging layer 901 covers the chip 906. The circuit layer 904 is disposed on the upper surface of the first packaging layer 901. The chip 906 has an electrical connector 907 on the side opposite to the substrate 902. The electrical connector 907 is electrically connected to the circuit layer 904 through the via 905. The second packaging layer 903 is disposed on the other side of the substrate 902 opposite to the chip 906.

[0004] The disadvantage of the existing packaging structure is that the via 905 is usually manufactured using nTSV and Si carrier technology. Because the via 905 has a large depth and a high aspect ratio, this leads to a high level of process difficulty and a long process time, making it difficult to reduce production costs.

[0005] In summary, there is a need in the art to provide a packaging structure that can overcome the shortcomings of the prior art. Utility Model Content

[0006] This application provides a packaging structure that can solve the problems of the prior art. The objective of this application is achieved through the following technical solution.

[0007] One embodiment of this application provides a packaging structure comprising: a first chip, the first chip including a connecting component, the connecting component including three first electrical connectors, the first chip having an active surface and a passive surface disposed opposite to each other, the connecting component being disposed on the active surface; a dielectric layer covering the first chip; and a first via electrically connected to the connecting component; wherein the three first electrical connectors of the connecting component are linearly arranged, and the first via is electrically connected to two of the three linearly arranged first electrical connectors located at both ends.

[0008] In some alternative embodiments, the packaging structure provided according to one embodiment of this application above, wherein the first chip is a thinned chip.

[0009] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a first connection layer, the first connection layer including a first conductive layer and a first seed layer stacked together, the first via being electrically connected to a connecting component through the first connection layer, the first seed layer being electrically connected to the connecting component, and the first conductive layer being electrically connected to the first via.

[0010] In some alternative embodiments, the encapsulation structure provided according to one embodiment of the present application above has a first connecting layer with an inverted W-shaped cross-section in the side view direction.

[0011] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the end of the first guide hole connected to the first connecting layer has an inwardly concave V-shaped cross-section in the side view direction, and the end of the inwardly concave V-shaped first guide hole cooperates with the inverted W-shaped first connecting layer to form an electrical connection.

[0012] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the two upwardly protruding ends of the first connecting layer, which is inverted W-shaped, are electrically connected to two of the three linearly arranged first electrical connectors located at both ends.

[0013] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the middle first electrical connector of the three linearly arranged first electrical connectors is isolated from the first via.

[0014] In some alternative implementations, the packaging structure provided according to one of the above embodiments of this application, wherein the first chip is an active chip.

[0015] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application further includes a second chip and a redistribution layer, wherein the second chip is electrically connected to the first chip through the redistribution layer.

[0016] In some alternative embodiments, the packaging structure provided according to one embodiment of this application above, wherein the size of the second chip is smaller than the size of the first chip.

[0017] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a second via, which is electrically connected to the second chip through a redistribution layer.

[0018] In some optional embodiments, the packaging structure provided according to one embodiment of the present application includes a plurality of first vias, and the first chip includes a plurality of connecting components, each connecting component being electrically connected to one of the first vias.

[0019] The advantages of the packaging structure according to the embodiments of this application are: by thinning the chip, shorter vias are used to replace taller electrode pillars, reducing manufacturing difficulty and cost; the back of the chip uses a pad structure for electrical connection, which has a large connection area, high mechanical strength, reduces the probability of poor connection, and has better electrical performance than electrode pillars. Attached Figure Description

[0020] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0021] Figure 1 A schematic diagram of a prior art packaging structure is shown;

[0022] Figure 2 As shown Figure 1 An enlarged schematic diagram of part A in a prior art packaging structure is shown;

[0023] Figure 3 A schematic diagram of a packaging structure according to an embodiment of this application is shown;

[0024] Figure 4 As shown Figure 3 An enlarged schematic diagram of the portion marked B in the packaging structure according to an embodiment of this application is shown;

[0025] Figure 5 As shown Figure 3 An enlarged schematic diagram of the portion marked C in the packaging structure according to an embodiment of this application is shown;

[0026] Figure 6-1 , 6-2 Tables 6-3, 6-4, 6-5, and 6-6 show examples such as... Figure 3 The diagram shown is a manufacturing process diagram of a packaging structure according to an embodiment of this application;

[0027] Figure 7 A schematic diagram of the packaging structure according to a second embodiment of this application is shown;

[0028] Figure 8 A schematic diagram of the packaging structure according to a third embodiment of this application is shown;

[0029] Figure 9 A schematic diagram of the packaging structure according to the fourth embodiment of this application is shown;

[0030] Figure 10 A schematic diagram of a package structure using panel-level (PNL) packaging according to one embodiment of this application is shown.

[0031] Figure 11 A schematic diagram of a package structure using wafer-level (WL) packaging according to one embodiment of this application is shown.

[0032] Labels and component names: 1-First chip, 2-Dielectric layer, 3-First via, 4-First connection layer, 5-Second chip, 6-Redistribution layer, 11-Connector, 12-Active surface, 13-Passive surface, 31-Sub-via, 32-Gap, 41-First conductive layer, 42-First seed layer, 111-First electrical connector, 7-Second electrical connector, 8-Second via, 101-First chip, 101a-Bump, 102-Carrier, 103-First sealing layer, 104-Second sealing layer, 104a-First through-hole, 104b-First via, 104c-First circuit layer, 105-First seed layer, 106-Third sealing layer, 106a-Groove, 107-First... Four-layer encapsulation, 107a-Second via, 107b-Second circuit layer, 108-Second chip, 108a-First electrical connector, 109-Fifth encapsulation, 110-Sixth encapsulation, 110a-First trench, 111-Seventh encapsulation, 111a-Second trench, 111b-Second seed layer, 111c-Pad, 112-Eighth encapsulation, 112a-Second via, Third seed layer 112b, 113-Ninth encapsulation, 114-Third via, 115-Fourth via, 116-Solder, 901-First encapsulation layer, 902-Substrate, 903-Second encapsulation layer, 904-Circuit layer, 905-via, 906-Chip, 907-Electrical connector. Detailed Implementation

[0033] The specific embodiments of this application are described below with reference to the accompanying drawings and examples. Through the content described in this specification, those skilled in the art can clearly and completely understand the technical solution, the technical problem solved, and the resulting technical effects of this application. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, for ease of description, only the parts related to this application are shown in the accompanying drawings.

[0034] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0035] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0036] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0037] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0038] The term "electrical connector" as used in this article can refer to a pad or a bump. A bump can be, for example, a gold bump (usually rectangular and made of gold), a solder bump (usually round and made of copper and tin), or a pillar bump (usually octagonal or polygonal and made of copper and tin or lead and tin).

[0039] As used herein, the term "redistribution layer (RDL)" can refer to a layer composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies, and this disclosure does not specifically limit this. For example, redistribution layers can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0040] The term "dielectric material" or "dielectric layer" as used herein may include organic and / or inorganic materials, wherein organic materials may be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0041] The term "molding compound" as used herein includes, but is not limited to, epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0042] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] Figure 3 A schematic diagram of a packaging structure according to an embodiment of this application is shown. Figure 4 As shown Figure 3 The diagram shown is an enlarged view of portion B in the packaging structure according to an embodiment of this application. Figure 5 As shown Figure 3 The diagram shows an enlarged view of the portion marked C in the packaging structure according to an embodiment of this application. Figures 3 to 5As shown, the packaging structure includes: a first chip 1, the first chip 1 including a connecting component 11, the connecting component 11 including three first electrical connectors 111, the first chip 1 having an active surface 12 and a passive surface 13 disposed opposite to each other, the connecting component 11 being disposed on the active surface 12; a dielectric layer 2 covering the first chip 1; a first via 3 electrically connected to the connecting component 11; wherein, the three first electrical connectors 111 of the connecting component 11 are arranged linearly, and the first via 3 is electrically connected to two of the three linearly arranged first electrical connectors 111 located at both ends.

[0044] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application above, wherein the first chip 1 is a thin chip.

[0045] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a first connection layer 4, the first connection layer 4 including a first conductive layer 41 and a first seed layer 42 stacked together, the first via 3 being electrically connected to the connecting component 11 through the first connection layer 4, the first seed layer 42 being electrically connected to the connecting component 11, and the first conductive layer 41 being electrically connected to the first via 3.

[0046] In some alternative embodiments, the encapsulation structure provided according to one embodiment of the present application above has a first connecting layer 4 in an inverted W-shaped cross-section in a side view direction.

[0047] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the end of the first guide hole 3 connected to the first connecting layer 4 has an inwardly concave V-shaped cross section in the side view direction, and the inwardly concave V-shaped end of the first guide hole 3 cooperates with the inverted W-shaped first connecting layer 4 to form an electrical connection.

[0048] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the two upwardly protruding ends of the first connecting layer 4, which is in the shape of an inverted W, are respectively electrically connected to two of the three linearly arranged first electrical connectors 111 located at both ends.

[0049] In some alternative embodiments, according to the packaging structure provided by one embodiment of this application, the V-shaped and W-shaped connection structure enables the first connection layer 4 to better connect with the minute-sized first via 3, improving the electrical performance of the connection structure and facilitating the improvement of electrical signal transmission capability and power supply capability through the minute via. Specifically, because the size difference between the first electrical connector 111 and the first via 3 is significant, the characteristics of laser apertures and the tapered aperture structure allow the large-sized first via 3 to smoothly convert its size and electrically connect with the first electrical connector 111.

[0050] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the middle first electrical connector 111 of the three linearly arranged first electrical connectors 111 is isolated from the first guide hole 3.

[0051] In some alternative implementations, according to the packaging structure provided by one of the above embodiments of this application, the first chip 1 is an active chip.

[0052] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a second chip 5 and a redistribution layer 6, wherein the second chip 5 is electrically connected to the first chip 1 through the redistribution layer 6.

[0053] In some alternative embodiments, according to the packaging structure provided by one embodiment of this application above, the size of the second chip 5 is smaller than the size of the first chip 1.

[0054] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a second via 8, which is electrically connected to the second chip 5 through a redistribution layer 6.

[0055] In some optional embodiments, the packaging structure provided according to one embodiment of the present application includes a plurality of first vias 3, and the first chip 1 includes a plurality of connecting components 11, each connecting component 11 being electrically connected to a first via 3.

[0056] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application further includes a second electrical connector 7, which is located at the bottom of the packaging structure and electrically connected to the second guide hole 8.

[0057] In some optional embodiments, the packaging structure provided according to one embodiment of the present application further includes a first molding layer 9 and a second molding layer 10, wherein the first molding layer 9 covers the second chip 5, and the second molding layer 10 is located below the dielectric layer 2 and between the chip 1 and the first interconnect layer 4.

[0058] In some optional embodiments, according to the packaging structure provided by one embodiment of this application, the size of the first chip 1 is between several millimeters and tens of millimeters, and the thickness of the first chip 1 is between several micrometers and tens of micrometers; the size of the second chip 5 is between hundreds of micrometers and several millimeters; the thickness of the first molding layer 9 is between several millimeters and tens of millimeters; the thickness of the redistribution layer 6 is between 1 micrometer and 10 micrometers; the thickness of the second molding layer 10 is between 1 micrometer and 10 micrometers; the width of the first electrical connector 111 and the spacing between the first electrical connectors 111 are both between 3 micrometers and 20 micrometers; the thickness of the first conductive layer 41 and the first seed layer 42 are both between 0.1 micrometers and 0.5 micrometers; the angle α between the two sides of the inverted W-shaped first connection layer 4 and the horizontal direction (e.g., α) Figure 5 The included angle a) is between 5° and 85°; the first chip 1 is embedded in the lower surface of the dielectric layer 2 and the embedding depth is between 1 micrometer and 10 micrometers.

[0059] Figure 6-1 , 6-2 Tables 6-3, 6-4, 6-5, and 6-6 show examples such as... Figure 3 The diagram shown illustrates the manufacturing process of a packaging structure according to an embodiment of this application. Figure 6-1 , 6-2 As shown in Figures 6-3, 6-4, 6-5, and 6-6, the manufacturing process of the packaging structure includes the following steps:

[0060] Step 1001: Provide a carrier board 102, and set a first chip 101 on the carrier board 102, with the side of the first chip 101 with bumps 101a facing upward;

[0061] Step 1002: Set the first mold sealing layer 103, and then set the second mold sealing layer 104; wherein, the first mold sealing layer 103 covers the side of the first chip 101, and the second mold sealing layer 104 is set above the first mold sealing layer 103 and the first chip 101 and covers the upper surface of the first chip 101;

[0062] Step 1003: Etch the second mold sealing layer 104;

[0063] Step 1004: A first seed layer 105 is provided on the upper surface of the second mold sealing layer 104 and on the inner wall of the first through hole 104a formed by etching;

[0064] Step 1005: Set a third mold cover layer 106 above the first seed layer 105, and then etch the third mold cover layer 106;

[0065] Step 1006: Electroplating is performed in the groove 106a etched on the third mold sealing layer 106 to form the first guide hole 104b;

[0066] Step 1007: Remove the third mold sealing layer 106 and form a patterned first circuit layer 104c on the upper surface of the second mold sealing layer 104;

[0067] Step 1008: Set a fourth mold sealing layer 107 above the second mold sealing layer 104;

[0068] Step 1009: Form the second via 107a and the second circuit layer 107b on the fourth mold sealing layer 107, referring to the methods in steps 1005-1007;

[0069] Step 1010: A second chip 108 is disposed on the fourth mold sealing layer 107, and the second chip 108 is electrically connected to the second circuit layer 107b through the first electrical connector;

[0070] Step 1011: Configure all second chips 108;

[0071] Step 1012: Use the fifth encapsulation layer 109 to cover the second chip 108;

[0072] Step 1013: Remove carrier plate 102;

[0073] Step 1014: Flip the product made in step 1013 and remove the first mold sealing layer 103 by chemical etching;

[0074] Step 1015: Thin the first chip 101 by chemical etching;

[0075] Step 1016: Deposit a sixth mold sealing layer 110 above the first chip 101 and the second mold sealing layer 104;

[0076] Step 1017: Etch a W-shaped first trench 110a on the sixth mold sealing layer 110;

[0077] Step 1018: Set the seventh mold sealing layer 111 on the sixth mold sealing layer 110;

[0078] Step 1019: Etch a W-shaped second trench 111a on the seventh mold sealing layer 111 and set a second seed layer 111b on the upper surface of the seventh mold sealing layer 111 and in the second trench 111a;

[0079] Step 1020: Electroplating is performed in the second trench 111a to form pads 111c;

[0080] Step 1021: Remove the seventh layer cover 111;

[0081] Step 1022: Place the eighth mold sealing layer 112 above the sixth mold sealing layer 110;

[0082] Step 1023: Laser etching of the eighth mold sealing layer 112, the sixth mold sealing layer 110, and the second mold sealing layer 104 forms a second through hole 112a, so that the first guide hole 104b and the pad 111c are exposed from the second through hole 112a, and then a third seed layer 112b is set in the second through hole 112a.

[0083] Step 1024; Set a ninth mold sealing layer 113 above the eighth mold sealing layer 112;

[0084] Step 1025: Etch the ninth mold sealing layer 113 at the position of the second through hole 112a and electroplate the third guide hole 114 and the fourth guide hole 115 in the second through hole 112a; wherein, the third guide hole 114 is connected to the pad 111c and the fourth guide hole 115 is connected to the first guide hole 104b.

[0085] Step 1026: Apply solder 116 above the third guide hole 114 and the fourth guide hole 115;

[0086] Step 1027: Remove the nine-layer cover 113;

[0087] Step 1028: Add solder 116 again; and

[0088] Step 1029: Cut the product made in step 1028.

[0089] Figure 7 A schematic diagram of the packaging structure according to a second embodiment of this application is shown. Figure 7 As shown, the connecting component 11 is flush with the active surface 12 of the chip 1, and the first seed layer 42 is electrically connected to the connecting component 11.

[0090] Figure 8 A schematic diagram of the packaging structure according to a third embodiment of this application is shown. Figure 8 As shown, the first guide hole 3 includes a plurality of sub-guide holes 31, and each first conductive layer 41 is electrically connected to the plurality of sub-guide holes 31.

[0091] Figure 9 A schematic diagram of the packaging structure according to a fourth embodiment of this application is shown. Figure 9 As shown, the first guide hole 3 includes mutually independent sub-guide holes 31, and the first connecting layer 4 includes mutually independent sub-connecting layers 4a, with each sub-guide hole 31 connected to a sub-connecting layer 4a.

[0092] Figure 10 A schematic diagram of a package structure using panel-level (PNL) packaging according to one embodiment of this application is shown. Figure 10 As shown, the package structure is rectangular, and the first chip 1 is disposed on the package structure.

[0093] Figure 11 A schematic diagram of a package structure using wafer-level (WL) packaging according to one embodiment of this application is shown. Figure 11 As shown, the package structure is circular, and the first chip 1 is disposed on the package structure.

[0094] The advantages of the packaging structure according to the embodiments of this application are: by thinning the chip, shorter vias are used to replace taller electrode pillars, reducing manufacturing difficulty and cost; the back of the chip uses a pad structure for electrical connection, which has a large connection area, high mechanical strength, reduces the probability of poor connection, and has better electrical performance than electrode pillars.

[0095] Although this application has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not intended to limit the application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the scope of protection of this application as defined by the claims. Differences may exist between the technical representation in this application and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The specification and illustrations should be considered illustrative rather than restrictive, and modifications can be made to suit the purpose and spirit of this application, all of which are within the scope of the claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be rearranged, subdivided, or arranged to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the application.

Claims

1. A packaging structure, characterized in that, include: A first chip, the first chip including a connecting component, the connecting component including three first electrical connectors, the first chip having an active surface and a passive surface disposed opposite to each other, the connecting component being disposed on the active surface; A dielectric layer, wherein the dielectric layer covers the first chip; A first guide hole is electrically connected to the connecting component. The three first electrical connectors of the connecting component are arranged linearly, and the first guide hole is electrically connected to two of the three linearly arranged first electrical connectors located at both ends.

2. The packaging structure according to claim 1, characterized in that, The first chip is a thin chip.

3. The packaging structure according to claim 1, characterized in that, The packaging structure further includes a first connection layer, which includes a first conductive layer and a first seed layer stacked together. The first via is electrically connected to the connection component through the first connection layer, the first seed layer is electrically connected to the connection component, and the first seed layer is electrically connected to the first via.

4. The packaging structure according to claim 3, characterized in that, The first connecting layer has an inverted W-shaped cross-section in the side view direction.

5. The packaging structure according to claim 4, characterized in that, The end of the first guide hole connected to the first connecting layer has an inwardly concave V-shape in cross-section when viewed from the side. The inwardly concave V-shaped end of the first guide hole cooperates with the inverted W-shaped first connecting layer to form an electrical connection.

6. The packaging structure according to claim 4, characterized in that, The two upward-protruding ends of the first connecting layer, which is shaped like an inverted W, are electrically connected to the two first electrical connectors located at both ends of the three linearly arranged first electrical connectors.

7. The packaging structure according to claim 1, characterized in that, Of the three linearly arranged first electrical connectors, the middle one is isolated from the first guide hole.

8. The packaging structure according to claim 1, characterized in that, The first chip is an active chip.

9. The packaging structure according to claim 1, characterized in that, The packaging structure also includes a second chip and a redistribution layer, wherein the second chip is electrically connected to the first chip through the redistribution layer.

10. The packaging structure according to claim 9, characterized in that, The packaging structure also includes a second via, which is electrically connected to the second chip through the redistribution layer.

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