Packaging structure

Abstract

The application provides a packaging structure, comprising at least two circuit frame layers, the circuit frame layers are longitudinally stacked; a mold sealing material, the mold sealing material fills the space between the circuit frame layers; a solder layer, the two adjacent circuit frame layers are fixedly connected through the solder layer, and the mold sealing material covers the side surface of the solder layer; wherein the bottom of the circuit frame layer at the bottom of the packaging structure protrudes from the mold sealing material, the protruding circuit frame layer forms a patterned circuit layer, and the circuit layer comprises at least one independent circuit. The application has the advantages that: the circuit frame layer is used to replace the circuit formed by electroplating, the structural strength, the conductive performance and the heat dissipation capacity of the packaging structure are improved; the packaging structure is not prone to deformation in the process, and the product yield is improved; the electroplating process is not necessary, the production cost is reduced, and the product reliability is improved; the circuit frame layer protruding downward from the bottom of the mold sealing material improves the heat dissipation performance of the packaging structure; and the working stability of the packaging structure in a high-temperature environment is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more specifically, to a packaging structure. Background Technology

[0002] High-power charging systems are gradually becoming the mainstream in the electric vehicle market. Quad Flat No-leads Package (QFN) is a packaging form that can meet the needs of high-power charging and power management. QFN packages offer advantages such as high thermal stability and high reliability; however, most existing QFN package products are single-layer structures and have a low pin count, making them difficult to meet the requirements of all-terrain vehicles (ATVs).

[0003] Furthermore, currently commonly used chip / passive component embedding technology utilizes surface mount technology (SMT) to achieve highly integrated 3D packaging, reducing package size and improving communication efficiency between chips by embedding power chips into the substrate. However, when applying chip / passive component embedding technology to high-power charging devices, regardless of whether organic substrates or integrated circuit boards are used, the thickness of the circuit layers needs to be increased, which leads to an increase in electroplating costs.

[0004] In summary, there is a need in the art to provide a packaging structure that can overcome the shortcomings of the prior art. Utility Model Content

[0005] This application provides a packaging structure that can solve the problems of the prior art. The objective of this application is achieved through the following technical solution.

[0006] One embodiment of this application provides a packaging structure comprising at least two circuit frame layers stacked vertically; a molding compound filled within and between the circuit frame layers; a solder layer fixedly connected between adjacent circuit frame layers, with the molding compound covering the sides of the solder layer; the packaging structure further comprising at least one electronic component disposed between or above the circuit frame layers, with the molding compound covering the electronic component; wherein the bottom of the circuit frame layer at the bottom of the packaging structure protrudes from the molding compound, the protruding circuit frame layer forming a patterned circuit layer, the circuit layer including at least one independent circuit.

[0007] In some alternative embodiments, the packaging structure provided according to one of the above embodiments of this application includes electronic components including chips and / or passive components.

[0008] In some alternative embodiments, according to the packaging structure provided by one embodiment of this application above, the chip includes a first electrical connector, through which the chip is electrically connected to the circuit frame layer.

[0009] In some alternative embodiments, the packaging structure provided according to one embodiment of this application further includes wire bonding, through which the chip is electrically connected to the circuit frame layer.

[0010] In some alternative embodiments, the packaging structure provided according to one embodiment of this application includes chips stacked on top of each other.

[0011] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application further includes an insulating layer, two adjacent circuit frame layers are interconnected by an insulating layer or a solder layer, and a molding compound covers the sides of the solder layer.

[0012] In some alternative embodiments, the packaging structure provided according to one embodiment of this application above, wherein at least a portion of the side of the circuit frame layer is exposed from the side of the molding compound.

[0013] In some alternative embodiments, in the packaging structure provided by one embodiment of the present application, the top of the uppermost circuit frame layer in the stacked circuit frame layers is exposed from the top of the molding compound.

[0014] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, in the stacked circuit frame layers, the bottommost circuit frame layer has a first groove on its side near the bottom surface.

[0015] In some alternative embodiments, the packaging structure provided according to one embodiment of this application includes passive components such as resistors, inductors, capacitors, filters, diodes, or fuses.

[0016] The advantages of the packaging structure according to the embodiments of this application are: the use of a circuit frame layer to replace the electroplated circuit improves the structural strength, conductivity and heat dissipation of the packaging structure; it is less prone to deformation during the manufacturing process, thus improving product yield; it eliminates the need for an electroplating process, reducing production costs and improving product reliability; the circuit frame layer protruding downwards from the bottom of the molding material improves the heat dissipation performance of the packaging structure; and it improves the working stability of the packaging structure in high-temperature environments. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0018] Figure 1 A side view schematic diagram of a packaging structure according to an embodiment of this application is shown;

[0019] Figure 2 It shows the use of, as Figure 1 The diagram shown is a manufacturing process diagram of a packaging structure according to an embodiment of this application;

[0020] Figure 3 A side view schematic diagram of the packaging structure according to a second embodiment of this application is shown;

[0021] Figure 4 It shows the use of, as Figure 3 The diagram shown is a manufacturing process diagram of the packaging structure according to the second embodiment of this application;

[0022] Figure 5 A side view schematic diagram of the packaging structure according to a third embodiment of this application is shown;

[0023] Figure 6 It shows the use of, as Figure 5 The diagram shown is a manufacturing process diagram of the packaging structure according to the third embodiment of this application;

[0024] Figure 7 A side view schematic diagram of the packaging structure according to a fourth embodiment of this application is shown;

[0025] Figure 8 It shows the use of, as Figure 7 The diagram shown is a manufacturing process diagram of the packaging structure according to the fourth embodiment of this application;

[0026] Figure 9 A side view schematic diagram of the packaging structure according to a fifth embodiment of this application is shown;

[0027] Figure 10 It shows the use of, as Figure 9 The diagram shown is a manufacturing process diagram of the packaging structure according to the fifth embodiment of this application;

[0028] Figure 11 A side view schematic diagram of the packaging structure according to the sixth embodiment of this application is shown;

[0029] Figure 12 It shows the use of, as Figure 11 The diagram shown is a manufacturing process diagram of the packaging structure according to the sixth embodiment of this application;

[0030] Figure 13 A side view schematic diagram of the packaging structure according to the seventh embodiment of this application is shown;

[0031] Figure 14It shows the use of, as Figure 13 The diagram shown is a manufacturing process diagram of the packaging structure according to the seventh embodiment of this application;

[0032] Figure 15 A side view schematic diagram of the packaging structure according to the eighth embodiment of this application is shown;

[0033] Figure 16 It shows the use of, as Figure 15 The diagram shown is a manufacturing process diagram of the packaging structure according to the eighth embodiment of this application;

[0034] Figure 17 A side view schematic diagram of the packaging structure according to the ninth embodiment of this application is shown;

[0035] Figure 18 It shows the use of, as Figure 17 The diagram shown is a manufacturing process diagram of the packaging structure according to the ninth embodiment of this application;

[0036] Figure 19 A side view schematic diagram of the packaging structure according to the tenth embodiment of this application is shown;

[0037] Figure 20 It shows the use of, as Figure 19 The diagram shown is a manufacturing process diagram of the packaging structure according to the tenth embodiment of this application;

[0038] Figure 21 A side view schematic diagram of the packaging structure according to the eleventh embodiment of this application is shown;

[0039] Figure 22 It shows the use of, as Figure 21 The diagram shown is a manufacturing process diagram of the packaging structure according to the eleventh embodiment of this application;

[0040] Figure 23 A side view schematic diagram of the packaging structure according to the twelfth embodiment of this application is shown;

[0041] Figure 24 It shows the use of, as Figure 23 The diagram shown is a manufacturing process diagram of the packaging structure according to the twelfth embodiment of this application;

[0042] Figure 25 A side view schematic diagram of the packaging structure according to the thirteenth embodiment of this application is shown;

[0043] Figure 26 It shows the use of, as Figure 25 The diagram shown is a manufacturing process diagram of the packaging structure according to the thirteenth embodiment of this application;

[0044] Figure 27 A side view schematic diagram of the packaging structure according to the fourteenth embodiment of this application is shown;

[0045] Figure 28 It shows the use of, as Figure 27 The diagram shown is a manufacturing process diagram of the packaging structure according to the fourteenth embodiment of this application.

[0046] Labels and component names: 1-Circuit frame layer, 2-Molding material, 3-Solder layer, 4-Chip, 5-Wire bonding, 6-Adhesive layer, 7-Passive component, 8-Insulating layer, 11-Circuit layer, 12-Second groove, 13-First groove, 41-Active surface, 42-Electrical connector, 1a-First circuit frame layer, 1b-Second circuit frame layer, 1c-Third circuit frame layer, 1d-Fourth circuit frame layer, 21-Through hole. Detailed Implementation

[0047] The specific embodiments of this application are described below with reference to the accompanying drawings and examples. Through the content described in this specification, those skilled in the art can clearly and completely understand the technical solution, the technical problem solved, and the resulting technical effects of this application. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, for ease of description, only the parts related to this application are shown in the accompanying drawings.

[0048] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this application should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including intermediate components or layers existing between the two.

[0049] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0050] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the scope of this application and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0051] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0052] The electrical connectors mentioned in this article can be pads / solder pads, bumps, or combinations thereof. Bumps can be, for example, gold bumps (typically rectangular, made of gold), solder bumps (typically round, made of copper and tin), or pillar bumps (typically octagonal or polygonal, made of copper and tin or lead and tin).

[0053] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0054] Figure 1 A side view schematic diagram of a packaging structure according to an embodiment of this application is shown. Figure 1As shown, the packaging structure includes: at least two circuit frame layers 1, which are stacked vertically; a molding compound 2, which fills the space between the circuit frame layers 1; a solder layer 3, which fixes two adjacent circuit frame layers 1 together, and the molding compound 2 covers the sides of the solder layer 3, which helps to further improve the strength of the connection between the two circuit frame layers 1; at least one electronic component (not shown in the figure), which includes a chip 4, and is disposed between or above the circuit frame layers 1, and is covered by the molding compound 2; wherein, the bottom of the circuit frame layer 1 located at the bottom of the packaging structure protrudes from the molding compound 2, and the protruding circuit frame layer 1 forms a patterned circuit layer 11, which includes at least one independent line.

[0055] In some alternative embodiments, according to the encapsulation structure provided by one embodiment of the present application, an independent line refers to a separate line that is not electrically connected to other lines in the line layer 11.

[0056] In some alternative embodiments, according to the packaging structure provided by one embodiment of the present application, the chip 4 includes a first electrical connector 42. In a side view, the active surface 41 of the chip 4 faces downward, the first electrical connector 42 is located on the active surface 41 of the chip 4, and the chip 4 is electrically connected to the circuit frame layer 1 through the first electrical connector 42.

[0057] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application further includes wire bonding 5, through which the chip 4 is electrically connected to the circuit frame layer 1.

[0058] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application, wherein at least a portion of the side of the circuit frame layer 1 is exposed from the side of the molding material 2.

[0059] In some alternative embodiments, according to the packaging structure provided by one embodiment of this application, the chips 4 are stacked on top of each other, such as... Figure 3 As shown, multiple chips 4 are stacked, with the top chip 4 electrically connected to the circuit frame layer 1 via wire bonding, and the bottom chip 4 electrically connected to the circuit frame layer 1 via electrical connector 42.

[0060] Figure 2 It shows the use of, as Figure 1 The diagram shown illustrates the manufacturing process of a packaging structure according to an embodiment of this application. Figure 2 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0061] Step 1001: Place the second circuit frame layer 1b above the first circuit frame layer 1a; wherein, the second circuit frame layer 1b is a fully etched circuit frame; the first circuit frame layer 1a is a partially etched circuit frame; and the bottom of the second circuit frame layer 1b is provided with a solder layer 3.

[0062] Step 1002: The second circuit frame layer 1b is fixedly connected to the top of the first circuit frame layer 1a by the solder layer 3; wherein the second circuit frame layer 1b is disposed along the edge of the upper surface of the first circuit frame layer 1a.

[0063] Step 1003: A stacked chip 4 is disposed at the center of the first circuit frame layer 1a, and the stacked chips 4 are connected to each other by an adhesive layer 6; wherein, the active surface 41 of the bottom chip 4 faces the first circuit frame layer 1a and is electrically connected to the first circuit frame layer 1a by a first electrical connector 42, and the top chip 4 is electrically connected to the second circuit frame layer 1b by a wire bonding 5.

[0064] Step 1004: Use molding compound 2 to cover the stacked chip 4, wire bonding 5, and the upper surface of the second circuit frame layer 1b; and

[0065] Step 1005: Etch the bottom surface of the first circuit frame layer 1a to form a second groove 12 and a circuit layer 11, and expose the mold seal material 2 from the second groove 12.

[0066] Figure 3 A side view schematic diagram of the packaging structure according to a second embodiment of this application is shown. Figure 3 As shown, multiple chips 4 are stacked, with the upper surface of the lower chip 4 exposed from the lower side of the upper chip 4. Each chip 4 is electrically connected to the circuit frame layer 1 via a wire bonding 5.

[0067] Figure 4 It shows the use of, as Figure 3 The diagram shows a manufacturing process schematic of the packaging structure according to the second embodiment of this application. Figure 4 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0068] Step 2001: Place the second circuit frame layer 1b above the first circuit frame layer 1a; wherein, the second circuit frame layer 1b is a fully etched circuit frame; the first circuit frame layer 1a is a partially etched circuit frame; and the bottom of the second circuit frame layer 1b is provided with a solder layer 3.

[0069] Step 2002: The second circuit frame layer 1b is fixedly connected above the first circuit frame layer 1a by the solder layer 3; wherein the second circuit frame layer 1b is disposed along the edge of the upper surface of the first circuit frame layer 1a.

[0070] Step 2003: A stacked chip 4 is disposed at the center of the first circuit frame layer 1a, and the stacked chips 4 are connected to each other by an adhesive layer 6; wherein, the upper surface of the lower chip 4 is exposed from the lower side of the upper chip 4, and each chip 4 is electrically connected to the circuit frame layer 1 by a wire bonding 5.

[0071] Step 2004: Use molding compound 2 to cover the stacked chip 4, wire bonding 5, and the upper surface of the second circuit frame layer 1b; and

[0072] Step 2005: Etch the bottom surface of the first circuit frame layer 1a to form a second groove 12 and a circuit layer 11, and expose the mold seal material 2 from the second groove 12.

[0073] Figure 5 A side view schematic diagram of the packaging structure according to a third embodiment of this application is shown. Figure 5 As shown, the lower chip 4 is electrically connected to the lower circuit frame layer 1 via electrical connector 42, and the upper chip 4 is connected to the upper circuit frame layer 1 via electrical connector 42.

[0074] Figure 6 It shows the use of, as Figure 5 The diagram shows a manufacturing process schematic of the packaging structure according to the third embodiment of this application. Figure 4 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0075] Step 3001: Place the second circuit frame layer 1b above the first circuit frame layer 1a; wherein, the second circuit frame layer 1b is a fully etched circuit frame; the first circuit frame layer 1a is a partially etched circuit frame; and the bottom of the second circuit frame layer 1b is provided with a solder layer 3.

[0076] Step 3002: The second circuit frame layer 1b is fixedly connected above the first circuit frame layer 1a by the solder layer 3; wherein the second circuit frame layer 1b is disposed along the edge of the upper surface of the first circuit frame layer 1a.

[0077] Step 3003: Chips 4 are disposed on the first circuit frame layer 1a and the second circuit frame layer 1b respectively; wherein, the lower chip 4 is connected to the first circuit frame layer 1b through an electrical connector 42, and the upper chip 4 is connected to the second circuit frame layer 1a through an electrical connector 42.

[0078] Step 3004: Cover the stacked chip 4 and the upper surface of the second circuit frame layer 1b with the molding compound 2; and

[0079] Step 3005: Etch the bottom surface of the first circuit frame layer 1a to form the second groove 12 and the circuit layer 11, and the mold sealing material 2 is exposed from the second groove 12.

[0080] Figure 7 A side view schematic diagram of the packaging structure according to a fourth embodiment of this application is shown. Figure 7 As shown, the lower chip 4 is connected to the lower circuit frame layer 1 via an adhesive layer 6 and is electrically connected to the lower circuit frame layer 1 via a bonding wire 5. The upper chip 4 is connected to the upper circuit frame layer 1 via an electrical connector 42.

[0081] Figure 8 It shows the use of, as Figure 7 The diagram shown illustrates the manufacturing process of the packaging structure according to the fourth embodiment of this application. Figure 8 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0082] Step 4001: Place the second circuit frame layer 1b above the first circuit frame layer 1a; wherein, the second circuit frame layer 1b is a fully etched circuit frame; the first circuit frame layer 1a is a partially etched circuit frame; and the bottom of the second circuit frame layer 1b is provided with a solder layer 3.

[0083] Step 4002: The second circuit frame layer 1b is fixedly connected above the first circuit frame layer 1a by the solder layer 3; wherein the second circuit frame layer 1b is disposed along the edge of the upper surface of the first circuit frame layer 1a.

[0084] Step 4003: Chips 4 are disposed on the first circuit frame layer 1a and the second circuit frame layer 1b respectively; wherein, the lower chip 4 is connected to the first circuit frame layer 1a through the adhesive layer 6 and electrically connected to the first circuit frame layer 1a through the bonding wire 5, and the upper chip 4 is connected to the second circuit frame layer 1a through the electrical connector 42.

[0085] Step 4004: Use molding compound 2 to cover the stacked chip 4, wire bonding 5, and the upper surface of the second circuit frame layer 1b; and

[0086] Step 4005: Etch the bottom surface of the first circuit frame layer 1a to form the second groove 12 and the circuit layer 11, and expose the mold seal material 2 from the second groove 12.

[0087] Figure 9 A side view schematic diagram of the packaging structure according to a fifth embodiment of this application is shown. Figure 9 As shown, it includes two line frame layers 1.

[0088] Figure 10 It shows the use of, as Figure 9The diagram shown illustrates the manufacturing process of the packaging structure according to the fifth embodiment of this application. Figure 10 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0089] Step 5001: Place the second circuit frame layer 1b above the first circuit frame layer 1a; wherein, both the first circuit frame layer 1a and the second circuit frame layer 1b are partially etched circuit frames.

[0090] Step 5002: The second circuit frame layer 1b is fixedly connected to the first circuit frame layer 1a above the solder layer 3;

[0091] Step 5003: Use molding material 2 to fill the space between the first circuit frame layer 1a and the second circuit frame layer 1b;

[0092] Step 5004: Etch the first circuit frame layer 1a and the second circuit frame layer 1b, forming second grooves 12 on the lower surface of the first circuit frame layer 1a and the upper surface of the second circuit frame layer 1b, respectively; and

[0093] Step 5005: A chip 4 is disposed on the second circuit frame layer 1b, with the active surface 41 of the chip 4 facing the second circuit frame layer 1b. The chip 4 is electrically connected to the second circuit frame layer 1b through an electrical connector 42. The chip 4 and the upper surface of the second circuit frame layer 1b are covered with a molding material 2.

[0094] Figure 11 A side view schematic diagram of the packaging structure according to a sixth embodiment of this application is shown. Figure 11 As shown, it includes three circuit frame layers 1.

[0095] Figure 12 It shows the use of, as Figure 11 The diagram shown illustrates the manufacturing process of the packaging structure according to the sixth embodiment of this application. Figure 12 As shown, the manufacturing process of its packaging structure includes, for example, Figure 11 Step 5001 shown refers to step 5004, and then the following steps are performed:

[0096] Step 5006: A third circuit frame layer 1c is formed on the second circuit frame layer 1b; wherein, the third circuit frame layer 1c is a partially etched circuit frame.

[0097] Step 5007: Use molding compound 2 to fill the space between the third circuit frame layer 1c and the second circuit frame layer 1b;

[0098] Step 5008: Etch the third circuit frame layer 1c, and form a second groove 12 on the upper surface of the third circuit frame layer 1c; and

[0099] Step 5009: A chip 4 is disposed on the third circuit frame layer 1c, with the active surface 41 of the chip 4 facing the third circuit frame layer 1c. The chip 4 is electrically connected to the third circuit frame layer 1c through an electrical connector 42. The chip 4 and the upper surface of the third circuit frame layer 1c are covered with a molding material 2.

[0100] Figure 13 A side view schematic diagram of the packaging structure according to a seventh embodiment of this application is shown. Figure 11 As shown, the electronic component also includes a passive component 7. A chip 4 and a passive component 7 are disposed between two stacked circuit frame layers 1, and a chip 4 is disposed above the two stacked circuit frame layers 1. The chip 4 disposed above the two circuit frame layers 1 is electrically connected to the circuit frame layer 1 through an electrical connector 42.

[0101] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application includes, but is not limited to, a resistor, inductor, capacitor, filter, diode or fuse.

[0102] Figure 14 It shows the use of, as Figure 13 The diagram shown illustrates the manufacturing process of the packaging structure according to the seventh embodiment of this application. Figure 14 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0103] Step 6001: Place the second circuit frame layer 1b above the first circuit frame layer 1a; wherein, the first circuit frame layer 1a and the second circuit frame layer 1b are both partially etched circuit frames, the upper surface of the first circuit frame layer 1a is provided with chip 4 and passive component 7, and the lower surface of the second circuit frame layer 1b is provided with chip 4 and passive component 7.

[0104] Step 6002: The second circuit frame layer 1b is fixedly connected to the first circuit frame layer 1a above the solder layer 3;

[0105] Step 6003: Use molding material 2 to fill the space between the first circuit frame layer 1a and the second circuit frame layer 1b; wherein, the molding material 2 covers the chip 4 and the passive component 7 between the first circuit frame layer 1a and the second circuit frame layer 1b;

[0106] Step 6004: Etch the first circuit frame layer 1a and the second circuit frame layer 1b, forming second grooves 12 on the lower surface of the first circuit frame layer 1a and the upper surface of the second circuit frame layer 1b, respectively; and

[0107] Step 6005: A chip 4 is disposed on the second circuit frame layer 1b, with the active surface 41 of the chip 4 facing the second circuit frame layer 1b. The chip 4 is electrically connected to the second circuit frame layer 1b through an electrical connector 42. A molding material 2 is used to cover the chip 4 and the upper surface of the second circuit frame layer 1b.

[0108] Figure 15 A side view schematic diagram of the packaging structure according to the eighth embodiment of this application is shown. Figure 15 As shown, a chip 4 and a passive component 7 are disposed between three stacked circuit frame layers 1, and a chip 4 is disposed above the three stacked circuit frame layers 1. The chip 4 disposed above two circuit frame layers 1 is electrically connected to the circuit frame layer 1 through an electrical connector 42.

[0109] Figure 16 It shows the use of, as Figure 15 The diagram shown is a manufacturing process diagram of the packaging structure according to the eighth embodiment of this application. Figure 16 As shown, the manufacturing process of its packaging structure includes, for example, Figure 14 Step 6001 shown refers to step 6004, and then the following steps are performed:

[0110] Step 6006: A chip 4 is disposed on the second circuit frame layer 1b. The chip 4 is connected to the second circuit frame layer 1b through an adhesive layer 6 and electrically connected to the second circuit frame layer 1b through a wire bonding 5.

[0111] Step 6007: A third circuit frame layer 1c is disposed on the upper surface of the second circuit frame layer 1b near the edge; wherein, the third circuit frame layer 1c is a fully etched circuit frame, and the third circuit frame layer 1c is disposed around the outside of the chip 4; and

[0112] Step 6008: A chip 4 is disposed on the second circuit frame layer 1b, with the active surface 41 of the chip 4 facing the second circuit frame layer 1b. The chip 4 is electrically connected to the second circuit frame layer 1b through an electrical connector 42. The chip 4 and the upper surface of the second circuit frame layer 1b are covered with a molding material 2.

[0113] Figure 17 A side view schematic diagram of the packaging structure according to the ninth embodiment of this application is shown. Figure 17 As shown, a chip 4 is disposed between two stacked circuit frame layers 1 and above the two stacked circuit frame layers 1. The chip 4 disposed above the two circuit frame layers 1 is electrically connected to the circuit frame layers 1 through an electrical connector 42.

[0114] Figure 18 It shows the use of, as Figure 17 The diagram shown illustrates the manufacturing process of the packaging structure according to the ninth embodiment of this application. Figure 18 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0115] Step 7001: Place the second circuit frame layer 1b above the first circuit frame layer 1a; wherein, the first circuit frame layer 1a and the second circuit frame layer 1b are both partially etched circuit frames, the upper surface of the first circuit frame layer 1a is provided with chip 4, and the lower surface of the second circuit frame layer 1b is provided with chip 4.

[0116] Step 7002: The second circuit frame layer 1b is fixedly connected to the first circuit frame layer 1a above the solder layer 3;

[0117] Step 7003: Use molding material 2 to fill the space between the first circuit frame layer 1a and the second circuit frame layer 1b; wherein, the molding material 2 covers the chip 4 between the first circuit frame layer 1a and the second circuit frame layer 1b.

[0118] Step 7004: Etch the first circuit frame layer 1a and the second circuit frame layer 1b, forming second grooves 12 on the lower surface of the first circuit frame layer 1a and the upper surface of the second circuit frame layer 1b, respectively; and

[0119] Step 7005: A chip 4 is disposed on the second circuit frame layer 1b, with the active surface 41 of the chip 4 facing the second circuit frame layer 1b. The chip 4 is electrically connected to the second circuit frame layer 1b through an electrical connector 42. The chip 4 and the upper surface of the second circuit frame layer 1b are covered with a molding material 2.

[0120] Figure 19 A side view schematic diagram of the packaging structure according to the tenth embodiment of this application is shown. Figure 18 As shown, a chip 4 and a passive component 7 are disposed between four stacked circuit frame layers 1, and a chip 4 is disposed above the four stacked circuit frame layers 1. The chip 4 disposed above two circuit frame layers 1 is electrically connected to the circuit frame layer 1 through an electrical connector 42.

[0121] Figure 20 It shows the use of, as Figure 19 The diagram shown illustrates the manufacturing process of the packaging structure according to the tenth embodiment of this application. Figure 20 As shown, the manufacturing process of its packaging structure includes, for example, Figure 18 Step 7001 shown refers to step 7004, and then the following steps are performed:

[0122] Step 7006: A passive element 7 is installed on the second circuit frame layer 1b, and the passive element 7 is electrically connected to the second circuit frame layer 1b.

[0123] Step 7007: A third circuit frame layer 1c is formed on the upper surface of the second circuit frame layer 1b; wherein, the third circuit frame layer 1c is a partially etched circuit frame.

[0124] Step 7008: A fourth circuit frame layer 1d is provided on the lower surface of the first circuit frame layer 1a; wherein, the fourth circuit frame layer 1d is a partially etched circuit frame and a passive element 7 is provided on the upper surface of the fourth circuit frame layer 1d, and the passive element 7 is electrically connected to the fourth circuit frame layer 1d.

[0125] Step 7009: Fill the space between the third circuit frame layer 1c and the second circuit frame layer 1b, and the space between the first circuit frame layer 1a and the fourth circuit frame layer 1d, using molding compound 2; wherein, molding compound 2 covers the passive element 7 between the third circuit frame layer 1c and the second circuit frame layer 1b, and the passive element 7 between the first circuit frame layer 1a and the fourth circuit frame layer 1d; and

[0126] Step 7010: A second groove 12 is etched on the upper surface of the third circuit frame layer 1c and the lower surface of the fourth circuit frame layer 1d. A chip 4 is disposed on the third circuit frame layer 1c, with the active surface 41 of the chip 4 facing the third circuit frame layer 1c. The chip 4 is electrically connected to the third circuit frame layer 1c through an electrical connector 42. The chip 4 and the upper surface of the third circuit frame layer 1c are covered with a molding material 2.

[0127] Figure 21 A side view schematic diagram of the packaging structure according to the eleventh embodiment of this application is shown. Figure 21 As shown, in the stacked circuit frame layer 1, the bottommost circuit frame layer 1 has a first groove 13 on its side near the bottom surface.

[0128] In some alternative embodiments, according to the above-described embodiment of the present application, the packaging structure wherein the first groove 13 exposes the side of the circuit frame layer 1 from the mold layer, facilitating Automated Optical Inspection (AOI); at the same time, by forming a wettable structure, its metallized surface is compatible with solder, ensuring a reliable connection during soldering, which is beneficial to improving product reliability, which is particularly important in automotive environments.

[0129] Figure 22 It shows the use of, as Figure 21 The diagram shown illustrates the manufacturing process of the packaging structure according to the eleventh embodiment of this application. Figure 22 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0130] Step 8001: Place the second circuit frame layer 1b above the first circuit frame layer 1a; wherein, both the first circuit frame layer 1a and the second circuit frame layer 1b are partially etched circuit frames.

[0131] Step 8002: The second circuit frame layer 1b is fixedly connected to the first circuit frame layer 1a above the solder layer 3;

[0132] Step 8003: Use molding material 2 to fill the space between the first circuit frame layer 1a and the second circuit frame layer 1b;

[0133] Step 8004: Etch the first circuit frame layer 1a and the second circuit frame layer 1b, forming second grooves 12 on the lower surface of the first circuit frame layer 1a and the upper surface of the second circuit frame layer 1b, respectively; and

[0134] Step 8005: Etch the first circuit frame layer 1a and form a first groove 13 at the lower surface edge of the first circuit frame layer 1a; place the chip 4 on the second circuit frame layer 1b, with the active surface 41 of the chip 4 facing the second circuit frame layer 1b, and the chip 4 electrically connected to the second circuit frame layer 1b through an electrical connector 42; and use a molding material 2 to cover the chip 4 and the upper surface of the second circuit frame layer 1b.

[0135] Figure 23 A side view schematic diagram of the packaging structure according to the twelfth embodiment of this application is shown. Figure 23 As shown, in the stacked circuit frame layer 1, the bottommost circuit frame layer 1 has a first groove 13 on its side near the bottom surface.

[0136] In some alternative embodiments, the packaging structure provided according to one embodiment of the present application further includes an insulating layer, two adjacent circuit frame layers 1 are connected to each other by an insulating layer or a solder layer 3, and the molding material 2 covers the side of the solder layer 3.

[0137] Figure 24 It shows the use of, as Figure 23 The diagram shows a manufacturing process schematic of the packaging structure according to the twelfth embodiment of this application. Figure 24 As shown, the manufacturing process of its packaging structure includes, for example, Figure 22 Step 8001 shown refers to step 8004, and then the following steps are performed:

[0138] Step 8006: Chip 4 and third frame layer 1c are disposed on the second circuit frame layer 1b. The third frame layer 1c covers the chip 4. The active surface 41 of chip 4 faces the second circuit frame layer 1b. Chip 4 is electrically connected to the second circuit frame layer 1b through electrical connector 42. The third frame layer 1c is fixedly connected to the second frame layer 1b through an insulating layer.

[0139] Step 8007: Fill the space between the third circuit frame layer 1c and the second circuit frame layer 1b with the molding compound 2 and cover the upper surface of the third circuit frame layer 1c; and

[0140] Step 8008: Etch the first circuit frame layer 1a and form a first groove 13 at the lower surface edge of the first circuit frame layer 1a.

[0141] Figure 25 A side view schematic diagram of the packaging structure according to the thirteenth embodiment of this application is shown. Figure 25 In the stacked circuit frame layer 1 shown, the top of the uppermost circuit frame layer 1 protrudes from the top of the molding material 2.

[0142] In some alternative embodiments, according to the above-described embodiment of the present application, the encapsulation material 2 is provided with a through hole 21, which connects the groove 12 of the upper circuit frame layer 1 and the groove 12 of the lower circuit frame layer 1.

[0143] Figure 26 It shows the use of, as Figure 25 The diagram shown illustrates the manufacturing process of the packaging structure according to the thirteenth embodiment of this application. Figure 26 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0144] Step 9001: Provide a second circuit frame layer 1b, on which chip 4 is disposed. The second circuit frame layer 1b is a partially etched circuit frame; wherein...

[0145] Step 9002: Flip the second line frame layer 1b and place the second line frame layer 1b on the first line frame layer 1a;

[0146] Step 9003: The second circuit frame layer 1b is fixedly connected to the first circuit frame layer 1a above the solder layer 3; wherein, the active surface 41 of the chip 4 faces the first circuit frame layer 1a, and the electrical connector 42 of the chip 4 is electrically connected to the first circuit frame layer 1a through the solder layer 3.

[0147] Step 9004: Fill the space between the first circuit frame layer 1a and the second circuit frame layer 1b using the molding compound 2; etch the second circuit frame layer 1b to form a second groove 12 on the upper surface of the second circuit frame layer 1b; and

[0148] Step 9005: Etch the first circuit frame layer 1a, form a second groove 12 on the lower surface of the first circuit frame layer 1a, and form a first groove 13 on the edge of the lower surface of the first circuit frame layer 1a; and make a second groove 12 on the mold sealing material 2 to connect the upper surface of the second circuit frame layer 1b with the lower surface of the first circuit frame layer 1a.

[0149] Figure 27 A side view schematic diagram of the packaging structure according to the fourteenth embodiment of this application is shown. Figure 27 As shown, the top of the uppermost circuit frame protrudes from the top of the molded material 2.

[0150] Figure 28 It shows the use of, as Figure 27 The diagram shown illustrates the manufacturing process of the packaging structure according to the fourteenth embodiment of this application. Figure 28 As shown, the manufacturing process of the packaging structure includes multiple steps:

[0151] Step 10001: Provide a second circuit frame layer 1b, on which chip 4 is disposed. The second circuit frame layer 1b is a partially etched circuit frame; wherein...

[0152] Step 10002: Flip the second line frame layer 1b and place the second line frame layer 1b on the first line frame layer 1a;

[0153] Step 10003: The second circuit frame layer 1b is fixedly connected to the first circuit frame layer 1a above the solder layer 3; wherein, the active surface 41 of the chip 4 faces the first circuit frame layer 1a, and the electrical connector 42 of the chip 4 is electrically connected to the first circuit frame layer 1a through the solder layer 3.

[0154] Step 10004: Fill the space between the first circuit frame layer 1a and the second circuit frame layer 1b using molding compound 2; etch the second circuit frame layer 1b to form a second groove 12 on the upper surface of the second circuit frame layer 1b; and

[0155] Step 10005: Etch the first circuit frame layer 1a, form a second groove 12 on the lower surface of the first circuit frame layer 1a, and form a first groove 13 at the edge of the lower surface of the first circuit frame layer 1a.

[0156] The advantages of the packaging structure according to the embodiments of this application are: the use of a circuit frame layer to replace the electroplated circuit improves the structural strength, conductivity and heat dissipation of the packaging structure; it is less prone to deformation during the manufacturing process, thus improving product yield; it eliminates the need for an electroplating process, reducing production costs and improving product reliability; the circuit frame layer protruding downwards from the bottom of the molding material improves the heat dissipation performance of the packaging structure; and it improves the working stability of the packaging structure in high-temperature environments.

[0157] Although this application has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not intended to limit the application. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the scope of protection of this application as defined by the claims. Differences may exist between the technical representation in this application and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this application may exist that are not specifically described. The specification and illustrations should be considered illustrative rather than restrictive, and modifications can be made to suit the purpose and spirit of this application, all of which are within the scope of the claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be rearranged, subdivided, or arranged to form equivalent methods without departing from the teachings of this application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the application.

Claims

1. A packaging structure, characterized in that, include: At least two layers of circuit frame layers, which are stacked vertically; A molding compound, which is filled into the space within the circuit frame layer and between the circuit frame layers; Solder layer, the upper and lower adjacent circuit frame layers are fixedly connected by solder layer, the molding material covers the side of the solder layer; At least one electronic component is disposed between or above the circuit frame layers, and the molding compound covers the electronic component. The bottom of the circuit frame layer located at the bottom of the packaging structure protrudes from the mold material, and the protruding circuit frame layer forms a patterned circuit layer, which includes at least one independent circuit.

2. The packaging structure according to claim 1, characterized in that, The electronic components include chips and / or passive components.

3. The packaging structure according to claim 2, characterized in that, The chip includes a first electrical connector, and the chip is electrically connected to the circuit frame layer through the first electrical connector.

4. The packaging structure according to claim 2, characterized in that, The packaging structure also includes wire bonding, through which the chip is electrically connected to the circuit frame layer.

5. The packaging structure according to claim 2, characterized in that, The chips are stacked on top of each other.

6. The packaging structure according to claim 2, characterized in that, The packaging structure also includes an insulating layer, and two adjacent circuit frame layers are connected to each other through an insulating layer or a solder layer, with the molding material covering the side of the solder layer.

7. The packaging structure according to claim 1, characterized in that, At least a portion of the side of the circuit frame layer is exposed from the side of the molding material.

8. The packaging structure according to claim 1, characterized in that, In the stacked circuit frame layers, the top of the uppermost circuit frame layer protrudes from the top of the molding compound.

9. The packaging structure according to claim 1, characterized in that, In the stacked circuit frame layers, the bottommost circuit frame layer has a first groove on its side near the bottom surface.

10. The packaging structure according to claim 2, characterized in that, The passive components are resistors, inductors, capacitors, filters, diodes, or fuses.

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