Semiconductor package

Abstract

Embodiments of the present application provide a semiconductor package including side-by-side first and second dies, an encapsulation laterally covering the first and second dies, and an interconnect structure underlying the encapsulation. Each of the first and second dies includes a front side and a back side opposite to each other. The second die further includes an optical interface at the back side, and a top surface of the back side and the optical interface of the second die are exposed by the encapsulation. The interconnect structure is connected to the front sides of the first and second dies, and the second die is electrically coupled to the first die through the interconnect structure. A circuit die including an optical path is protected by the encapsulation to provide better reliability, and damage to the optical path of the die due to a grinding process is eliminated.

Description

Technical Field

[0001] Embodiments of this utility model relate to a semiconductor package, and more particularly to a semiconductor package including a photonic integrated circuit and an electronic integrated circuit. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration of various semiconductor components, such as transistors, diodes, resistors, and capacitors. To a large extent, these improvements in integration stem from the continuous reduction in the smallest feature size, allowing more semiconductor components to be integrated into a given area. As the demand for miniaturized semiconductor components continues to grow, a trend has emerged towards smaller and more innovative semiconductor die packaging technologies. While existing semiconductor packages and manufacturing methods are generally sufficient to meet their intended purposes, they are not entirely satisfactory in all aspects. Utility Model Content

[0003] An embodiment of this utility model provides a semiconductor package including a first die and a second die arranged side by side, an encapsulation body laterally covering the first die and the second die, and an interconnect structure. Each of the first die and the second die includes a front side and a back side opposite to each other. The second die also includes an optical interface on the back side. The top surface of the back side of the second die and the optical interface are exposed by the encapsulation body. The interconnect structure lies under the encapsulation body and is connected to the front side of the first die and the second die. The second die is electrically coupled to the first die through the interconnect structure.

[0004] An embodiment of this utility model provides a semiconductor package including a first die, a second die laterally disposed next to the first die, an interconnect structure, and an encapsulation body. The first die includes a front side, a back side opposite to the front side, and a sidewall connected to the front side and the back side. The second die includes a photonic integrated circuit, an electronic integrated circuit disposed on and bonded to the photonic integrated circuit, a dielectric layer disposed on the photonic integrated circuit and covering the electronic integrated circuit, and an optical component disposed on the electronic integrated circuit and the dielectric layer. The optical component includes an optical interface on the side opposite to the dielectric layer, and the height of the second die is less than the height of the first die. The interconnect structure connects the front side of the first die and the photonic integrated circuit of the second die. The second die is electrically coupled to the first die through the interconnect structure. The encapsulation body is disposed on the interconnect structure and extends along the sidewalls of the first die and the second die. The encapsulation body includes an opening exposing the optical interface and an upper inner sidewall surrounding the opening.

[0005] Based on the above, in embodiments of this invention, the integrated circuit die of the semiconductor package is laterally encapsulated by an insulating encapsulator without damaging the optical path of the integrated circuit die. During the formation of the insulating encapsulator, a sacrificial film covers the optical path of the integrated circuit die, and the sacrificial film can then be removed after the insulating encapsulator is formed to expose the optical path of the integrated circuit die. Alternatively, the optical path of the integrated circuit die can be exposed by the insulating encapsulator using a suitable removal process to prevent damage to the optical path during the polishing process. In this way, the integrated circuit die, including the optical path, is protected by the insulating encapsulator to provide better reliability and eliminate damage to the optical path of the integrated circuit die due to the polishing process.

[0006] To make the above features and advantages of the embodiments of this utility model more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1A , Figure 1B and Figure 1C This is a schematic cross-sectional view showing different types of integrated circuit (IC) dies according to some embodiments.

[0008] Figure 1D This illustrates some embodiments. Figure 1C A schematic top view of the IC die shown.

[0009] Figures 2A-2B and Figure 2E-Figure 2I This is a schematic cross-sectional view of a method for manufacturing a semiconductor package at various stages according to some embodiments.

[0010] Figures 2C-2D This illustrates some embodiments. Figure 2B Schematic top view of different configurations of the structure shown.

[0011] Figure 3 This illustrates coupling to an optical signal port according to some embodiments. Figure 2I A schematic cross-sectional view of a semiconductor package.

[0012] Figures 4A-4D This is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor package at various stages according to some embodiments.

[0013] Figures 5-6 This is a schematic cross-sectional view showing a semiconductor package according to an alternative embodiment.

[0014] Figure 7This is a flowchart illustrating a method for forming a semiconductor package according to some embodiments.

[0015] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numerals generally denote identical, functionally similar, and / or structurally similar devices. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of this utility model. Specific examples of components and arrangements are described below to simplify this utility model. Of course, these are merely examples and are not intended to limit the scope of this utility model. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples. Such repetition is for simplification and clarity in describing this utility model, and is not intended to limit the relationship between various embodiments and / or configurations.

[0017] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations illustrated in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein may be interpreted in the same manner. Unless otherwise explicitly stated, each component with the same reference numerals is assumed to have the same material composition and thickness within the same thickness range.

[0018] Currently, semiconductor dies, including photonic integrated circuits (PICs) and electronic integrated circuits (EICs), are becoming increasingly popular due to their compactness. Furthermore, optical signal processing is also gaining more traction due to the widespread use of fiber optic applications for signal transmission. Embodiments of this invention provide a novel method for forming a semiconductor package and its structure, wherein the semiconductor package includes an integrated circuit (IC) die comprising a PIC bonded to an EIC, and the IC die is laterally encapsulated by an insulating encapsulation without damaging the optical path of the IC die. During the formation of the insulating encapsulation, a sacrificial film covers the optical path of the IC die, and the sacrificial film can then be removed after the insulating encapsulation is formed to expose the optical path of the IC die. Alternatively, the optical path of the IC die can be exposed by the insulating encapsulation using a suitable removal process to prevent damage to the optical path during polishing processes. In this manner, the IC die including the optical path is protected by the insulating encapsulation to provide better reliability and eliminate damage to the optical path of the IC die due to polishing processes. In addition, IC dies, including PIC and EIC, can be electrically coupled to one or more IC dies using short electrical signal paths, thereby improving signal performance and increasing data transmission rates.

[0019] According to some embodiments, Figure 1A , Figure 1B and Figure 1C It is a schematic cross-sectional view showing different types of IC dies, and Figure 1D It is shown Figure 1C A schematic top view of the IC die shown. (Reference) Figure 1AIC die 110 may be provided. IC die 110 may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management die (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, sensor die, micro-electro-mechanical system (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front-end (AFE) die), or similar combinations thereof.

[0020] Continue to refer to Figure 1A IC die 110 can be formed in a semiconductor wafer, which may include different device regions that are monomerized to form multiple IC dies 110. IC die 110 can be processed according to applicable manufacturing processes to form an integrated circuit. For example, IC die 110 includes a semiconductor substrate 111, such as an active layer of doped or undoped silicon or a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 111 may include other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. IC die 110 may include active devices (e.g., transistors, diodes, etc.), passive devices (e.g., capacitors, resistors, inductors, etc.), and combinations thereof. These active / passive devices (not shown separately) can be formed on the front side of the semiconductor substrate 111 using a suitable front-end-of-line (FEOL) process.

[0021] Still referencing Figure 1A The IC die 110 may include an interconnect structure 116 formed above a semiconductor substrate 111 and interconnected with active and / or passive devices to form an integrated circuit. For example, the interconnect structure 116 is formed by metallization patterns 1161 in one or more dielectric layers 1162. The metallization patterns 1161 include metal pads, metal lines, and metal vias formed in the dielectric layer 1162 and electrically coupled to active and / or passive devices. The interconnect structure 116 may include contact pads 1163 formed on the dielectric layer 1162 and electrically coupled to the metallization patterns 1161. The IC die 110 may include die connectors 117 formed on the contact pads 1163. One side of the IC die 110 with the die connectors 117 distributed thereon can be considered the active side of the IC die 110. The die connector 117 may be formed of a solderable conductive material (e.g., solder), or may include other suitable conductive materials such as copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the die connector 117 is referred to as a microbump. The above examples are for illustrative purposes only, and other embodiments may utilize additional components. In some embodiments, the IC die 110 is subjected to chip probe (CP) testing to determine whether the IC die 110 is a known good die (KGD). Therefore, only KGD IC dies 110 are subsequently processed and packaged, while other dies that fail the CP test are not packaged.

[0022] refer to Figure 1BAn IC die 120 may be provided. For example, the IC die 120 is a memory device, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like comprising multiple memory dies. In some embodiments, the IC die 120 includes multiple layers stacked and bonded to each other. Each layer of the IC die 120 may include a semiconductor substrate 122, a through-substrate via (TSV) 123 formed in the semiconductor substrate 122, a bonding layer 124 formed over one side (e.g., the front side) of the semiconductor substrate 122, and a selective bonding layer 125 formed over the opposite side (e.g., the back side) of the semiconductor substrate 122. The material of the semiconductor substrate 122 may be selected from candidate substrate materials of the semiconductor substrate 111. Each bonding layer (124 and 125) may include bonding pads (124P and 125P) laterally covered by bonding dielectric layers (e.g., 124D and 125D). The bonding pad 124P of the upper layer can be bonded to the bonding pad 125P of the lower layer in a one-to-one manner. The bonding dielectric layer 124D of the upper layer can be fused with the bonding dielectric layer 125D of the lower layer.

[0023] Continue to refer to Figure 1B The bottommost layer 120B of the IC die 120 may have a lateral dimension larger than the lateral dimension of any layer stacked above the bottommost layer 120B. In some embodiments, an encapsulation 121 is disposed on the bottommost layer 120B and laterally covers multiple layers stacked above the bottommost layer 120B. The IC die 120 may include die connectors 127 formed below the bottommost layer 120B and electrically connected to a bonding layer 124. One side of the IC die 120 with die connectors 127 distributed thereon may be considered the active side of the IC die 120. Die connectors 127 may be formed of a reflowable conductive material (e.g., solder) or may include one or more conductive materials, such as copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. The above examples are for illustrative purposes only, and other embodiments may utilize additional components. CP testing may be performed on the IC die 120 to determine whether the IC die 120 is KGD. Therefore, only KGD's IC die 120 is processed and packaged, while other dies that fail the CP test are not packaged.

[0024] refer to Figure 1C The IC die 130 may be provided with a sacrificial film 31. In an alternative embodiment, the IC die 130 is not provided with the sacrificial film 31 (see [link to documentation]). Figure 4AAccording to some embodiments, the sacrificial film 31 can be considered sacrificial because it will eventually be removed. The material of the sacrificial film 31 may include any suitable polymer material, which can be removed, for example, by dissolving the sacrificial film 31 in a suitable solvent, etching the sacrificial film 31 using a suitable chemical solution, etc.

[0025] In some embodiments, IC die 130 is an optical-engine (OE) die including an EIC 134 stacked and bonded to PIC 132. In some embodiments, EIC 134 exchanges electrical signals with PIC 132. PIC 132 can convert the electrical signals from EIC 134 into optical signals. For example, PIC 132 includes a substrate 1321, a through substrate via (TSV) 1322 through the substrate 1321, a bonding layer 1323 disposed on the substrate 1321, an optional wiring layer 1324 interposed between the substrate 1321 and the bonding layer 1323 to electrically couple the bonding layer 1323 to the TSV 1322, and a contact pad 1325 formed under the substrate 1321 and electrically coupled to the TSV 1322. PIC 132 may include one or more optical components 1326 for processing, receiving, and / or transmitting optical signals, wherein the optical components 1321 may include photodiodes or photosensors, couplers, waveguides, laser sources, modulators, the like, combinations thereof, etc. The optical components 1321 may be formed in / on a substrate 1321 and may be partially or completely covered by wiring layers 1324 and / or bonding layers 1323.

[0026] Continue to refer to Figure 1C EIC 134 may include a substrate 1341 and a bonding layer 1343. The substrate 1341 includes a front side 1341a and a back side 1341b opposite to the front side 1341a. The bonding layer 1343 is disposed above the front side 1341a of the substrate 1341 and is physically and electrically coupled to the bonding layer 1323 of the PIC 132. EIC 134 may include active and / or passive devices (not shown separately) formed in / on the substrate 1341 to form functional circuitry for processing electrical signals converted from optical signals in the PIC 132, and the bonding layer 1343 may be electrically coupled to these active and / or passive devices. The bonding layers (1323 and 1343) may each include bonding pads (e.g., 132P, 134P) laterally covered by bonding dielectric layers (e.g., 132D, 134D). The bonding pad 132P of PIC 132 can be bonded to the bonding pad 134P of EIC 134 in a one-to-one manner. The bonding dielectric layer 132D of PIC 132 can be melted to the bonding dielectric layer 134D of EIC 134.

[0027] Continue to refer to Figure 1C The lateral dimension of PIC 132 may be larger than the lateral dimension of EIC 134. A dielectric layer 136 may be formed on PIC 132 and extend along a first sidewall 134W of EIC 134. In some embodiments, dielectric layer 136 further covers the back side 1341b of EIC 134. The material of dielectric layer 136 is not particularly limited and may be selected based on its refractive index. Dielectric layer 136 may be transparent to light radiation in the target wavelength range. For example, dielectric layer 136 comprises an inorganic material, such as an oxide (e.g., silicon oxide), a nitride, a carbide, or the like. Dielectric layer 136 may include a first side 136a connected to a bonding dielectric layer 132D of PIC 132, a second side 136b opposite to the first side 136a, and an outer sidewall 136W connected to the first side 136a and the second side 136b. In some embodiments, dielectric layer 136 is referred to as a gap-filling oxide.

[0028] Still referencing Figure 1CThe IC die 130 may include an optical assembly 131 stacked above the EIC 134 and the dielectric layer 136. For example, the optical assembly 131 includes a first side 131a bonded to the dielectric layer 136, a second side 131b opposite to the first side 131a, an optical interface 131L formed on the second side 131b and optically aligned (or optically coupled) to an optical component 1326 of the PIC 132, and opposing outer sidewalls (131W and 131X) respectively connected to the first side 131a and the second side 131b. In some embodiments, the optical assembly 131 includes a substrate 1311 and a bonding dielectric layer 1312 formed on the first side 131a of the optical assembly 131 and bonding the substrate 1311 to the second side 136b of the dielectric layer 136. For example, the bonding dielectric layer 1312 and the dielectric layer 136 are bonded together by fusion bonding. The optical interface 131L may be recessed from the topmost surface 1311t of the substrate 1311. In some embodiments, the optical interface 131L is a convex surface serving as a lens. For example, the apex 131LT of the optical interface 131L is located between the apex of the second side 131b and the first side 131a. The vertical distance VD1 measured between the apex 131LT of the optical interface 131L and the virtual plane VP1 containing the apex of the second side 131b of the substrate 1311 may be non-zero. In some embodiments, the maximum thickness 131H of the optical component 131 is greater than the maximum thickness 13H of the combination of dielectric layer 136, EIC 134, and PIC 132. For example, the ratio of the maximum thickness 131H to the maximum thickness 13H is in the range of about 24 to about 40. The maximum thickness 131H of the optical component 131 may be in the range of about 720 micrometers to about 800 micrometers. The maximum thickness 13H of the combination of dielectric layer 136, EIC 134, and PIC 132 may be in the range of about 20 micrometers to about 30 micrometers. It should be understood that the thickness range is an example and can be changed to other suitable values ​​according to product requirements.

[0029] Still referencing Figure 1CIn some embodiments, the IC die 130 includes a protective film 133 formed on a second side 131b of the optical component 131 and covering the optical interface 131L for protection. For example, the protective film 133 has a flat top surface 133t. The protective film 133 may be transparent to light radiation within a target wavelength range. For example, during operation, incident light passes through the protective film 133, the optical interface 131L of the optical component 131, the dielectric layer 136, and is directed towards the optical component 1326 of the PIC 132. The protective film 133, the optical interface 131L, and the dielectric layer 136 can be considered as part of the optical path of the IC die 130. The material of the protective film 133 is not particularly limited and can be selected based on its refractive index. For example, the protective film 133 includes inorganic materials such as oxides (e.g., silicon oxide), nitrides, carbides, or the like. The refractive index and thickness of the protective film 133 can be adjusted according to the refractive index of the optical interface 131L to meet the optical requirements of the IC die 130. The maximum thickness 133H of the protective film 133 can be less than the maximum thickness 13H and the maximum thickness 131H. For example, the ratio of the maximum thickness 13H to the maximum thickness 133H is in the range of about 2 to about 6. In some embodiments, the maximum thickness 133H of the protective film 133 is in the range of about 5 micrometers to about 10 micrometers. It should be understood that the thickness range is an example and can be changed to other suitable values ​​according to product requirements.

[0030] Continue to refer to Figure 1C Protective film 133 can be replaced by protective film 133'. Except that protective film 133' conformally lines the second side 131b of optical assembly 131 and optical interface 131L, protective film 133' may be similar to protective film 133. For example, protective film 133' has a curved top surface 133t' conformally lined on optical interface 131L. In alternative embodiments, the protective film (133 or 133') is omitted.

[0031] Still referencing Figure 1CAccording to some embodiments, the sacrificial film 31 may be formed on the protective film 133 (or 133'). Alternatively, the sacrificial film 31 may be formed directly on the second side 131b of the optical component 131 and the optical interface 131L, without any protective film inserted between them. During the formation of the IC die 130, the sacrificial film 31 may be attached to the back side of the IC die 130 and then monolithized together with the IC die 130. The first sidewall 31W of the sacrificial film 31 may be substantially flush (or coplanar) with the outer sidewall 131W of the optical component 131, the outer sidewall 136W of the dielectric layer 136, and the first sidewall 132W of the PIC 132 within the range of process variations. The second sidewall 31X of the sacrificial film 31 may be substantially flush (or coplanar) with the outer sidewall 131X of the optical component 131, the second sidewall 134X of the EIC 134, and the second sidewall 132X of the PIC 132 within the range of process variations.

[0032] refer to Figure 1D And refer to Figure 1C The optical interface 131L can be surrounded by the recess 131R. In Figure 1C In the cross-sectional view, the optical interface 131L can be a convex surface that is rounded or curved outward from the bottom surface 131RB of the recess 131R. A protective film 133 can extend into the recess 131R to surround the optical interface 131L. Figure 1D In the top view, the optical interface 131L may have a circular top view shape, and the recess 131R may be formed as a dead loop around the periphery of the optical interface 131L. Alternatively, the optical interface 131L and / or the recess 131R may have a different top view shape than shown. In some embodiments, a plurality of optical interfaces (e.g., lenses) 131L are arranged in an array above the PIC 132. In some embodiments, the number of optical interfaces (e.g., lenses) 131L is in the range of about 20 to about 24. It should be noted that the dimensions, number, and configuration of the PIC 132 and / or EIC 134 and / or optical components 131 are shown for illustrative purposes only. It is also worth noting that... Figure 1D The protective film 133 and the sacrificial film 31 are omitted to show the details of the optical component 131 more clearly.

[0033] Return to reference Figure 1CThe IC die 130 may include a die connector 137 formed beneath the contact pad 1325 of the PIC 132 and electrically connected to the TSV 1322. The side of the IC die 130 with the die connector 137 distributed thereon can be considered the active side of the IC die 130. The die connector 137 may be formed of a reflowable conductive material (e.g., solder) or include one or more suitable conductive materials, such as copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. The IC die 130 may be subjected to a CP test to determine whether the IC die 130 is a KGD (knock-down die). Therefore, only KGD IC dies 130 are subsequently processed and packaged, while other dies that fail the CP test are not packaged. It should be noted that the configuration of the IC die 130 may differ from that shown.

[0034] According to some embodiments, Figures 2A-2B and Figure 2E-Figure 2I Yes, this is a schematic cross-sectional view of the manufacturing process of a semiconductor package at various stages, and Figures 2C-2D It is shown Figure 2B The diagram shows schematic top views of different configurations of the structure. While the method embodiments are discussed as being performed in a specific order, other embodiments may be performed in any logical order.

[0035] refer to Figure 2A And refer to Figures 1A-1C One or more IC dies (e.g., 110, 120, and 130) may be disposed on and electrically coupled to the intermediate 140', wherein the IC dies may include similar devices and / or different devices. For example, the embodiments shown herein include IC dies 110, 120, and 130, wherein IC die 130, including the optical interface 131L, may have a different function than IC dies 110 and 120. At this stage, IC die 130 may remain covered by the sacrificial film 31. IC dies 110 and 120 may each have a single function (e.g., a logic device, a memory die, etc.) or may have multiple functions (e.g., a system-on-a-chip, etc.). In one embodiment, IC die 110 is a logic device (e.g., a CPU die or a SoC die) and IC die 120 is a memory device (e.g., an HBM module). The lateral distance LD1 between two adjacent sidewalls (e.g., 110c and 120c or 110c and 130c) of an IC die (e.g., 110 and 120 or 110c and 130c) can be non-zero. For example, the lateral distance LD1 is in the range of approximately 50 μm to approximately 100 μm. In some embodiments, the height 130H of IC die 130 is less than the height 110H of IC die 110. The height 130H of IC die 130 may also be less than the height 120H of IC die 120. It should be understood that the distance range and height are merely examples and may be changed to other suitable values ​​depending on product requirements.

[0036] Continue to refer to Figure 2A The intermediate 140' may include a substrate 142, a through substrate via (TSV) 144, and an interconnect structure 146. The material of the substrate 142 may be from... Figure 1A The semiconductor substrate 111 is selected from candidate substrate materials. Devices (e.g., transistors, capacitors, resistors, diodes, etc.) may be formed in and / or on the front side 142a of the substrate 142. A TSV 144 may be formed extending from the front side 142a of the substrate 142 into the substrate 142. At this stage, the TSV 144 may not reach the back side 142b of the substrate 142. An interconnect structure 146 may be formed on the front side 142a of the substrate 142 and may be used to form electrical connections between devices (if any) on the substrate 142 and the TSV 144 and / or external devices. The interconnect structure 146 may include a dielectric layer 1461 and a metallization pattern 1462 formed in the dielectric layer 1461. The metallization pattern 1462 may be a redistribution layer (RDL) that includes metal vias, metal pads, and / or metal lines forming electrical connections. In some embodiments, the interconnect structure 146 is referred to as a redistribution structure or a fan-out redistribution structure. Intermediate 140' may include contact pads 1463 of die connectors (e.g., 117, 127, and 137) disposed on the interconnect structure 146 and coupled to IC dies (e.g., 110, 120, and 130). IC dies (e.g., 110, 120, and 130) may be electrically connected to each other via the interconnect structure 146 and contact pads 1463. In some embodiments, IC die 130 has one or more associated IC dies 110 and / or 120, which may be electrically connected to IC die 130 (e.g., via the interconnect structure 146 and contact pads 1463).

[0037] refer to Figure 2B And refer to Figure 2AAn underfill layer 151 may be formed on the interposer 140' to at least surround an electrical connection between the IC die (e.g., 110, 120, and 130) and the interposer 140' (e.g., contact pad 1463 and die connectors (e.g., 117, 127, and 137)). The underfill layer 151 may be any acceptable material, such as polymers, epoxy resins, etc., and may be formed by capillary flow processes or other suitable dispensing techniques. In some embodiments, the underfill layer 151 is omitted. Encapsulation material 152 An encapsulation material 152' may be formed on the interposer 140 to embed the IC die (e.g., 110, 120, and 130) and the underfill layer 151 (if present). For example, an encapsulation material 152' is formed on the interconnect structure 146, and the IC die (e.g., 110, 120, and 130) and the underfill layer 151 (if present) are surrounded and covered by the encapsulation material 152'. In some embodiments, a sacrificial film 31 on the IC die 130 may be embedded into the encapsulation material 152' at this stage.

[0038] Continue to refer to Figure 2B The encapsulation material 152' may be or include molding compounds, epoxy resins, etc., and can be coated by compression molding, transfer molding, etc. The encapsulation material 152' may include a substrate 152M (e.g., a polymer, epoxy resin, etc.) and a filler 152F in the substrate 152M. The filler 152F may include dielectric particles such as silicon oxide, alumina, and silica, and may have a spherical shape. The spherical filler 152F may have the same diameter or different diameters. In some embodiments, the encapsulation material 152' is coated in a liquid or semi-liquid form and then cured. In embodiments where the underfill layer 151 is omitted, the encapsulation material 152' is a molded underfill that extends into the gap between the respective IC dies (e.g., 110, 120, and 130) and the intermediary 140' to surround the contact pad 1463 and the die connector (e.g., 117, 127, and 137).

[0039] refer to Figure 2C And refer to Figure 2B , Figure 2B It can be along Figure 2CA cross-sectional view of the structure taken along line 2B-2B. In the top view, IC die 110 may be disposed in the central region, while IC dies (120 and 130) may be disposed in the peripheral regions and sides of IC die 110. Although a single IC die 110 is shown, the number of IC dies 110 may be two or more, depending on product requirements. For example, a plurality of IC dies 120 may be arranged in a row along one side of IC die 110, and a plurality of IC dies 130 may be arranged in a row along the opposite side of IC die 110. In some embodiments, IC dies 120 and 130 may be arranged in a row along one side of IC die 110. In some embodiments, one or more dies 90 may be disposed in a blank area in the encapsulation material 152'. Depending on product requirements, dies 90 may have the same size or may include different sizes. In some embodiments, dies 90 may include dummy dies, and including dummy dies may improve the warpage characteristics of the resulting package. When one or more dummy dies are included, the resulting package may experience less warpage and / or more symmetrical warpage. In some embodiments, die 90 includes input / output dies electrically coupled to intermediate 140' according to circuit and product requirements.

[0040] refer to Figure 2D And refer to Figure 2C In addition to the IC dies (120 and 130) being arranged on all (e.g., four) sides of IC die 110, Figure 2D The configuration can be similar to Figure 2C The configuration is as follows. Although a single IC die 110 is shown, the number of IC dies 110 may be two or more, depending on product requirements. For example, IC dies 120 may be arranged in rows on two opposite sides of IC die 110, while IC dies 130 may be arranged in rows on another two opposite sides of IC die 110. One or more dies 90 may be arranged at the corner between IC dies (120 and 130) and may be covered by encapsulation material 152'. It should be understood that these configurations are examples, and other configurations or arrangements are possible.

[0041] refer to Figure 2E And refer to Figure 2BThinning processes (e.g., chemical-mechanical polishing (CMP), grinding, etching, or combinations thereof) can be performed on the back side 142b of the substrate 142 of the intermediate 140' until at least a portion of the TSV 144 is tangibly exposed to form the intermediate 140. In some embodiments, the thinned surface 142b' and the exposed surface 144b of the substrate 142 of the TSV 144 are substantially flush (or coplanar) within process variations. In some embodiments, the intermediate 140 includes contact pads 147 formed on the thinned surface 142b' of the substrate 142 and electrically connected to the exposed surface 144b of the TSV 144. In some embodiments, conductive bumps 148 are formed on the contact pads 147. The conductive bumps 148 may be formed of a resolderable conductive material (e.g., solder) or may include other suitable conductive materials such as copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. The conductive bump 148 can be a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, or a bump formed using electroless nickel-electroless palladium-immersion gold (ENEPIG) technology. During the thinning process and the formation of the contact pad 147 and the conductive bump 148, the encapsulation material 152' can serve as a structural support, and the sacrificial film 31 can remain embedded in the encapsulation material 152' during this stage.

[0042] refer to Figure 2F And refer to Figure 2EConductive bumps 148 may be attached to support strip 41. For example, conductive bumps 148 (and contact pads 147, if desired) are embedded in support strip 41. Support strip 41 may be provided in wafer form for performing wafer-level packaging processes. In some embodiments, a thinning process (e.g., CMP, polishing, etching, or combinations thereof) is performed on encapsulation material 152' to form encapsulation 152. As shown in the enlarged view, a portion of filler 152F at the top surface 152b of encapsulation 152 may be planarized and exposed in an accessible manner by substrate 152M. Planarized filler 152F' may make the top surface 152b non-uniform. During the thinning of encapsulation material 152', support strip 41 may act as a support. In some embodiments, after thinning of encapsulation material 152', sacrificial film 31 may be exposed in an accessible manner by encapsulation 152 for further processing. The back side (e.g., 110b and 120b) of the IC die (e.g., 110 and 120) can also be exposed in an accessible manner by the encapsulation 152. The thinning process can planarize the structure so that the top surface 152b of the encapsulation 152 is substantially flush (or coplanar) with the back side (e.g., 110b and 120b) of the IC die (e.g., 110 and 120) within the process variation.

[0043] refer to Figure 2G And refer to Figure 2F The sacrificial film 31 can be removed to expose the IC die 130. For example, after removing the sacrificial film 31, the protective film 133 of the IC die 130 is exposed in an accessible manner. Removal of the sacrificial film 31 may include applying appropriate light irradiation (e.g., ultraviolet (UV) light, laser irradiation, etc.) to the sacrificial film 31, followed by dissolving the sacrificial film 31 with appropriate water / solvent. Exposure to light can cause a chemical change that makes the sacrificial film 31 soluble in a suitable solvent. The sacrificial film 31 can be dissolved by rinsing, washing, or soaking with water or a solvent, depending on the material properties of the sacrificial film 31. In some embodiments, the sacrificial film 31 is removed by applying a solution (e.g., an alkaline solution or the like) instead of light irradiation. For example, the sacrificial film 31 is soluble in deionized water, isopropanol, acetone, alkaline solutions, and / or the like. In some embodiments, hot water is used to remove the sacrificial film 31, wherein the expected temperature of the hot water is about 25°C to about 60°C. It should be understood that the method for removing the sacrificial membrane 31 depends on the properties of the material selected for the sacrificial membrane 31, and is not a limitation in this invention.

[0044] Continue to refer to Figure 2GAfter the sacrificial membrane 31 is removed, the inner sidewall 152c of the encapsulation 152, connected to the top surface 152b, can be exposed in an accessible manner. The surface roughness of the top surface 152b of the encapsulation 152 may be greater than the surface roughness of the inner sidewall 152c of the encapsulation 152. The surface roughness of the inner sidewall 152c of the encapsulation 152 may be greater than the surface roughness of the outermost surface 133b of the protective membrane 133. In some embodiments, the inner sidewall 152c of the encapsulation 152 is substantially vertical (or slightly inclined according to the profile of the sacrificial membrane). The outermost surface 133b of the protective membrane 133 may be lower than the top surface 152b of the encapsulation 152, and the vertical distance between the outermost surfaces 133b of the protective membrane 133 may be substantially equal to the height of the inner sidewall 152c of the encapsulation 152.

[0045] refer to Figure 2H And refer to Figure 2G Flipable Figure 2G The structure shown is attached to the frame 43 for further processing. Since the sacrificial film 31 on the IC die 130 has been removed, the outermost surface 133b of the protective film 133 can contact the frame 43. The support strip 41 can be removed from the intermediate 140 to expose the conductive bumps 148 and contact pads 147 in an accessible manner. In some embodiments where the above process is performed at the wafer level, a monomerization process S43 is performed to cleave the intermediate 140 and the encapsulation 152 to form a plurality of device packages 100. The frame 43 can serve as a support during the monomerization process S43 and is therefore referred to as a cleaving frame.

[0046] refer to Figure 2I And refer to Figure 2HOne or more device packages 100 may be attached to a package substrate 220 to form a semiconductor package 10. The semiconductor package 10 may be considered a three-dimensional integrated circuit (3DIC) package. In some embodiments, the semiconductor package 10 is referred to as a chip-on-wafer-on-substrate (CoWoS) package. The package substrate 220 may be electrically connected to an IC die (e.g., 110, 120, and 130) via an intermediary 140. For example, the package substrate 220 includes a substrate core 222, which may be made of one or more semiconductor materials, one or more compound materials, the like, or combinations thereof. Alternatively, the substrate core 222 may be an insulating core (e.g., FR4, bismaleimide-triazine (BT) resin, etc.). In an alternative embodiment, the substrate core 222 is made of one or more printed circuit board materials, and the substrate core 222 may use a build-up film (e.g., Ajinomoto build-up film (ABF) or other laminated materials). The substrate core 222 may include active and / or passive devices (not shown separately) to produce functional requirements that meet the system design. The substrate core 222 may also include metallization layers and vias (not shown separately) to electrically connect various devices to form functional circuitry.

[0047] Continue to refer to Figure 2I The package substrate 220 may include bonding pads 224 formed above the substrate core 222. Conductive bumps 148 may be reflowed to connect contact pads 147 to the bonding pads 224. In some embodiments, an underfill layer 228 is formed between the device package 100 and the package substrate 220 to surround the conductive bumps 148, contact pads 147, and bonding pads 224. The underfill layer 228 may be formed by a capillary flow process after attaching the device package 100, or by any suitable deposition method before attaching the device package 100. The underfill layer 228 may be a continuous material extending from the package substrate 220 to the sidewalls of the interposer 140. In some embodiments, external terminals 226 are formed below the substrate core 222. The external terminals 226 may be ball grid array (BGA) connectors, solder balls, metal pillars, C4 bumps, microbumps, ENEPIG-formed bumps, or the like.

[0048] Still referencing Figure 2IIC die 130 (e.g., OE die) may be included in device package 100 and electrically coupled to other IC dies (e.g., 110 and / or 120) via interconnect structure 146 of intermediary 140. Interconnect structure 146 may be formed with fine linewidth / spacing to match the die connectivity density of the respective IC dies (e.g., 110, 120, and 130), thereby improving electrical / signal performance and enabling higher data transfer rates. Since IC die 130 (e.g., OE die) is integrated into device package 100 instead of using a wiring layer in package substrate 220, the signal bandwidth of semiconductor package 10 is no longer limited by substrate processing. When a thinning process is performed on encapsulation material 152' (see...), the signal bandwidth of semiconductor package 10 is no longer limited by substrate processing. Figure 2F Using a protective film 133 and a sacrificial film 31 covering the protective film 133, the optical interface 131L of the IC die 130 can be protected from grinding. After the thinning process, the sacrificial film 31 can be removed to expose the protective film 133. In this way, damage to the optical interface 131L of the IC die 130 can be prevented, and the sidewalls of the IC die 130 can remain protected by the encapsulation 150, thereby improving the reliability of the device package 100.

[0049] Figure 3 This illustrates coupling to an optical signal port according to some embodiments. Figure 2I A schematic cross-sectional view of a semiconductor package. (Reference) Figure 3 and Figure 2I Optical signal port 250 may be coupled to semiconductor package 10. For example, optical signal port 250 is attached to package substrate 220 and optically coupled to optical interface 131L of IC die 130. Optical signal port 250 may include at least one optical fiber 251 and an optical interface layer 252 disposed between optical fiber 251 and protective film 133 of IC die 130 for bonding optical fiber 251 to device package 100. Optical fiber 251 may be optically aligned with IC die 130 (e.g., OE die) to enable the exchange of optical signals between optical fiber 251 and optical components 1326 of PIC 132 via optical interface 131L. For example, optical fiber 251 is bonded to IC die 130 by coating optical interface layer 252 onto optical fiber 251 and protective film 133 of IC die 130. Optical interface layer 252 may include a clear (or transparent) adhesive or other suitable optical adhesive / grease. In some embodiments, the optical interface layer 252 is a refractive index-matching adhesive layer and can be refractively matched with the optical fiber 251 and the protective film 133 of the IC die 130 to the optical interface 131L to reduce optical loss. The refractive index and thickness of the optical interface layer 252 can be adjusted according to the refractive indices of the optical fiber 251, the protective film 133, and the optical interface 131L. It should be noted that the optical signal port 250 may have a different configuration than shown.

[0050] Figures 4A-4D This is a schematic cross-sectional view illustrating methods of manufacturing semiconductor packages at various stages according to some embodiments. Unless otherwise explicitly stated, the materials and forming methods of the components in these embodiments are substantially related to bonding. Figures 2A-2I Similar components in the described embodiments are indicated by similar reference numerals.

[0051] refer to Figure 4A And refer to Figure 2B ,Apart from Figure 4A Except for the sacrificial membrane 31, Figure 4A The structure shown can be similar to Figure 2B The structure shown. For example, IC die 130 (such as...) Figure 1C (As shown) no sacrificial film 31 is provided, and the IC die 130 is attached to the intermediary 140 (see...) Figure 2A After that, the back side of the IC die 130 can be exposed and facing upwards. After the encapsulation material 152' is formed, the outermost surface 133b of the protective film 133 of the IC die 130 can be covered by the encapsulation material 152'.

[0052] refer to Figure 4B And refer to Figure 4A and Figures 2E-2F A thinning process can be performed on the substrate 142 of the intermediate 140' until at least a portion of the TSV 144 is exposed in a tangible manner to form the intermediate 140 (see [link]). Figure 2E Contact pads 147 and conductive bumps 148 may be sequentially formed on the thinned surface 142b' of substrate 142 to be electrically coupled to TSV 144 (see...). Figure 2E Then, the conductive bump 148 can be attached to the support strip 41 for further processing (see...). Figure 2F Thinning processes can be performed on the encapsulation material 152' (see...). Figure 2F This process forms an encapsulation 152". After thinning, the back sides (e.g., 110b and 120b) of the IC dies (e.g., 110 and 120) can be exposed in an accessible manner by the encapsulation 152". The top surface 152b of the encapsulation 152" may be substantially flush (or coplanar) with the back sides (e.g., 110b and 120b) of the IC dies (e.g., 110 and 120) within the range of process variations. At this stage, the IC die 130 may not be exposed by the encapsulation 152". For example, the back side 1341b of the EIC 134 and the second side 136b of the dielectric layer 136 remain covered by the encapsulation 152" at this stage.

[0053] refer to Figure 4C And refer to Figure 4BA removal process S45 can be performed on the encapsulation 152” to form an encapsulation 152-1 with an opening 152P (or a hollow region), wherein at least a portion of the protective film 133 directly above the optical interface 131L is exposed in an accessible manner through the opening 152P. For example, the opening 152P is formed using a suitable process (e.g., laser drilling, etching, a combination thereof, or the like). In some embodiments, the etching process is a plasma etching (or plasma bombardment) process. For example, laser energy is applied to the encapsulation 152” to form the opening 152P”. After the laser drilling process, residues of the encapsulation 152” may be left on the IC die 130. In some embodiments, residues of the encapsulation 152” are removed by a plasma cleaning process, wherein a pad of process gas may be used to bombard the residues of the encapsulation 152”. Alternatively, residues of the encapsulation 152” can be removed by any suitable etching / cleaning process.

[0054] Continue to refer to Figure 4C After removal process S45, the inner sidewall 152c' of the encapsulation 152-1 connected to the top surface 152b can be exposed in an accessible manner. In some embodiments, during removal process S45, a portion of the substrate 152M and a portion of the filler 152F corresponding to the location of the opening 152P are removed. For example, the partially removed filler 152F" can be exposed in an accessible manner by the substrate 152M, as shown in the enlarged view. The partially removed filler 152F" can make the inner sidewall 152c' uneven. The surface roughness of the inner sidewall 152c' of the encapsulation 152-1 can be greater than the surface roughness of the top surface 152b of the encapsulation 152-1. The surface roughness of the top surface 152b of the encapsulation 152-1 can be greater than the surface roughness of the back side 1341b of EIC 134.

[0055] Still referencing Figure 4C The removal process S45 allows the upper inner wall c1 of the encapsulation 152-1 to be angled. In some embodiments, the upper inner wall c1 includes rounded corners connecting to the lower inner wall c2 and the top surface 152b. In some embodiments, at least a portion of the upper inner wall c1 is curved. For example, from... Figure 4CThe cross-sectional view shown shows a recessed surface profile. In some embodiments, the upper inner sidewall c1 with the recessed surface profile is considered as a curved portion 152CP. For example, the inner sidewall 152c' of the encapsulation 152-1 is substantially aligned with the sidewall 130c of the IC die 130. In some embodiments, a portion of the encapsulation 152" relative to the curved portion 152CP is removed, such that the top surface 152b' of the encapsulation 152-1 is lower than the top surface 152b, as shown in dashed box A. For example, the top surface 152b' of the encapsulation 152-1 is substantially flush with the outermost surface 133b of the protective film 133, as shown in dashed box A. In some embodiments, the opposite sides of the opening 152P defined by the encapsulation 152-1 are arranged in a substantially symmetrical manner, as shown in dashed box B. The opening 152P may have different dimensions than those shown, which will combine Figure 5 Let's have a discussion.

[0056] refer to Figure 4D And refer to Figure 4C and Figures 2H-2I The support strip 41 can be removed from the intermediary 140, and a monomerization process can be performed to cut the intermediary 140 and the encapsulation 152-1 to form multiple device packages 100-1. These steps can be combined with... Figure 2H The process described herein is similar, therefore, for simplicity, it will not be described in detail again. One or more device packages 100-1 may be attached to the package substrate 220 using conductive bumps 148. An underfill layer 228 is selectively formed between the device package 100-1 and the package substrate 220 to protect the electrical connection between them. The steps may be similar to those described herein. Figure 2I The process described herein will not be repeated in detail for the sake of simplicity.

[0057] Continue to refer to Figure 4D and Figure 2I It can provide semiconductor packages 20. Figure 4D The semiconductor package 20 shown and Figure 2I The differences between the semiconductor packages 10 shown include that the encapsulation material can directly contact the protective film 133 of the IC die 130, and then expose the protective film 133 of the IC die 130 by forming an opening 152P in the encapsulation material. The optical interface 131L of the IC die 130 can be protected from abrasion by the protective film 133, and the thinning of the encapsulation material is performed before the opening 152P of the encapsulation 152-1 is formed.

[0058] Figures 5-6 This is a schematic cross-sectional view illustrating a semiconductor package according to an alternative embodiment. Unless otherwise explicitly stated, the materials and methods of forming the components in these embodiments are substantially the same as those used in bonding. Figure 2I and Figure 4DSimilar components in the described embodiments are indicated by similar reference numerals.

[0059] refer to Figure 5 And refer to Figure 4D Except that the encapsulation 152-2 of the device package 100-2 extends to cover at least a portion of the back side of the IC die 130, the semiconductor package 30 may be similar to Figure 4D The semiconductor package 20 shown. The portion of the outermost surface 133b of the protective film 133 directly above the optical interface 131L is kept unobstructed by the encapsulation 152-2. In the illustrated embodiment, the encapsulation 152-2 covers the sidewall 130c of the IC die 130 and extends to cover a portion of the outermost surface 133b of the protective film 133. For example, the lateral dimension LD2 of the portion of the encapsulation 152-2 directly above the outermost surface 133b of the protective film 133 is non-zero. In some embodiments, the lateral dimension LD2 is in the range of approximately 2 μm to approximately 5 μm. It should be understood that the range of the lateral dimension LD2 is merely an example and may be changed to other suitable values ​​depending on product requirements.

[0060] refer to Figure 6 And refer to Figure 2I or Figure 4D A semiconductor package 40 may be provided. In some embodiments, the semiconductor package 40 is an integrated fan-out (InFO) package. For example, the semiconductor package 40 includes IC dies 110' and 130' arranged side-by-side and laterally covered by encapsulations 152-3. Except that the contact pads 1163 of IC die 110' can be used as die connectors for further electrical connections, IC die 110' may be similar to... Figure 1A The IC die 110 described herein. In the illustrated embodiment, the contact pad 1163 is laterally covered by a passivation layer 1164. Alternatively, the passivation layer 1164 can be omitted and the contact pad 1163 can be laterally covered by the encapsulation 152-3. Except that the contact pad 1325 of the IC die 130' can be used as a die connector for further electrical connections, the IC die 130' can be similar to... Figure 1C The IC die 130 described herein. In the illustrated embodiment, contact pad 1325 is laterally covered by passivation layer 1326. Alternatively, passivation layer 1326 can be omitted and contact pad 1325 can be laterally covered by encapsulation 152-3. Although two IC dies (110' and 130') are shown here, more than two IC dies of the same or different types (e.g., IC die 120) can be encapsulated using encapsulation 152-3.

[0061] Continue to refer to Figure 6A redistribution structure 410 may be formed on the enclosure 152-3 and the IC dies (110' and 130'). In some embodiments, the redistribution structure 410 is referred to as a fan-out redistribution structure or an interconnect structure. The redistribution structure 410 may provide electrical interconnection between the IC dies (110' and 130'). The redistribution structure 410 may include a dielectric layer 412 and a metallization pattern 414. The metallization pattern 414 may include metal lines, metal vias, metal pads, etc. In some embodiments, the metal vias of the metallization pattern 414 make physical and electrical contact with the contact pads 1325 and 1163 of the IC die 130' and IC die 110'. The metallization pattern 414 may reroute signals between the IC dies (110' and 130') and may be referred to as a redistribution layer (RDL). The redistribution structure 410 is shown as an example having three metallization patterns 414 and three dielectric layers 412. More or fewer dielectric layers 412 and metallization patterns 414 may be formed in the redistribution structure 410. The semiconductor package 40 may include external terminals 416 formed beneath the redistribution structure 410. The external terminals 416 may be BGA connectors, solder balls, metal pillars, C4 bumps, microbumps, ENEPIG-formed bumps, or the like.

[0062] Continue to refer to Figure 6 The back side of IC die 130' may be partially or completely exposed by the encapsulation 152-3, as shown by dashed boxes (2G, 4C, and 5), where dashed box 2G corresponds to Figure 2G The enlarged view shown has dashed box 4C corresponding to... Figure 4C The enlarged view shown, with dashed box 5 corresponding to... Figure 5 The enlarged view shown. For details regarding the relationship between the package 152-3 and the IC die 130', please refer to [reference needed]. Figure 2G , Figure 4C , Figure 5 The embodiments shown will not be described in detail here.

[0063] Figure 7 This is a flowchart illustrating a method 500 for forming a semiconductor package according to some embodiments. While this and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that the invention is not limited to the illustrated sequence or actions. The actions may be performed in a different order than shown and / or simultaneously. The illustrated actions or events may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. Some illustrated actions or events may be omitted, and other actions or events not shown may be included. Actions may correspond to previously... Figures 2A-2B and Figure 2E-Figure 2I or Figures 4A-4D The structure shown.

[0064] At action 510, the IC die can be coupled to an interposer (or interconnect / rewiring structure), wherein at least one of the IC dies (e.g., IC die 130) includes an optical path (e.g., multiple portions of optically coupled to the optical interface 131L including optical interface 131L, protective film 133, and dielectric layer 136). Figure 2A Cross-sectional views corresponding to some embodiments of action 510 are shown.

[0065] At action 520, an encapsulation can be formed on the intermediary to cover the IC die. Figure 2B and Figures 2E-2F and Figures 4A-4B Cross-sectional views corresponding to some embodiments of action 520 are shown.

[0066] At action 530, a portion of the encapsulation is removed to expose the top surface and optical path of one of the IC dies (e.g., IC die 130). In some embodiments, heat dissipation of IC die 130 is improved because the top surface of IC die 130 is fully or partially exposed by the encapsulation. The optical path of IC die 130 can be exposed by the encapsulation to facilitate optical signal transmission. Figure 2G and Figure 4C Cross-sectional views corresponding to some embodiments of action 530 are shown. At sub-action 5301, the sacrificial film covering the optical path can be removed. Figure 2G Cross-sectional views corresponding to some embodiments of action 5301 are shown. At sub-action 5302, an opening is formed in the encapsulation to expose the optical path. Figure 4C Cross-sectional views corresponding to some embodiments of action 5302 are shown. It should be noted that multiple subsequent steps (e.g., forming a metallization layer and other back end of line (BEOL) steps / packaging steps) may be performed to produce a usable working semiconductor package.

[0067] Other features and processes may also be included. For example, test structures may be included to assist in the testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in redistribution layers or on substrates, which allow for testing of 3D packages or 3DICs, probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods incorporated into intermediate verification of known good dies to increase yield and reduce costs.

[0068] According to some embodiments, a semiconductor package includes a first die and a second die arranged side-by-side, an encapsulation laterally covering the first die and the second die, and an interconnect structure underlying the encapsulation. Each of the first die and the second die includes a front side and a back side opposite to each other. The second die also includes an optical interface on its back side, and the top surface of the back side of the second die and the optical interface are exposed by the encapsulation. The interconnect structure is connected to the front sides of the first and second dies, and the second die is electrically coupled to the first die through the interconnect structure.

[0069] In some embodiments, the back side of the second die is between the top surface of the encapsulation and the front side of the second die. In some embodiments, the apex of the optical interface of the second die is between the back side of the second die and the front side of the second die. In some embodiments, the second die includes a photonic integrated circuit, an electronic integrated circuit disposed on and bonded to the photonic integrated circuit, and a dielectric layer disposed on the photonic integrated circuit and covering the sidewalls and top surface of the electronic integrated circuit. In some embodiments, the second die further includes an optical component including a first side bonded to the dielectric layer, a second side opposite to the first side, the optical interface disposed on the second side, and a recess disposed on the second side and surrounding the optical interface. In some embodiments, the second die further includes a protective film disposed on the second side of the optical component and filling the recess to cover the optical interface. In some embodiments, the encapsulation includes a top surface and an inner sidewall connected to the top surface and intersecting the second die, and the surface roughness of the top surface of the encapsulation is greater than the surface roughness of the inner sidewall of the encapsulation. In some embodiments, the inner sidewall of the encapsulation is substantially coplanar with the sidewall of the second die that connects to the front and back sides. In some embodiments, the encapsulation includes a top surface and an inner sidewall connected to the top surface and intersecting the second die, and the surface roughness of the inner sidewall of the encapsulation is greater than the surface roughness of the top surface of the encapsulation. In some embodiments, the encapsulation includes a first top surface and a second top surface, the top surface of the back side of the second die being between the first top surface and the second top surface of the encapsulation, and the second top surface of the encapsulation being substantially coplanar with the top surface of the back side of the second die. In some embodiments, the interconnect structure is part of an intermediary or redistribution structure.

[0070] According to some embodiments, a semiconductor package includes a first die, a second die laterally disposed next to the first die, an interconnect structure, and an encapsulation disposed on the interconnect structure. The first die includes a front side, a back side opposite to the front side, and sidewalls connecting the front and back sides. The second die includes a PIC, an EIC disposed on and bonded to the PIC, a dielectric layer disposed on the PIC and covering the EIC, and optical components disposed on the EIC and the dielectric layer, wherein the optical components include an optical interface on the side opposite to the dielectric layer. The interconnect structure connects to the front side of the first die and the PIC of the second die, and the second die is electrically coupled to the first die through the interconnect structure. The encapsulation is disposed on the interconnect structure and extends along the sidewalls of the first and second dies. The encapsulation includes an opening exposing the optical interface and an upper inner sidewall surrounding the opening. The height of the second die is less than the height of the first die.

[0071] In some embodiments, the top surface of the encapsulation, connected to the upper inner sidewall, is higher than the optical interface of the second die relative to the interconnect structure. In some embodiments, the upper inner sidewall of the encapsulation is angled and intersects the second die. In some embodiments, the encapsulation extends laterally along the sidewalls of the photonic integrated circuit, the electronic integrated circuit, the dielectric layer, and the optical component. In some embodiments, the encapsulation includes a substrate and a filler in the substrate, a portion of which is exposed by the substrate at the top surface of the encapsulation. In some embodiments, another portion of the filler is exposed by the substrate at the upper inner sidewall of the encapsulation, connected to the top surface of the encapsulation.

[0072] According to some embodiments, a method of manufacturing a semiconductor package includes: coupling a first die and a second die to an interposer, wherein the second die includes an optical path; forming an encapsulation on the interposer to cover the first and second dies; and removing a portion of the encapsulation to expose the top surface of the second die and the optical path.

[0073] In some embodiments, the second die is provided with a sacrificial film covering the optical path, the optical path remaining covered by the sacrificial film during the formation of the encapsulation, and the manufacturing method further includes removing the sacrificial film after removing the portion of the encapsulation. In some embodiments, removing the portion of the encapsulation includes forming an opening in the encapsulation to at least expose the optical path of the second die.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor package, characterized in that, include: A first die and a second die are arranged side by side, each of the first die and the second die includes a front side and a back side opposite to each other, and the second die also includes an optical interface on the back side; An encapsulation body laterally covers the first die and the second die, with the top surface of the back side of the second die and the optical interface exposed by the encapsulation body; as well as An interconnect structure lies beneath the encapsulation and connects to the front sides of the first die and the second die, wherein the second die is electrically coupled to the first die through the interconnect structure.

2. The semiconductor package according to claim 1, characterized in that, The back side of the second die is located between the top surface of the encapsulation and the front side of the second die.

3. The semiconductor package according to claim 1, characterized in that, The highest point of the optical interface of the second die is located between the back side and the front side of the second die.

4. The semiconductor package according to claim 1, characterized in that, The second die includes a photonic integrated circuit, an electronic integrated circuit disposed on and bonded to the photonic integrated circuit, and a dielectric layer disposed on the photonic integrated circuit and covering the sidewalls and top surface of the electronic integrated circuit.

5. The semiconductor package according to claim 1, characterized in that, The encapsulation includes a top surface and an inner wall connected to the top surface and intersecting with the second die, and the surface roughness of the top surface of the encapsulation is greater than the surface roughness of the inner wall of the encapsulation.

6. The semiconductor package according to claim 1, characterized in that, The encapsulation includes a top surface and an inner wall connected to the top surface and intersecting with the second die, and the surface roughness of the inner wall of the encapsulation is greater than the surface roughness of the top surface of the encapsulation.

7. The semiconductor package according to claim 1, characterized in that, The encapsulation includes a first top surface and a second top surface, the top surface of the back side of the second die is between the first top surface and the second top surface of the encapsulation, and the second top surface of the encapsulation is coplanar with the top surface of the back side of the second die.

8. A semiconductor package, characterized in that, include: The first die includes a front side, a back side opposite to the front side, and a sidewall connected to the front side and the back side; The second die is disposed laterally next to the first die. The second die includes a photonic integrated circuit, an electronic integrated circuit disposed on and bonded to the photonic integrated circuit, a dielectric layer disposed on and covering the electronic integrated circuit, and an optical component disposed on the electronic integrated circuit and the dielectric layer. The optical component includes an optical interface on the side opposite to the dielectric layer, and the height of the second die is less than the height of the first die. An interconnect structure is provided, connecting the front side of the first die and the photonic integrated circuit of the second die, wherein the second die is electrically coupled to the first die through the interconnect structure. as well as An encapsulation body, disposed on the interconnect structure and extending along the sidewalls of the first die and the second die, the encapsulation body including an opening exposing the optical interface and an upper inner sidewall surrounding the opening.

9. The semiconductor package according to claim 8, characterized in that, The top surface of the encapsulation connected to the upper inner wall is higher than the optical interface of the second die relative to the interconnect structure.

10. The semiconductor package according to claim 8, characterized in that, The encapsulation includes a substrate and a filler in the substrate, a portion of which is exposed by the substrate at the top surface of the encapsulation.

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