Parallel flip chip packaging structure of power chip

Abstract

The application relates to a parallel flip-chip packaging structure of a power chip, which comprises a packaging substrate and a packaging cover plate, the packaging substrate comprises a common-source connecting plate and a common-gate connecting plate; a plurality of parallelly connected source welding islands are arranged on a source pad of the common-source connecting plate at intervals; a plurality of parallelly connected gate welding islands are arranged on a gate pad of the common-gate connecting plate at intervals; the plurality of source welding islands and the plurality of gate welding islands are alternately arranged and isolated; the packaging cover plate is used as a common-drain connecting cover plate and is used for covering the source pad and the gate pad. The packaging structure can realize parallel flip-chip packaging of a plurality of power chips, the area and the volume of the overall packaging structure are as small as possible, the current path is effectively shortened, the on-resistance and the thermal resistance are reduced, and the overall performance of the device is improved.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit packaging technology, and in particular to a parallel flip-chip packaging structure for power chips. Background Technology

[0002] MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are currently the most commonly used voltage-controlled power switching devices, widely applied in power management, motor drives, and switching circuits. As electronic devices evolve towards miniaturization, higher efficiency, and higher power, higher demands are being placed on the packaging structure of MOSFETs.

[0003] Existing MOSFETs employ wire bonding packaging technology, such as the transistor packaging structure and fabrication method disclosed in Chinese patent CN120529629A. In this process, the gate of the MOSFET is connected to the gate terminal of the substrate via a wire, the source of the MOSFET is connected to the interconnect layer on the substrate, and the drain of the MOSFET is connected to the source of another HEMT via a wire. Wire bonding packaging results in high internal resistance of the packaged device and limited overcurrent and overvoltage capabilities. Furthermore, it is increasingly difficult to meet high-performance requirements in terms of heat dissipation, parasitic inductance, and space utilization.

[0004] On the other hand, existing MOSFETs are usually single-chip packages, with a single overcurrent of less than 20A. This makes it difficult to meet the high current requirements in high-power applications. In actual use, multiple MOSFETs need to be connected in parallel, which leads to problems such as large footprint, large size, increased system complexity, and difficulty in current sharing design. Utility Model Content

[0005] Therefore, the purpose of this utility model is to provide a parallel flip-chip package structure for power chips. This package structure adopts a package substrate with a common source connection plate and a common gate connection plate that are interleaved and isolated from each other, and a common drain connection cover plate. It can connect several power chips in parallel and flip-chip, so that the area and volume of the overall package structure are as small as possible, and the current path is effectively shortened, the on-resistance and thermal resistance are reduced, and the overall performance of the device is improved.

[0006] A parallel flip-chip package structure for a power chip includes a package substrate and a package cover plate, wherein the package substrate includes a common source connection plate and a common gate connection plate. The common source electrode connection plate includes a source electrode pad, and a plurality of source electrode islands are arranged in parallel on the source electrode pad at intervals. Source electrode bumps are provided on the source electrode islands. The common gate connection board includes a gate pad, and a plurality of gate bonding islands are arranged in parallel on the gate pad at intervals. Gate bonding islands are provided with gate pad bumps. The plurality of source solder islands and the plurality of gate solder islands are interspersed and isolated from each other; The package cover plate, as a common drain connection cover plate, is used to cover the source pad and the gate pad.

[0007] Furthermore, the spacing between adjacent source bonding islands is equal, and this spacing is the first isolation gap △S1; the first isolation gap △S1 is greater than the width of the gate bonding island.

[0008] Furthermore, the spacing between adjacent gate bonding islands is equal, and this spacing is the second isolation gap △S2; the second isolation gap △S2 is greater than the width of the source bonding island.

[0009] Furthermore, the values ​​of the first isolation gap △S1 and the second isolation gap △S2 are determined according to the source and gate settings of the power chip to be packaged.

[0010] Furthermore, the common source connection plate also includes a source conductor plate, which is connected to the source pad; one end of the source conductor plate is also provided with a test resistor connection position.

[0011] Furthermore, the common gate connection plate also includes a gate guide plate, which is connected to the gate pad; one end of the gate guide plate is also provided with a gate lead.

[0012] Furthermore, the surfaces of the source plate, source pad, gate plate, and gate pad are Cu / Al2O3 metal oxide composite layers.

[0013] Furthermore, the thickness of the Cu layer in the Cu / Al2O3 metal oxide composite layer is controlled at 0.2 mm to 0.4 mm, and the thickness of the Al2O3 layer is controlled at 0.9 mm to 1.1 mm.

[0014] Furthermore, a solder resist layer is provided on the source pad in the area excluding the source pad bump and on the gate pad in the area excluding the gate pad bump, wherein the thickness of the solder resist layer is controlled to be 10μm to 30μm.

[0015] Furthermore, it also includes a packaging frame, which is a ceramic frame used to support the packaging substrate.

[0016] Compared with existing technologies, this invention, through its designed packaging substrate with interleaved and isolated common-source and common-gate connection plates, and a common-drain connection cover plate covering several power chips, effectively solves the problems of large packaging area, large volume, complex wire bonding system, and difficult current sharing design associated with existing parallel connection of multiple power chips via wire bonding. By using a ceramic frame to support the packaging substrate, stress deformation during high-temperature packaging is effectively reduced, addressing the issue of deformation of conventional copper frames when the packaging substrate experiences excessive current (200A-1000A). The parallel power chips packaged using this structure can withstand a high current of 1000A for over 5 seconds. Attached Figure Description

[0017] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the packaging substrate for the parallel flip-chip structure of the power chip of this utility model; Figure 2 This is a schematic diagram of the parallel flip-chip structure of the power chip of this utility model after packaging. Detailed Implementation

[0019] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings of the embodiments. The described embodiments are merely some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0020] Please see Figure 1 and Figure 2 The present invention discloses a parallel flip-chip packaging structure for power chips, comprising a packaging substrate 1, a packaging cover plate 3, and a packaging frame 5. The packaging cover plate 3 covers the packaging substrate 1 on which several power chips are soldered, and the packaging substrate 1 is mounted on the packaging frame 2.

[0021] The packaging substrate 1 includes a common source connection plate 10 and a common gate connection plate 20. The common source connection plate 10 and the common gate connection plate 20 are interlocked and isolated from each other.

[0022] The common source connection plate 10 includes a source conductor plate 11 and a source pad 12, which are used to realize the parallel connection of the sources of multiple power chips.

[0023] The source electrode plate 11 is electrically connected to the source electrode pad 12.

[0024] The source pad 12 has a plurality of source pad islands 122 spaced apart, and a plurality of source pad bumps 124 are arrayed on the source pad islands 122.

[0025] Furthermore, the spacing between adjacent source solder islands 122 is equal, and this spacing is the first isolation gap △S1, which is used to prevent short circuits between sources.

[0026] Furthermore, a test resistor connection position 126 is provided at one end of the source pad 12. The test resistor connection position 126 can be electrically connected to the source of each power chip to monitor the total current of the parallel power chips in real time, thereby improving the reliability and maintainability of the package module. The resistance value of the test resistor connected to the test resistor connection position 126 is controlled within ±1% to ensure the accuracy of current detection.

[0027] The common gate connection plate 20 includes a gate conductor plate 21 and a gate pad 22, which are used to realize the parallel connection of the gates of multiple power chips.

[0028] The gate conductor 21 is electrically connected to each gate pad 22.

[0029] The gate guide plate 21 extends to the edge of the package and is provided with a gate lead 211 to facilitate the access of external drive signals.

[0030] The gate pad 22 has a plurality of gate solder islands 222 spaced apart, and one or more gate solder bumps 224 are provided on each gate solder island 222. The number of gate solder islands 222 matches the number of source solder islands 122.

[0031] Furthermore, the spacing between adjacent gate bonding islands 222 is equal, and this spacing is the second isolation gap ΔS2, to prevent short circuits between gates and meet high-voltage insulation requirements. The values ​​of the first isolation gap ΔS1 and the second isolation gap ΔS2 are determined based on the source and gate configurations of the power chip to be packaged. Furthermore, the spacing of the second isolation gap △S2 is greater than the width of the source bonding island 122, and the spacing of the first isolation gap △S1 is greater than the width of the gate bonding island 222, so that when the several source bonding islands 122 and several gate bonding islands 222 are interlocked and isolated, the package area can be reduced while meeting the electrical connection requirements of the source and gate of the power chip.

[0032] Furthermore, the surfaces of the source plate 11, source pad 12, gate plate 21, and gate pad 22 are Cu / Al2O3 metal oxide composite layers, wherein the thickness of the Cu layer is controlled between 0.2 mm and 0.4 mm, and the thickness of the Al2O3 layer is controlled between 0.9 mm and 1.1 mm, so that the total thickness of the Cu / Al2O3 metal oxide composite layer is controlled between 1.1 mm and 1.5 mm.

[0033] Furthermore, a solder resist layer is applied to the area on the source pad 12 other than the source pad bump 124, and to the area on the gate pad 22 other than the gate pad bump 224, and to the other areas except for the test resistor connection bit 126 and the gate lead 211, to prevent short circuits and improve insulation performance. Please refer to [link to relevant documentation]. Figure 1 The black area in the middle is the solder mask area.

[0034] The solder resist layer is made of high-temperature resistant epoxy resin material, and its thickness is controlled between 10μm and 30μm.

[0035] The encapsulation cover 3 is a common-drain connection cover 30.

[0036] The common-drain connection cover plate 30 is a metal layer used to cover all the power chips soldered in parallel on the packaging substrate, realizing low-impedance parallel connection of the drains of all MOSFETs, further reducing on-resistance and thermal resistance, and improving the overall performance of the device. At the same time, the metal layer plate also has a heat dissipation function, efficiently conducting the heat from the chip to the external heat sink.

[0037] Furthermore, the metal plate is a copper sheet.

[0038] Furthermore, the thickness of the common-drain connection cover 30 is controlled between 0.3 mm and 0.5 mm to ensure good conductivity and mechanical strength. The surface of the common-drain connection cover 30 that is not electrically connected to the drain of the power chip is also covered with a Cu / Al2O3 metal oxide composite layer.

[0039] The packaging frame 5 has an internal cavity size that matches that of the packaging substrate 1 and is used to support the packaging substrate 1.

[0040] Furthermore, the packaging frame 5 is a ceramic frame, and the coefficient of thermal expansion of the ceramic frame matches that of the packaging substrate 1, effectively reducing stress deformation during the high-temperature packaging process. This solves the problem that conventional copper frames are prone to deformation when the packaging substrate experiences excessive current (200A-1000A).

[0041] Please see Figure 1 and Figure 2 In some embodiments, a common source connection plate 10' and a common gate connection plate 20' are also provided on the same packaging frame 5. The common source connection plate 10' and the common gate connection plate 20' form a mirror symmetrical layout with the common source connection plate 10 and the common gate connection plate 20. The common drain connection cover plate 3 is covered on the source connection plate 10, the common source connection plate 10', the common gate connection plate 20 and the common gate connection plate 20' to improve the efficiency of the packaging process and the utilization rate of the packaging area.

[0042] This invention utilizes a package substrate with interleaved and isolated common-source and common-gate connection plates, and a common-drain connection cover plate covering several power chips. This allows for parallel flip-chip connection of multiple power chips, effectively solving the problems of large package area, large volume, complex wire bonding systems, and difficult current sharing design associated with existing parallel connection methods using wire bonding. By employing a ceramic frame to support the package substrate, stress deformation during high-temperature packaging is effectively reduced, addressing the issue of deformation easily occurring in conventional copper frames when the package substrate experiences excessive current (200A-1000A). This packaging structure is suitable for power chips with source, gate, and drain terminals, such as MOSFETs and IGBTs.

[0043] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0044] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0045] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and the present invention also intends to include these modifications and variations.

Claims

1. A parallel flip-chip package structure for a power chip, comprising a package substrate and a package cover, characterized in that: The packaging substrate includes a common source connection plate and a common gate connection plate; The common source electrode connection plate includes a source electrode pad, and a plurality of source electrode islands are arranged in parallel on the source electrode pad at intervals. Source electrode bumps are provided on the source electrode islands. The common gate connection board includes a gate pad, and a plurality of gate bonding islands are arranged in parallel on the gate pad at intervals. Gate bonding islands are provided with gate pad bumps. The plurality of source solder islands and the plurality of gate solder islands are interspersed and isolated from each other; The package cover plate, as a common drain connection cover plate, is used to cover the source pad and the gate pad.

2. The parallel flip-chip package structure of the power chip according to claim 1, characterized in that, The spacing between adjacent source bonding islands is equal, and this spacing is the first isolation gap △S1; the first isolation gap △S1 is greater than the width of the gate bonding island.

3. The parallel flip-chip package structure of the power chip according to claim 2, characterized in that, The spacing between adjacent gate bonding islands is equal, and this spacing is the second isolation gap △S2; the second isolation gap △S2 is greater than the width of the source bonding island.

4. The parallel flip-chip package structure of the power chip according to claim 3, characterized in that, The values ​​of the first isolation gap △S1 and the second isolation gap △S2 are determined according to the source and gate settings of the power chip to be packaged.

5. The parallel flip-chip package structure of the power chip according to claim 1, characterized in that, The common source connection plate also includes a source conductor plate, which is connected to the source pad; one end of the source conductor plate is also provided with a test resistor connection position.

6. The parallel flip-chip package structure of the power chip according to claim 5, characterized in that, The common gate connection plate also includes a gate guide plate, which is connected to the gate pad; one end of the gate guide plate is also provided with a gate lead.

7. The parallel flip-chip package structure of the power chip according to claim 6, characterized in that, The surfaces of the source plate, source pad, gate plate, and gate pad are Cu / Al2O3 metal oxide composite layers.

8. The parallel flip-chip package structure of the power chip according to claim 7, characterized in that, The thickness of the Cu layer in the Cu / Al2O3 metal oxide composite layer is controlled at 0.2 mm to 0.4 mm, and the thickness of the Al2O3 layer is controlled at 0.9 mm to 1.1 mm.

9. The parallel flip-chip package structure of the power chip according to claim 1, characterized in that, A solder resist layer is provided on the source pad in the area excluding the source pad bump, and on the gate pad in the area excluding the gate pad bump, wherein the thickness of the solder resist layer is controlled to be 10 μm to 30 μm.

10. The parallel flip-chip package structure of the power chip according to claim 1, characterized in that, It also includes a packaging frame, which is a ceramic frame used to support the packaging substrate.

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