A sensing structure suitable for a glass non-magnetic base surface

Abstract

The utility model belongs to sensor technical field discloses a kind of sensing structure suitable for glass non-magnetic base table. The sensing structure suitable for glass non-magnetic base table, including bottom layer induction coil and pin header pad, the bottom layer induction coil includes outer layer coil and inner layer coil, the structure of outer layer coil and each inner layer coil is respectively electrically connected with each contact on pin header pad. The sensing structure suitable for glass non-magnetic base table can effectively reduce the complexity of induction coil part circuit, and is connected by standard pin between main control board, so that induction coil board and main control board form a whole, reduce the quantity of MCU, improve the reliability of circuit, adjustable while reducing the complexity of assembly process, reduce production cost.

Description

Technical Field

[0001] This utility model relates to the technical field of sensors, specifically a sensing structure suitable for non-magnetic glass substrates. Background Technology

[0002] The sensors currently used in glass non-magnetic base meters are all independent and are generally connected to the main control board via flexible flat cables. Both the sensor and the main control board have independent MCUs. Due to the limited space in the sensor position, it is difficult to design a stable and reliable circuit for the sensor part, resulting in poor sensor reliability. Utility Model Content

[0003] The purpose of this utility model is to provide a sensing structure suitable for non-magnetic glass-based watches, which solves the problems mentioned in the background art.

[0004] To achieve the above objectives, this utility model is implemented through the following technical solution: a sensing structure suitable for glass non-magnetic base watches, including a bottom induction coil and pin header pads, wherein the bottom induction coil includes an outer coil and an inner coil, and the structure of the outer coil and each inner coil is electrically connected to each contact on the pin header pads, thereby establishing a connection with the main control board.

[0005] Preferably, the inner coil's inner terminal to its outer terminal are both counterclockwise windings.

[0006] Preferably, the outer coil has a counterclockwise winding from its external connector to its internal connector.

[0007] Preferably, the pin header pad includes eight pins numbered 1-8, wherein pins 1, 2, and 7 are electrically connected to ground (GND) to the external connectors of the outer coil and the internal connectors of the four inner coils; pins 3, 5, 4, and 6 are electrically connected to the external connectors of the four inner coils respectively; and pin 8 is electrically connected to the internal connector of the outer coil.

[0008] Preferably, the four inner coils are arranged in a ring within the outer coils.

[0009] Preferably, the main control board module includes a first external signal pin header input group, consisting of contacts J3 and J6, for connecting external devices to input signals to be processed; The second external signal pin header input group, consisting of contacts J4 and J5, is used to connect external devices to input signals to be processed. The first transistor signal conditioning circuit consists of transistor Q1, resistors R27, R28, R23, R12, R15, and capacitors C37 and C38. The input terminal of the first transistor signal conditioning circuit is connected to the output terminal of the first external signal pin header input group, and the output terminal is connected to the PA06 and PA07 pins of the main control chip. It is used to process the signal input from the first external signal pin header input group. The second transistor signal conditioning circuit consists of transistor Q3, resistors R29, R30, R31, and capacitors C39 and C40. The input terminal of the second transistor signal conditioning circuit is connected to the output terminal of the second external signal pin header input group, and the output terminal is connected to the PA05 and PA04 pins of the main control chip. It is used to process the signal input from the second external signal pin header input group. The first preprocessing circuit, consisting of resistors R34 and R35, is connected between the first external signal header input group and the first transistor signal conditioning circuit, and is used to sample and preprocess the signal input to the first external signal header input group. The second preprocessing circuit, consisting of resistors R36 and R37, is connected between the second external signal header input group and the second transistor signal conditioning circuit, and is used to sample and preprocess the signal input to the second external signal header input group. The control, triggering and synchronization circuit consists of logic chip U5, resistors R42, R39, R41 and capacitors C32, C33, C29 and C30. The input terminal of the control, triggering and synchronization circuit is connected to the PB02 pin of the main control chip, and the output terminal is connected to the signal output contact J8. It is used to process the signal input from the PB02 pin and output it to J8. J3, J4, J5, J6 and J8 are electrically connected to pins 3, 4, 5, 6 and 8 of the pin header pads, respectively.

[0010] By adopting the aforementioned technical solution, the beneficial effects of this utility model are: This sensing structure, suitable for glass non-magnetic base meters, can effectively reduce the complexity of the induction coil circuit. It connects to the main control board via standard pin headers, making the induction coil board and the main control board a unified whole. This reduces the number of MCUs, improves circuit reliability and adjustability, reduces assembly process complexity, and lowers production costs. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the existing technology; Figure 2 This is a schematic diagram of the bottom layer induction coil structure of this utility model; Figure 3 This is a schematic diagram of the structure of the surface mount pin pad of this utility model; Figure 4 This is the circuit diagram of the main control board module of this utility model.

[0012] In the diagram: 100, bottom induction coil; 101, outer coil; 102, inner coil; 200, pin header pad. Detailed Implementation

[0013] Please see Figure 1-4 This utility model provides a technical solution: a sensing structure suitable for a glass non-magnetic base watch, including a bottom induction coil 100 and a pin header pad 200. The bottom induction coil includes an outer coil 101 and an inner coil 102. The outer coil is an excitation (primary) coil, and the inner coil is a separately excited (secondary) coil. The connectors of the outer coil 101 and each inner coil 102 are electrically connected to the contacts on the pin header pad 200, thereby establishing a connection with the main control board. The outer coil 101 has a counterclockwise winding from its outer connector to its inner connector, and the inner coil 102 has a counterclockwise winding from its inner connector to its outer connector. The four inner coils 102 are arranged in a ring inside the outer coil.

[0014] It should be noted that you should refer to [link / reference]. Figure 2-3 , Figure 3 The middle circular contact is the connection point between the pin header pad 200 and the bottom induction coil 100. Figure 2 For ease of understanding, the connectors of the bottom-layer induction coil 100 are numbered. The pin header pad 200 includes eight pins, of which pins 1, 2, and 7 are connected to ground (GND) via contacts 2, 10, 11, 12, and 13 of the induction coil; pin 3 is connected to contact 3 of the induction coil; pin 5 is connected to contact 4 of the induction coil; pin 4 is connected to contact 5 of the induction coil; pin 6 is connected to contact 6 of the induction coil; and pin 8 is connected to contact 1 of the induction coil.

[0015] The pin header pad includes eight pins numbered 1-8. Pins 1, 2, and 7 are electrically connected to ground (GND) to the external connectors of the outer coil and the internal connectors of the four inner coils. Pins 3, 5, 4, and 6 are electrically connected to the external connectors of the four inner coils, respectively. Pin 8 is connected to the internal connector of the outer coil.

[0016] See Figure 4The connection circuit between the pin header pad 200 and the main control board is disclosed, with the following key points: PB02 is connected to the MCU's I / O port; PA05 and PA06 are connected to the positive and negative phases of the comparator inside the MCU; PA04 and PA07 are connected to the positive and negative phases of the comparator inside the MCU; J8 is connected to pin header 8; J3 is connected to pin header 3; J6 is connected to pin header 6; J4 is connected to pin header 4; J5 is connected to pin header 5; Q1 and Q3 are dual transistor electronic components, and U5 is a 74LVC14 inverter.

[0017] Please see Figure 4 The circuit diagram of the main control board module is shown. This circuit is a multi-channel signal conditioning and interface circuit, used to realize signal interaction between external devices and the main control chip (such as a microcontroller). The core module includes a pin header interface, signal conditioning circuit, preprocessing circuit and auxiliary control filtering circuit. The functions of each part are as follows; The main control board module includes a first external signal pin header input group, consisting of contacts J3 and J6, used to connect external devices to input signals to be processed; The second external signal pin header input group, consisting of contacts J4 and J5, is used to connect external devices to input signals to be processed. The first transistor signal conditioning circuit consists of transistor Q1, resistors R27, R28, R23, R12, R15, and capacitors C37 and C38. The input terminal of the first transistor signal conditioning circuit is connected to the output terminal of the first external signal pin header input group, and the output terminal is connected to the PA06 and PA07 pins of the main control chip. It is used to process the signal input from the first external signal pin header input group. The second transistor signal conditioning circuit consists of transistor Q3, resistors R29, R30, R31, and capacitors C39 and C40. The input terminal of the second transistor signal conditioning circuit is connected to the output terminal of the second external signal pin header input group, and the output terminal is connected to the PA05 and PA04 pins of the main control chip. It is used to process the signal input from the second external signal pin header input group. The first preprocessing circuit, consisting of resistors R34 and R35, is connected between the first external signal header input group and the first transistor signal conditioning circuit, and is used to sample and preprocess the signal input to the first external signal header input group. The second preprocessing circuit, consisting of resistors R36 and R37, is connected between the second external signal header input group and the second transistor signal conditioning circuit, and is used to sample and preprocess the signal input to the second external signal header input group. The control, triggering, and synchronization circuit consists of logic chip U5, resistors R42, R39, and R41, and capacitors C32, C33, C29, and C30. U5 is connected to the PB02 pin of the main control chip, and the program controls PB02. Pin 4 of U5 generates a high-frequency pulse excitation signal, which is coupled to contact J8 via capacitor C31. Output pin 4 of U5 is connected to pin 1, and output pin 6, along with C32 and R41, generates a negative pulse power signal synchronized with the signal at pin 4. This signal is connected to the emitters of Q1 and Q2 via resistors R23, R31, R27, R28, R29, and R30, constructing a signal amplification and processing circuit synchronized with the excitation signal source. This ensures signal stability and reliability. J3, J4, J5, J6 and J8 are electrically connected to pins 3, 4, 5, 6 and 8 of the pin header pads, respectively.

[0018] Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A sensing structure suitable for non-magnetic glass substrate watches, characterized in that: It includes a bottom-layer induction coil, pin header pads, and a main control board module. The bottom-layer induction coil includes an outer coil and an inner coil. The four inner coils are arranged in a ring inside the outer coil. The structure of the outer coil and each inner coil is electrically connected to each contact on the pin header pad, thereby establishing a connection with the main control board module.

2. The sensing structure suitable for a non-magnetic glass substrate as described in claim 1, characterized in that: The inner coil's inner terminal to its outer terminal are both counterclockwise windings.

3. The sensing structure suitable for a non-magnetic glass substrate as described in claim 2, characterized in that: The outer coil's external connector to its internal connector is a counter-clockwise winding.

4. The sensing structure suitable for a non-magnetic glass substrate as described in claim 3, characterized in that: The pin header pad includes eight pins numbered 1-8. Pins 1, 2, and 7 are electrically connected to the external connectors of the outer coil and the internal connectors of the four inner coils and grounded. Pins 3, 5, 4, and 6 are electrically connected to the external connectors of the four inner coils, respectively. Pin 8 is electrically connected to the internal connector of the outer coil.

5. A sensing structure suitable for a non-magnetic glass substrate watch according to any one of claims 1-4, characterized in that: The main control board module includes a first external signal pin header input group, consisting of contacts J3 and J6, used to connect external devices to input signals to be processed; The second external signal pin header input group, consisting of contacts J4 and J5, is used to connect external devices to input signals to be processed. The first transistor signal conditioning circuit consists of transistor Q1, resistors R27, R28, R23, R12, R15, and capacitors C37 and C38. The input terminal of the first transistor signal conditioning circuit is connected to the output terminal of the first external signal pin header input group, and the output terminal is connected to the PA06 and PA07 pins of the main control chip. It is used to process the signal input from the first external signal pin header input group. The second transistor signal conditioning circuit consists of transistor Q3, resistors R29, R30, R31, and capacitors C39 and C40. The input terminal of the second transistor signal conditioning circuit is connected to the output terminal of the second external signal pin header input group, and the output terminal is connected to the PA05 and PA04 pins of the main control chip. It is used to process the signal input from the second external signal pin header input group. The first preprocessing circuit, consisting of resistors R34 and R35, is connected between the first external signal header input group and the first transistor signal conditioning circuit, and is used to sample and preprocess the signal input to the first external signal header input group. The second preprocessing circuit, consisting of resistors R36 and R37, is connected between the second external signal header input group and the second transistor signal conditioning circuit, and is used to sample and preprocess the signal input to the second external signal header input group. The control, triggering and synchronization circuit consists of logic chip U5, resistors R42, R39, R41 and capacitors C32, C33, C29 and C30. The input terminal of the control, triggering and synchronization circuit is connected to the PB02 pin of the main control chip, and the output terminal is connected to the signal output contact J8. It is used to process the signal input from the PB02 pin and output it to J8. J3, J4, J5, J6 and J8 are electrically connected to pins 3, 4, 5, 6 and 8 of the pin header pads, respectively.

Images