A residual voltage detection circuit

Abstract

A residual voltage detection circuit, comprising: a sampling terminal for sampling incoming or outgoing voltage of any phase of ABC three-phase bus, a control signal input terminal for receiving residual voltage control signal, a detection signal output terminal for outputting residual voltage acquisition signal, a magnetic latching relay, a resistance R1 and a rectifier voltage stabilizing module; the magnetic latching relay comprises: a normally closed contact, a normally open contact, a starting coil and a reset coil; the positive electrode of the sampling terminal is connected with the first input terminal of the rectifier voltage stabilizing module via the resistance R1 and the normally closed contact, and the negative electrode is connected with the second input terminal of the rectifier voltage stabilizing module; the positive electrode of the starting coil is connected with the first output terminal of the rectifier voltage stabilizing module via the capacitor C1, and the negative electrode is connected with the second output terminal of the rectifier voltage stabilizing module; the positive and negative electrodes of the reset coil are connected with the positive and negative electrodes of the control signal input terminal respectively; the two ends of the normally open contact are connected with the positive and negative electrodes of the detection signal output terminal respectively. The utility model can effectively reduce the number of devices required by the residual voltage detection circuit, reduce power consumption and improve response speed.

Description

Technical Field

[0001] This utility model relates to the field of residual pressure monitoring technology, specifically to a residual pressure detection circuit. Background Technology

[0002] In the field of power distribution systems, ensuring the safe and stable operation of power equipment and protecting the lives of personnel are always paramount objectives. With the continuous advancement of smart grid construction, power distribution protection equipment such as feeder terminal units (FTUs) and data transfer units (DTUs) are playing an increasingly crucial role in power distribution automation systems, enabling real-time monitoring, control, and protection of power distribution lines.

[0003] In actual power distribution system operation, residual voltage exists. Residual voltage is the voltage that continues to be maintained briefly after the busbar is disconnected due to energy storage components (such as capacitors and inductors) or distributed power sources (such as capacitive voltage transformers, cable-to-ground capacitance, etc.) in the system. The characteristics of residual voltage are that its amplitude decays over time, its duration is short, and its frequency may deviate from the power frequency (50Hz / 60Hz).

[0004] If there is residual voltage on both sides of the circuit breaker or tie switch, the following risks may occur: First, the residual voltage may cause electric shock to personnel around the power distribution system; second, if the residual voltage is out of phase with the system voltage, it may cause a large current surge during reclosing operation, which may damage the power equipment; in addition, the high-frequency or resonant overvoltage generated after closing may damage high-voltage equipment, thereby affecting the stability and reliability of the entire power distribution system.

[0005] Currently, various residual voltage detection circuits have emerged, but all of them have various problems:

[0006] For example, prior art 1 describes a residual voltage detection and discharge circuit for high-voltage equipment. After detecting high voltage, it outputs corresponding level logic through an operational amplifier and uses a switching transistor to provide a residual voltage discharge path, resulting in faster residual voltage discharge at the high-voltage power supply terminal after power failure. However, this solution requires long-term acquisition of the high-voltage bus voltage, resulting in power loss due to resistance.

[0007] Existing technology 2 describes an inverter and its bus sampling circuit and protection method, including determining the positive half-bus voltage and the negative half-bus voltage of the inverter, then determining the difference between the two half-bus voltages; and outputting a blocking signal when the difference is greater than a preset threshold. However, this scheme has many circuit components, and its reliability is difficult to guarantee after the operational amplifier of the detection bus is damaged.

[0008] Existing technology 3 describes a bus residual voltage discharge circuit that uses an optocoupler to turn on the switching transistor and open the residual voltage discharge path. However, this scheme still requires long-term acquisition of high-voltage bus voltage, and there is power loss in the resistor.

[0009] Therefore, it is necessary to provide improved residual voltage detection or monitoring circuits to more effectively address the risks posed by residual voltage and reduce circuit power consumption. Utility Model Content

[0010] To overcome the shortcomings of the prior art, this utility model proposes a residual voltage detection circuit, which can detect the residual voltage of the circuit breaker and the connection input and output terminals. When residual voltage is detected, it completes the lockout protection state, effectively reduces the number of required components, reduces power consumption, and improves response speed.

[0011] In one embodiment, the residual voltage detection circuit of this utility model includes: a sampling terminal, a control signal input terminal, a detection signal output terminal, a magnetic latching relay, a resistor R1, a rectifier and voltage regulator module, and a capacitor C1; the magnetic latching relay includes: a normally closed contact, a normally open contact, a start coil, and a reset coil;

[0012] The sampling terminal is connected to the PT and is used to sample the bus input voltage or output voltage of any one of the three phases ABC sensed by the PT; the positive terminal of the sampling terminal is connected to the first input terminal of the rectifier and voltage regulator module through resistor R1 and normally closed contact, and the negative terminal of the sampling terminal is connected to the second input terminal of the rectifier and voltage regulator module.

[0013] The positive terminal of the start-up coil is connected to the first output terminal of the rectifier and voltage regulator module via capacitor C1, and the negative terminal of the start-up coil is connected to the second output terminal of the rectifier and voltage regulator module.

[0014] The positive and negative terminals of the return coil are connected to the positive and negative terminals of the control signal input terminal, respectively; the control signal input terminal is used to receive the residual voltage control signal.

[0015] The two ends of the normally open contact are connected to the positive and negative terminals of the detection signal output terminal, respectively; the detection signal output terminal is used to output the residual voltage acquisition signal.

[0016] Preferably, the residual voltage detection circuit further includes a varistor disposed between the positive terminal and the negative terminal of the sampling end.

[0017] Preferably, both the starting coil and the return coil are resistive coils.

[0018] Preferably, the device further includes diodes D1 and D2; the positive and negative terminals of diode D1 are connected to the negative and positive terminals of the starting coil, respectively; the positive and negative terminals of diode D2 are connected to the negative and positive terminals of the resetting coil, respectively.

[0019] Preferably, when the starting coil is energized, the normally closed contact changes from a closed state to an open state, and the normally open contact changes from an open state to a closed state; when the starting coil is de-energized, the normally closed contact remains open, and the normally open contact remains closed; and even if the starting coil is re-energized after the starting coil is de-energized, the normally closed contact remains open, and the normally open contact remains closed, only when the re-energized coil is energized will the normally closed contact change from an open state to a closed state, and the normally open contact change from a closed state to an open state.

[0020] Preferably, the rectifier voltage regulator module includes a rectifier element, a resistor R2, and a capacitor C2; the first and second input terminals of the rectifier element are respectively the first and second input terminals of the rectifier voltage regulator module, the resistor R2 and the capacitor C2 are connected in parallel between the first and second output terminals of the rectifier element, and the first and second output terminals of the rectifier element are respectively led out as the first and second output terminals of the rectifier voltage regulator module.

[0021] Preferably, a TVS is disposed between the first and second output terminals of the rectifier element.

[0022] Preferably, the rectifier includes four identical diodes D3. The first input terminal of the rectifier and voltage regulator module is connected to the cathode of the first diode D3 and the anode of the second diode D3. The second input terminal of the rectifier and voltage regulator module is connected to the cathode of the third diode D3 and the anode of the fourth diode D3. The first output terminal of the rectifier and voltage regulator module is connected to the anode of the first diode D3 and the anode of the third diode D3. The second output terminal of the rectifier and voltage regulator module is connected to the cathode of the second diode D3 and the cathode of the fourth diode D3.

[0023] Preferably, the residual voltage detection circuit further includes a controller; the controller is connected to the PT, the control signal input terminal and the detection signal output terminal respectively, and is used to acquire the bus incoming voltage or outgoing voltage of any one of the three phases ABC, provide a high potential signal VDD to the positive terminal of the control signal input terminal and the positive terminal of the detection signal output terminal, send a residual voltage control signal to the negative terminal of the control signal input terminal, and receive the residual voltage acquisition signal output from the negative terminal of the detection signal output terminal.

[0024] Preferably, the controller is a CPU controller.

[0025] Compared with the prior art, this application has the following significant advantages:

[0026] 1. Fast response and high reliability: The step voltage characteristic of the DC blocking capacitor C1 generates a voltage spike across the starting coil K1A of the magnetic latching relay, thereby triggering the starting coil K1A to open the normally closed contact K1D and close the normally open contact K1C, achieving instantaneous detection of residual voltage with a fast response speed. At the same time, due to the magnetic latching characteristic of the magnetic latching relay, the state can be recorded without continuous power supply, realizing the lockout protection of the residual voltage detection result.

[0027] 2. By setting up a controller and connecting it to the PT, the control signal input terminal, and the detection signal output terminal, intelligent detection of residual pressure can be achieved.

[0028] 3. Fewer components are used: The circuit design is simple, mainly relying on magnetic latching relays and a small number of capacitors, resistors and diodes to realize the residual voltage detection function, which reduces hardware complexity and cost.

[0029] 4. Low power consumption: When the CPU device is working, the residual voltage detection circuit does not work, so there is no power loss. Attached Figure Description

[0030] Figure 1 This is a block diagram illustrating the application principle of the residual voltage detection circuit of this utility model for residual voltage detection.

[0031] Figure 2 This is a circuit diagram of the residual voltage detection circuit of this utility model. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The embodiments described in this application are merely some embodiments of this utility model, not all embodiments. Based on the spirit of this utility model, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this utility model.

[0033] like Figure 1 As shown, taking any one of the three phases (A, B, and C) as an example, the bus voltage of both the incoming and outgoing lines needs to be connected to the residual voltage monitoring device. In practical applications, all three phases (A, B, and C) are connected to the residual voltage monitoring device, and each device has two residual voltage detection circuits, for a total of six residual voltage detection circuits. It should be noted that... Figure 1 The diagram only shows the voltage of one phase out of the three phases A, B, and C.

[0034] like Figure 2As shown, in one embodiment, the residual voltage detection circuit of this utility model specifically includes: a sampling terminal, a control signal input terminal, a detection signal output terminal, a magnetic latching relay, a resistor R1, a rectifier and voltage regulator module ZW, and a capacitor C1; the magnetic latching relay includes: a normally closed contact K1D, a normally open contact K1C, a start coil K1A, and a reset coil K1B.

[0035] The sampling terminal is connected to a PT (Potential Transformer) to sample the bus input or output voltage of any one of the three phases (A, B, and C) sensed by the PT. The positive terminal ACL of the sampling terminal is connected to the first input terminal in1 of the rectifier and voltage regulator module ZW via resistor R1 and normally closed contact K1D, and the negative terminal ACN of the sampling terminal is connected to the second input terminal in2 of the rectifier and voltage regulator module ZW.

[0036] The positive terminal of the start-up coil K1A is connected to the first output terminal o1 of the rectifier and voltage regulator module ZW via capacitor C1, and the negative terminal of the start-up coil K1A is connected to the second output terminal o2 of the rectifier and voltage regulator module ZW.

[0037] The positive and negative terminals of the return coil K1B are connected to the positive and negative terminals of the control signal input terminal, respectively; the control signal input terminal is used to receive the residual voltage control signal.

[0038] The two ends of the normally open contact K1C are connected to the positive and negative terminals of the detection signal output terminal, respectively; the detection signal output terminal is used to output the residual voltage acquisition signal.

[0039] In this embodiment, residual voltage detection can be controlled by receiving a residual voltage control signal at the control signal input terminal. During the residual voltage detection process, when a residual voltage signal is present in the sampled bus input voltage or current voltage, the capacitor voltage of capacitor C1, which is used as a DC blocking capacitor, will exhibit a step characteristic. This step characteristic causes a voltage spike across the starting coil K1A of the magnetic latching relay, thereby triggering the starting coil K1A to operate, causing the normally closed contact K1D to open and the normally open contact K1C to close. Instantaneous detection of residual voltage can be achieved through the detection signal output terminal, with a fast response speed. At the same time, due to the magnetic latching characteristic of the magnetic latching relay, the state can be recorded without continuous power supply, realizing the lockout protection of the residual voltage detection result.

[0040] Furthermore, to prevent surge hazards that may arise from the bus sampling voltage introduced into the residual voltage detection circuit, the residual voltage detection circuit also includes a varistor RV, which is positioned between the positive terminal ACL and the negative terminal ACN of the sampling end. The varistor is model FNR07K681T, and its specifications must be selected according to the actual bus voltage level. In this embodiment, a varistor with a nominal voltage of 680V is selected, suitable for secondary side protection scenarios where the bus voltage is 480Vac after transformation by a PT (voltage transformer). It should be noted that in other embodiments, other models or specifications (nominal voltage) of varistors can also be selected according to specific circumstances.

[0041] In this embodiment, resistor R1 is used as a current-limiting resistor and can be implemented using a 1K ohm power resistor. This value can better reduce the inrush current during application. It should be noted that in other embodiments, resistor R1 can also be a power resistor of other values ​​depending on the specific situation. This resistance value should not be too large, but it must be greater than the minimum current requirement of the relay coil after the residual voltage appears. For reference, the rated current of the relay coil in this embodiment is I = 24 / 1920 = 12.5mA.

[0042] In this embodiment, the magnetic latching relay is model DSP1-L2-DC24V-F. Figure 2 Both the starting coil K1A and the return coil K1B are resistive coils with a rated voltage of 24V, and are controlled by a dual-coil system. The normally closed contact K1D is closed when the residual voltage circuit begins to operate, while the normally open contact K1C is open. Energizing either the starting coil K1A or the return coil K1B will activate both sets of contacts and maintain their respective states. For example, after the starting coil K1A is energized, contact K1D changes from closed to open, and contact K1C changes from open to closed. After the starting coil K1A is de-energized, normally closed contact K1D remains open, and normally open contact K1C remains closed. Even if the starting coil K1A is re-energized after it is de-energized, normally closed contact K1D remains open, and normally open contact K1C remains closed. Only when the reset coil K1B is energized does normally closed contact K1D change from open to closed, and contact K1C change from closed to open.

[0043] In this embodiment, the rectifier and voltage regulator module ZW includes a rectifier element, a resistor R2, and a capacitor C2. The first and second input terminals of the rectifier element are respectively the first input terminal in1 and the second input terminal in2 of the rectifier and voltage regulator module ZW. The resistor R2 and the capacitor C2 are connected in parallel between the first and second output terminals of the rectifier element, and the first and second output terminals of the rectifier element are respectively led out as the first output terminal o1 and the second output terminal o2 of the rectifier and voltage regulator module ZW.

[0044] Furthermore, the rectifier includes four identical diodes D3. The first input terminal in1 of the rectifier and voltage regulator module ZW is connected to the cathode of the first diode D3 and the anode of the second diode D3. The second input terminal in2 of the rectifier and voltage regulator module ZW is connected to the cathode of the third diode D3 and the anode of the fourth diode D3. The first output terminal o1 of the rectifier and voltage regulator module ZW is connected to the anode of the first diode D3 and the anode of the third diode D3. The second output terminal o2 of the rectifier and voltage regulator module ZW is connected to the cathode of the second diode D3 and the cathode of the fourth diode D3.

[0045] By setting up the rectifier and voltage regulator module ZW, the unstable sampling voltage can be converted into a stable and reliable DC current, thus better realizing residual voltage detection. When selecting the specifications of diode D3, resistor R2, and capacitor C2, surface-mount packages should be prioritized, ensuring they are suitable for low-current operating scenarios to reduce circuit power consumption. Furthermore, the selected components must meet the circuit's voltage regulation requirements.

[0046] To further prevent potential surge damage from the bus sampling voltage, a TVS (Transient Voltage Suppressor) can be placed between the first and second output terminals of the rectifier element. It should be noted that in other embodiments, either the varistor RV or the TVS can be used; however, in practical applications, the varistor is more commonly chosen.

[0047] Furthermore, the residual voltage detection circuit in this embodiment also includes diodes D1 and D2. The anode and cathode of diode D1 are connected to the cathode and anode of the starting coil K1A, respectively; the anode and cathode of diode D2 are connected to the cathode and anode of the return coil K1B, respectively. In this way, diodes D1 and D2 are used as clamping diodes, preferably of model 1SMA5935BT3G. Clamping diodes D1 and D2 can clamp the voltage across the starting coil K1A and return coil K1B, which are connected in parallel with them, within a preset range, i.e., suppressing their maximum voltage and protecting them from overvoltage damage. It should be noted that in other embodiments, diodes D1 and D2 may be of other models as needed.

[0048] In this embodiment, capacitor C1 is used as a DC blocking capacitor. When residual voltage occurs, the capacitor voltage of C1 exhibits a step characteristic, causing a spike level at the end of the starting coil K1A connected to capacitor C1. The positive terminal of capacitor C1 is connected to the first output terminal o1 of the rectifier and voltage regulator circuit, and the negative terminal of capacitor C1 is connected to the positive terminal of the starting coil K1A. The capacitance of capacitor C1 is 10uF, which is selected based on the coil resistance of the magnetic latching relay. For reference, in this embodiment, the coil resistance of the magnetic latching relay is 1920 ohms, and the corresponding excitation voltage of the relay coil is approximately τ = 10^(-6) × 1920 = 0.00192V. It should be noted that in other embodiments, capacitor C1 may also be of other models and specifications depending on the specific circumstances.

[0049] To achieve intelligent control of residual voltage detection, a controller is also provided in this embodiment. This controller is connected to the control signal input terminal and detection signal output terminal of the PT (Potential Transmission Unit), the residual voltage detection circuit, and respectively. It obtains the bus input or output voltage of any one of the three phases (A, B, and C) from the PT, provides a high-potential signal VDD (24V in this embodiment) to the positive terminal of the control signal input terminal and the positive terminal of the detection signal output terminal, sends a residual voltage control signal CY_CTRL to the negative terminal of the control signal input terminal, and receives the residual voltage acquisition signal CY_DIN output from the detection signal output terminal. The controller can be, for example, a CPU (Central Processing Unit), and the high-potential signal VDD is actually the power supply provided by the CPU, with a value of 24V.

[0050] In this embodiment, the reset coil K1B in the residual voltage detection circuit is controlled by the CPU. When the CPU starts up, it checks whether the normally open contact K1C is closed and checks the voltage of the bus input and output lines. If the check is normal, the CPU issues a residual voltage control command (i.e., sets the residual voltage control signal CY_CTRL=0) to energize the reset coil K1B, thereby causing the normally closed contact K1D to close again and the normally open contact K1C to open again, thus performing residual voltage detection.

[0051] In this embodiment, the specific usage method of the residual voltage detection circuit is described as follows:

[0052] 1. Under normal operating conditions of the CPU and circuitry, the residual voltage control signal CY_CTRL = 1 (i.e., a given 24V). The reset coil K1B is not energized, the normally closed contact K1D is open, and the residual voltage detection circuit is not working. Since residual voltage was previously detected, the normally open contact K1C is closed, the residual voltage acquisition signal CY_DIN = 24V, and the CPU acquires the corresponding status.

[0053] 2. Before the circuit breaker or tie switch is put into operation in the open state, when the CPU device detects that the voltage of the incoming and outgoing busbars is zero, the CPU device controls the residual voltage control signal CY_CTRL = 0 (i.e., given 0V). At this time, the reset coil K1B is energized, the normally closed contact K1D is in the closed state, and the residual voltage detection circuit works. The normally open contact K1C changes from the closed state to the open state.

[0054] 3. When residual voltage is generated on the bus, the bus voltage will rise rapidly. At this time, the voltage across capacitor C1 cannot change abruptly. When a step signal appears at the positive terminal of capacitor C1, a voltage spike will appear at the end of the starting coil K1A connected to capacitor C1. When this peak value reaches the minimum excitation voltage threshold of the starting coil K1A, the normally closed contact K1D opens and the normally open contact K1C closes. At this time, the residual voltage acquisition signal CY_DIN = 24V, and the CPU acquires the corresponding status.

[0055] 4. When the CPU device loses voltage and is in a non-operating state, the reset coil K1B demagnetizes, the normally open contact K1C opens, and the normally closed contact K1D closes. When residual voltage appears on the bus, the normally closed contact K1D opens, and the normally open contact K1C closes. When the CPU device is powered on again, it will detect that the normally open contact K1C has activated and record the residual voltage condition on the bus. At this time, the voltage of the incoming and outgoing bus lines must be checked again. When the voltage of the incoming and outgoing bus lines is detected to be zero again, the CPU device will control the residual voltage control signal CY_CTRL = 0. The reset coil K1B is re-energized, causing the normally closed contact K1D to change from the open state to the closed state, and the residual voltage detection circuit is put back into operation.

[0056] Therefore, compared with the prior art, the advantages of this application are as follows:

[0057] 1. Fast response and high reliability: The step voltage characteristic of the DC blocking capacitor C1 generates a voltage spike across the starting coil K1A of the magnetic latching relay, thereby triggering the starting coil K1A to open the normally closed contact K1D and close the normally open contact K1C, achieving instantaneous detection of residual voltage with a fast response speed. At the same time, due to the magnetic latching characteristic of the magnetic latching relay, the state can be recorded without continuous power supply, realizing the lockout protection of the residual voltage detection result.

[0058] 2. By setting up a controller and connecting it to the PT, the control signal input terminal, and the detection signal output terminal, intelligent detection of residual pressure can be achieved.

[0059] 3. Fewer components are used: The circuit design is simple, mainly relying on magnetic latching relays and a small number of capacitors, resistors and diodes to realize the residual voltage detection function, which reduces hardware complexity and cost.

[0060] 4. Low power consumption: When the CPU device is working, the residual voltage detection circuit does not work, so there is no power loss.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of this utility model and not to limit it. Although the utility model has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this utility model. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this utility model should be covered within the protection scope of the claims of this utility model.

Claims

1. A residual voltage detection circuit, characterized in that, include: The system includes a sampling terminal, a control signal input terminal, a detection signal output terminal, a magnetic latching relay, a resistor R1, a rectifier and voltage regulator module, and a capacitor C1. The magnetic latching relay includes a normally closed contact, a normally open contact, a start coil, and a reset coil. The sampling terminal is connected to the PT and is used to sample the bus input voltage or output voltage of any one of the three phases ABC sensed by the PT; the positive terminal of the sampling terminal is connected to the first input terminal of the rectifier and voltage regulator module through resistor R1 and normally closed contact, and the negative terminal of the sampling terminal is connected to the second input terminal of the rectifier and voltage regulator module. The positive terminal of the start-up coil is connected to the first output terminal of the rectifier and voltage regulator module via capacitor C1, and the negative terminal of the start-up coil is connected to the second output terminal of the rectifier and voltage regulator module. The positive and negative terminals of the return coil are connected to the positive and negative terminals of the control signal input terminal, respectively; the control signal input terminal is used to receive the residual voltage control signal. The two ends of the normally open contact are connected to the positive and negative terminals of the detection signal output terminal, respectively; the detection signal output terminal is used to output the residual voltage acquisition signal.

2. The residual voltage detection circuit according to claim 1, characterized in that, It also includes a varistor, which is placed between the positive and negative terminals of the sampling end.

3. The residual voltage detection circuit according to claim 1, characterized in that, Both the starting coil and the return coil are resistive coils.

4. The residual voltage detection circuit according to claim 1, characterized in that, It also includes diodes D1 and D2; the positive and negative terminals of diode D1 are connected to the negative and positive terminals of the starting coil, respectively; the positive and negative terminals of diode D2 are connected to the negative and positive terminals of the resetting coil, respectively.

5. The residual voltage detection circuit according to claim 1, characterized in that, When the starting coil is energized, the normally closed contact changes from closed to open, and the normally open contact changes from open to closed. When the starting coil is de-energized, the normally closed contact remains open, and the normally open contact remains closed. Furthermore, even if the starting coil is re-energized after de-energization, the normally closed contact remains open, and the normally open contact remains closed. Only when the re-energized coil is re-energized will the normally closed contact change from open to closed, and the normally open contact change from closed to open.

6. The residual voltage detection circuit according to claim 1, characterized in that, The rectifier and voltage regulator module includes a rectifier element, a resistor R2, and a capacitor C2. The first and second input terminals of the rectifier element are the first and second input terminals of the rectifier and voltage regulator module, respectively. The resistor R2 and the capacitor C2 are connected in parallel between the first and second output terminals of the rectifier element, and the first and second output terminals of the rectifier element are respectively led out as the first and second output terminals of the rectifier and voltage regulator module.

7. The residual voltage detection circuit according to claim 6, characterized in that, A TVS is provided between the first and second output terminals of the rectifier element.

8. The residual voltage detection circuit according to claim 6, characterized in that, The rectifier includes four identical diodes D3. The first input terminal of the rectifier and voltage regulator module is connected to the cathode of the first diode D3 and the anode of the second diode D3. The second input terminal of the rectifier and voltage regulator module is connected to the cathode of the third diode D3 and the anode of the fourth diode D3. The first output terminal of the rectifier and voltage regulator module is connected to the anodes of the first diode D3 and the third diode D3. The second output terminal of the rectifier and voltage regulator module is connected to the cathodes of the second diode D3 and the fourth diode D3.

9. The residual voltage detection circuit according to claim 1, characterized in that, It also includes a controller; the controller is connected to the PT, the control signal input terminal and the detection signal output terminal respectively, to obtain the bus incoming voltage or outgoing voltage of any one of the three phases ABC from the PT, to provide a high potential signal VDD to the positive terminal of the control signal input terminal and the positive terminal of the detection signal output terminal, to send a residual voltage control signal to the negative terminal of the control signal input terminal, and to receive the residual voltage acquisition signal output from the negative terminal of the detection signal output terminal.

10. The residual voltage detection circuit according to claim 9, characterized in that, The controller is a CPU controller.

Images