A tri-state input detection circuit

Abstract

The utility model relates to input level state detection technical field discloses a kind of tri-state input detection circuit, including MOS tube M1, MOS tube M2, first voltage dividing unit, second voltage dividing unit, third voltage dividing unit, comparator CMP1 and comparator CMP2;For the circuit of the utility model, the reference voltage size input to comparator CMP1 and comparator CMP2 can be specifically set by setting MOS tube M2, second voltage dividing unit and third voltage dividing unit, MOS tube M1 and first voltage dividing unit can be set to input different size detection voltage to comparator CMP1 and comparator CMP2 when the gate of MOS tube M1 inputs 1-3V high level signal and is high resistance state, to realize accurate level state detection.

Description

Technical Field

[0001] This utility model relates to the field of input level state detection technology, specifically to a three-state input detection circuit. Background Technology

[0002] In electronic circuits, processors such as MCUs often need to detect the state of the input level of external circuits in order to execute relevant control strategies. The input state of external circuits includes three basic logic states: high level, low level, and high impedance. The high impedance state is also called the floating state.

[0003] The circuit diagram of the existing three-state detection circuit is as follows: Figure 1 As shown, in Figure 1 In the circuit, resistors R1 and R2 are connected in series to ensure that the input signal Vin has a defined voltage of 0.5Vdd even when it is floating. Resistors R3, R4, and R5 form a voltage divider network to provide a reference voltage. The reference voltage input to the positive input terminal of comparator 11 is 0.7Vdd, and the reference voltage input to the negative input terminal of comparator 12 is 0.3Vdd. Comparator 11 and comparator 12 compare the input signal Vin with two reference voltages, respectively. The three states of the input signal can be represented by combining the output states of the two comparators.

[0004] for Figure 1 The circuit shown has three input states: low level, high impedance, and high level Vdd. If Vdd = 3V, and the high-level input signal Vin is applied within a range of 1V-3V, the circuit cannot accurately identify the high level, resulting in a detection failure. Therefore, existing three-state input detection circuits will experience false detections when the voltage input to the comparator in both the high-impedance and high-level states exceeds the reference voltages of both comparator inputs. Utility Model Content

[0005] In view of the shortcomings of the prior art, this utility model provides a three-state input detection circuit. The technical problem to be solved is that when the voltage input to the comparator in the high impedance state and the voltage input to the comparator in the high level state both exceed the reference voltages of the two comparator inputs, false detection will occur.

[0006] To solve the above technical problems, this utility model provides the following technical solution: a three-state input detection circuit, including MOSFET M1, MOSFET M2, a first voltage divider unit, a second voltage divider unit, a third voltage divider unit, a comparator CMP1, and a comparator CMP2; The input terminals of the first voltage divider unit and the second voltage divider unit are electrically connected to each other for inputting the power supply voltage Vdd; The voltage divider nodes of the first voltage divider unit are electrically connected to the negative input terminal of comparator CMP1, the positive input terminal of comparator CMP1, and the drain of MOSFET M1, respectively; the output terminal of the first voltage divider unit is electrically connected to the gate of MOSFET M1 and is used to input the signal Vin to be detected; the source of MOSFET M1 is grounded. The voltage dividing node of the second voltage divider unit is electrically connected to the positive input terminal of comparator CMP1; the output terminal of the second voltage divider unit is electrically connected to the input terminal of the third voltage divider unit, the drain of MOSFET M2, and the drain of MOSFET M3, respectively; the voltage dividing node of the third voltage divider unit is electrically connected to the negative input terminal of comparator CMP2, and the output terminal of the third voltage divider unit and the source of MOSFET M2 are both grounded.

[0007] In one embodiment, the MOS transistor M1 is an NMOS transistor.

[0008] In one embodiment, the MOS transistor M2 is an NMOS transistor.

[0009] In one embodiment, the first voltage divider unit includes resistors R1 and R4 with the same resistance value. One end of resistor R1 is the input terminal of the first voltage divider unit, and the other end of resistor R1 is the voltage dividing node of the first voltage divider unit and is electrically connected to one end of resistor R4. The other end of resistor R4 is the output terminal of the first voltage divider unit.

[0010] In one embodiment, the second voltage divider unit includes resistors R2 and R3 with the same resistance value. One end of resistor R2 is the input terminal of the second voltage divider unit, and the other end of resistor R2 is the voltage dividing node of the second voltage divider unit and is electrically connected to one end of resistor R3. The other end of resistor R3 is the output terminal of the second voltage divider unit.

[0011] In one embodiment, the third voltage divider unit includes resistors R5 and R6 with the same resistance value. One end of resistor R5 is the input terminal of the third voltage divider unit, and the other end of resistor R5 is the voltage divider node of the third voltage divider unit and is electrically connected to one end of resistor R6. The other end of resistor R6 is the output terminal of the third voltage divider unit.

[0012] In one embodiment, when the power supply voltage Vdd is a 3V DC voltage, the reference voltage input to the positive input terminal of comparator CMP1 is 1.2V, and the voltage input to the negative input terminal of comparator CMP2 is 0.6V.

[0013] In one embodiment, the resistance of resistor R2 is half the resistance of resistor R1, and the sum of the resistances of resistors R5 and R6 is greater than ten times RDS2, where RDS2 is the drain-source impedance of MOSFET M2.

[0014] In one embodiment, the comparator CMP1 includes a MOS transistor MP1; The source of MOSFET MP1 is electrically connected to the sources of MOSFET MP2, MOSFET MP3, MOSFET MP4, MOSFET MP5 and MOSFET MP6 respectively, for connection to the power supply voltage Vdd. The gate of MOS transistor MP1 is electrically connected to the gate of MOS transistor MP2, the drain of MOS transistor MP2, the drain of MOS transistor MP3, the gate of MOS transistor MP4, and the drain of MOS transistor MN1, respectively. The gate of MOS transistor MP3 is electrically connected to the drain of MOS transistor MP4, the drain of MOS transistor MP5, the gate of MOS transistor MP5, the gate of MOS transistor MP6, and the drain of MOS transistor MN2, respectively. The drain of MOS transistor MP1 is electrically connected to the drain of MOS transistor MN3, the gate of MOS transistor MN3, and the gate of MOS transistor MN4, respectively; the drain of MOS transistor MP6 is electrically connected to the drain of MOS transistor MN4 and serves as the output terminal of comparator CMP1; the sources of MOS transistor MN3 and MOS transistor MN4 are both grounded. The gate of the MOS transistor MN1 is electrically connected to the voltage divider node of the first voltage divider unit, and the gate of the MOS transistor MN2 is electrically connected to the voltage divider node of the second voltage divider unit. The source of both the MOS transistor MN1 and the source of the MOS transistor MN2 are electrically connected to one end of the resistor R7, and the other end of the resistor R7 is grounded.

[0015] In one embodiment, the comparator CMP2 includes a resistor R8; One end of the resistor R8 is electrically connected to the source of MOSFET MP9 and the source of MOSFET MP10 respectively, for use in connecting the power supply voltage Vdd. The other end of the resistor R8 is electrically connected to the source of the MOSFET MP7 and the source of the MOSFET MP8, respectively. The gate of the MOS transistor MP7 is electrically connected to the voltage divider node of the third voltage divider unit, and the gate of the MOS transistor MP8 is electrically connected to the voltage divider node of the first voltage divider unit. The drain of MOS transistor MP7 is electrically connected to the drain of MOS transistor MN5, the drain of MOS transistor MN6, the drain of MOS transistor MN7, and the gate of MOS transistor MN8, respectively. The drain of the MOS transistor MP8 is electrically connected to the gate of the MOS transistor MN10, the drain of the MOS transistor MN9, the drain of the MOS transistor MN8, and the gate of the MOS transistor MN7, respectively. The sources of MOS transistors MN5, MN6, MN7, MN8, MN9, and MN10 are all grounded. The drain of MOS transistor MN5 is electrically connected to the drain of MOS transistor MP9, the gate of MOS transistor MP9, and the gate of MOS transistor MP10, respectively. The drain of the MOS transistor MN10 is electrically connected to the drain of the MOS transistor MP10, which is the output terminal of the comparator CMP2.

[0016] The beneficial effects of this utility model compared with the prior art are as follows: For the circuit of this utility model, by setting MOS transistor M2, the second voltage divider unit and the third voltage divider unit, the reference voltage input to comparator CMP1 and comparator CMP2 can be specifically set. By setting MOS transistor M1 and the first voltage divider unit, different detection voltages can be input to comparator CMP1 and comparator CMP2 when a high-level signal of 1-3V is input to the gate of MOS transistor M1 and when it is in a high-impedance state, thereby achieving accurate level state detection. Attached Figure Description

[0017] Figure 1 The circuit diagram is for an existing three-state detection circuit. Figure 2 This is a schematic diagram of the structure of the present invention in the embodiments; Figure 3 This is a circuit diagram of comparator CMP1 in the embodiment; Figure 4 This is a circuit diagram of comparator CMP2 in the embodiment. Detailed Implementation

[0018] The illustrative embodiments of this application include, but are not limited to, a three-state input detection circuit.

[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0020] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. Words such as “comprising” or “including” mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and does not exclude other elements or objects. Words such as “connected” or “linked” are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0021] When performing three-state detection of input signals, in order to avoid the influence of the high-level voltage range on the detection results, it is necessary to accurately detect the three level states, such as... Figure 2 As shown, this embodiment provides a tri-state input detection circuit, including MOSFET M1, MOSFET M2, a first voltage divider unit 1, a second voltage divider unit 2, a third voltage divider unit 3, a comparator CMP1, and a comparator CMP2; The input terminal of the first voltage divider unit 1 and the input terminal of the second voltage divider unit 2 are electrically connected to each other for inputting the power supply voltage Vdd; The voltage divider nodes of the first voltage divider unit 1 are electrically connected to the negative input terminal of comparator CMP1, the positive input terminal of comparator CMP1, and the drain of MOSFET M1, respectively; the output terminal of the first voltage divider unit 1 is electrically connected to the gate of MOSFET M1 and is used to input the signal Vin to be detected; the source of MOSFET M1 is grounded. The voltage dividing node of the second voltage divider unit 2 is electrically connected to the positive input terminal of comparator CMP1; the output terminal of the second voltage divider unit 2 is electrically connected to the input terminal of the third voltage divider unit 3, the drain of MOSFET M2, and the drain of MOSFET M3, respectively; the voltage dividing node of the third voltage divider unit 3 is electrically connected to the negative input terminal of comparator CMP2, and the output terminal of the third voltage divider unit 3 and the source of MOSFET M2 are both grounded.

[0022] In practical use, this invention can specifically set the reference voltage input to comparators CMP1 and CMP2 by setting MOS transistor M2, second voltage divider unit 2 and third voltage divider unit 3. By setting MOS transistor M1 and first voltage divider unit 1, different detection voltages can be input to comparators CMP1 and CMP2 when a high-level signal of 1-3V is input to the gate of MOS transistor M1 and when it is in a high-impedance state, thereby achieving accurate level state detection.

[0023] Specifically, in this embodiment, MOS transistor M1 is an NMOS transistor; MOS transistor M2 is an NMOS transistor.

[0024] Specifically, in this embodiment, in Figure 2 In the first voltage divider unit 1, there are resistors R1 and R4 with the same resistance value. One end of resistor R1 is the input terminal of the first voltage divider unit 1, and the other end of resistor R1 is the voltage divider node of the first voltage divider unit 1 and is electrically connected to one end of resistor R4. The other end of resistor R4 is the output terminal of the first voltage divider unit 1.

[0025] Specifically, in this embodiment, in Figure 2 In the second voltage divider unit 2, there are resistors R2 and R3 with the same resistance value. One end of resistor R2 is the input terminal of the second voltage divider unit 2, and the other end of resistor R2 is the voltage divider node of the second voltage divider unit 2 and is electrically connected to one end of resistor R3. The other end of resistor R3 is the output terminal of the second voltage divider unit 2.

[0026] Specifically, in this embodiment, in Figure 2 In the third voltage divider unit 3, there are resistors R5 and R6 with the same resistance value. One end of resistor R5 is the input terminal of the third voltage divider unit 3, and the other end of resistor R5 is the voltage divider node of the third voltage divider unit 3 and is electrically connected to one end of resistor R6. The other end of resistor R6 is the output terminal of the third voltage divider unit 3.

[0027] In this embodiment, the resistance values ​​of the resistors in the first voltage divider unit 1, the second voltage divider unit 2, and the third voltage divider unit 3 are related as follows: the resistance value of resistor R2 is half the resistance value of resistor R1, and the sum of the resistance values ​​of resistors R5 and R6 is greater than ten times RDS2, where RDS2 is the drain-source impedance of MOS transistor M2.

[0028] In this embodiment, the resistance values ​​of resistors R2 and R3, as well as the width-to-length ratio of MOSFET M2, are set so that MOSFET M2 operates in the saturation region, resulting in a VGS2 of MOSFET M2 of 0.6V. Consequently, the reference voltage input to the positive input terminal of comparator CMP1 is 1.2V, and the voltage input to the negative input terminal of comparator CMP2 is 0.6V, thus enabling accurate setting of the reference voltage values ​​input to comparators CMP1 and CMP2.

[0029] In one implementation, the resistance ratio of resistor R2 to resistor R3 and the resistance ratio of resistor R5 to resistor R6 can be set to other ratios, thereby changing the magnitude of the reference voltage input to comparators CMP1 and CMP2.

[0030] In this embodiment, a voltage divider unit formed by resistors connected in series is used to input voltage to the comparator. Thus, when the power supply voltage Vdd changes, the voltage input to the comparator also changes because the voltage divider ratio is set, and three-state detection can still be achieved, making it highly applicable.

[0031] In this embodiment, Figure 2 The detection process for the circuit shown is as follows: When the signal Vin to be detected is in a high-impedance state, i.e., a floating state, the output voltage VB of the voltage divider node B of the first voltage divider unit 1 is VGS1, where VGS1 is the gate-source threshold voltage of the MOS transistor M1, which is 0.6V; at this time, comparators CMP1 and CMP2 output high-level signals respectively. When the signal Vin to be detected is low, MOSFET M1 is turned off. Since the resistance values ​​of resistor R1 and resistor R4 are the same, the output voltage VB of the first voltage divider node 1 is 1.5V, which causes comparator CMP1 to output a low-level signal and comparator CMP2 to output a high-level signal. When the signal Vin to be detected is at a high level of 1-3V, the resistance values ​​of resistors R1 and R4 are set so that MOSFET M1 operates in the deep linear region. At this time, the on-resistance of MOSFET M1 is extremely low, and the output voltage VB is approximately 0V. At this time, comparator CMP1 outputs a high-level signal, causing comparator CMP2 to output a low-level signal.

[0032] In summary, when the signal Vin to be detected is in a high impedance state, a low level state, or a high level state, comparators CMP1 and CMP2 can output the corresponding detection signal, thus achieving accurate three-state detection.

[0033] In this embodiment, the circuit of comparator CMP1 is as follows: Figure 3 As shown, it includes MOSFET MP1; The source of MOSFET MP1 is electrically connected to the sources of MOSFETs MP2, MP3, MP4, MP5, and MP6, respectively, for connection to the power supply voltage Vdd. The gate of MOSFET MP1 is electrically connected to the gate of MOSFET MP2, the drain of MOSFET MP2, the drain of MOSFET MP3, the gate of MOSFET MP4, and the drain of MOSFET MN1, respectively. The gate of MOSFET MP3 is electrically connected to the drain of MOSFET MP4, the drain of MOSFET MP5, the gate of MOSFET MP5, the gate of MOSFET MP6, and the drain of MOSFET MN2, respectively. The drain of MOSFET MP1 is electrically connected to the drain of MOSFET MN3, the gate of MOSFET MN3, and the gate of MOSFET MN4, respectively; the drain of MOSFET MP6 is electrically connected to the drain of MOSFET MN4, and is the output terminal of comparator CMP1; the source of MOSFET MN3 and the source of MOSFET MN4 are both grounded. The gate of MOS transistor MN1 is electrically connected to the voltage divider node of the first voltage divider unit 1, and the gate of MOS transistor MN2 is electrically connected to the voltage divider node of the second voltage divider unit 2. The sources of MOS transistors MN1 and MN2 are both electrically connected to one end of resistor R7, and the other end of resistor R7 is grounded.

[0034] for Figure 3 In the circuit shown, MOSFETs MP1-MP6 are all PMOS transistors, MOSFETs MN1-MN4 are all NMOS transistors, and MOSFETs MP3 and MP4 are a cross-coupled pair, which act as a load to provide output impedance and gain. In actual operation, if the output voltage VA of the voltage divider node of the second voltage divider unit is greater than VB, then the current flowing through MOSFET MN2 is greater than the current flowing through MOSFET MN1. The current of MOSFET MN2 is copied to MOSFET MP6 through the current mirror, and the current of MOSFET MN1 is copied to MOSFET MN4 through the current mirror. That is, the current of MP6 is greater than the current of MN4, so the output OUT1 will be pulled up to a high level. If VB > VA, then similarly, the current flowing through MOSFET MN4 is greater than the current flowing through MOSFET MP6, and output OUT1 is pulled down to a low level.

[0035] In this embodiment, the circuit of comparator CMP2 is as follows: Figure 4 As shown, it includes resistor R8; One end of resistor R8 is electrically connected to the source of MOSFET MP9 and the source of MOSFET MP10 respectively, for use in connecting the power supply voltage Vdd; The other end of resistor R8 is electrically connected to the source of MOSFET MP7 and the source of MOSFET MP8, respectively. The gate of MOSFET MP7 is electrically connected to the voltage divider node of the third voltage divider unit 3, and the gate of MOSFET MP8 is electrically connected to the voltage divider node of the first voltage divider unit 1. The drain of MOSFET MP7 is electrically connected to the drain of MOSFET MN5, the drain of MOSFET MN6, the drain of MOSFET MN7, and the gate of MOSFET MN8, respectively. The drain of MOSFET MP8 is electrically connected to the gate of MOSFET MN10, the drain of MOSFET MN9, the drain of MOSFET MN8, and the gate of MOSFET MN7, respectively. The sources of MOSFETs MN5, MN6, MN7, MN8, MN9, and MN10 are all grounded. The drain of MOSFET MN5 is electrically connected to the drain of MOSFET MP9, the gate of MOSFET MP9, and the gate of MOSFET MP10, respectively. The drain of MOSFET MN10 is electrically connected to the drain of MOSFET MP10, which is the output terminal of comparator CMP2.

[0036] exist Figure 4 In the diagram, MOSFETs MP7-MP10 are all PMOS transistors, and MOSFETs MN5-MN10 are all NMOS transistors. The functions of MOSFETs MN7 and MN8 are the same as those of MOSFETs MP3 and MP4. Furthermore, the working principles of comparators CMP1 and CMP2 are the same, so they will not be described further here.

[0037] Based on the above description and inspired by this utility model, those skilled in the art can make various changes and modifications without departing from the technical concept of this utility model. The technical scope of this utility model is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A three-state input detection circuit, characterized in that, It includes MOSFET M1, MOSFET M2, first voltage divider unit, second voltage divider unit, third voltage divider unit, comparator CMP1, and comparator CMP2; The input terminals of the first voltage divider unit and the second voltage divider unit are electrically connected to each other for inputting the power supply voltage Vdd; The voltage divider nodes of the first voltage divider unit are electrically connected to the negative input terminal of comparator CMP1, the positive input terminal of comparator CMP1, and the drain of MOSFET M1, respectively; the output terminal of the first voltage divider unit is electrically connected to the gate of MOSFET M1 and is used to input the signal Vin to be detected; the source of MOSFET M1 is grounded. The voltage dividing node of the second voltage divider unit is electrically connected to the positive input terminal of comparator CMP1; the output terminal of the second voltage divider unit is electrically connected to the input terminal of the third voltage divider unit, the drain of MOSFET M2, and the drain of MOSFET M3, respectively; the voltage dividing node of the third voltage divider unit is electrically connected to the negative input terminal of comparator CMP2, and the output terminal of the third voltage divider unit and the source of MOSFET M2 are both grounded.

2. The tri-state input detection circuit according to claim 1, characterized in that, The MOS transistor M1 is an NMOS transistor.

3. The tri-state input detection circuit according to claim 1, characterized in that, The MOS transistor M2 is an NMOS transistor.

4. The tri-state input detection circuit according to claim 1, characterized in that, The first voltage divider unit includes resistors R1 and R4 with the same resistance value. One end of resistor R1 is the input terminal of the first voltage divider unit, and the other end of resistor R1 is the voltage divider node of the first voltage divider unit and is electrically connected to one end of resistor R4. The other end of resistor R4 is the output terminal of the first voltage divider unit.

5. A three-state input detection circuit according to claim 4, characterized in that, The second voltage divider unit includes resistors R2 and R3 with the same resistance value. One end of resistor R2 is the input terminal of the second voltage divider unit, and the other end of resistor R2 is the voltage divider node of the second voltage divider unit and is electrically connected to one end of resistor R3. The other end of resistor R3 is the output terminal of the second voltage divider unit.

6. A three-state input detection circuit according to claim 5, characterized in that, The third voltage divider unit includes resistors R5 and R6 with the same resistance value. One end of resistor R5 is the input terminal of the third voltage divider unit, and the other end of resistor R5 is the voltage divider node of the third voltage divider unit and is electrically connected to one end of resistor R6. The other end of resistor R6 is the output terminal of the third voltage divider unit.

7. A three-state input detection circuit according to claim 6, characterized in that, When the power supply voltage Vdd is 3V DC, the reference voltage input to the positive input terminal of comparator CMP1 is 1.2V, and the voltage input to the negative input terminal of comparator CMP2 is 0.6V.

8. A three-state input detection circuit according to claim 7, characterized in that, The resistance of resistor R2 is half the resistance of resistor R1, and the sum of the resistances of resistors R5 and R6 is greater than ten times RDS2, where RDS2 is the drain-source impedance of MOSFET M2.

9. A three-state input detection circuit according to any one of claims 1-8, characterized in that, The comparator CMP1 includes a MOSFET MP1; The source of MOSFET MP1 is electrically connected to the sources of MOSFET MP2, MOSFET MP3, MOSFET MP4, MOSFET MP5 and MOSFET MP6 respectively, for connection to the power supply voltage Vdd. The gate of MOS transistor MP1 is electrically connected to the gate of MOS transistor MP2, the drain of MOS transistor MP2, the drain of MOS transistor MP3, the gate of MOS transistor MP4, and the drain of MOS transistor MN1, respectively. The gate of MOS transistor MP3 is electrically connected to the drain of MOS transistor MP4, the drain of MOS transistor MP5, the gate of MOS transistor MP5, the gate of MOS transistor MP6, and the drain of MOS transistor MN2, respectively. The drain of MOS transistor MP1 is electrically connected to the drain of MOS transistor MN3, the gate of MOS transistor MN3, and the gate of MOS transistor MN4, respectively; the drain of MOS transistor MP6 is electrically connected to the drain of MOS transistor MN4 and serves as the output terminal of comparator CMP1; the sources of MOS transistor MN3 and MOS transistor MN4 are both grounded. The gate of the MOS transistor MN1 is electrically connected to the voltage divider node of the first voltage divider unit, and the gate of the MOS transistor MN2 is electrically connected to the voltage divider node of the second voltage divider unit. The source of both the MOS transistor MN1 and the source of the MOS transistor MN2 are electrically connected to one end of the resistor R7, and the other end of the resistor R7 is grounded.

10. A three-state input detection circuit according to any one of claims 1-8, characterized in that, The comparator CMP2 includes a resistor R8; One end of the resistor R8 is electrically connected to the source of MOSFET MP9 and the source of MOSFET MP10 respectively, for use in connecting the power supply voltage Vdd. The other end of the resistor R8 is electrically connected to the source of the MOSFET MP7 and the source of the MOSFET MP8, respectively. The gate of the MOS transistor MP7 is electrically connected to the voltage divider node of the third voltage divider unit, and the gate of the MOS transistor MP8 is electrically connected to the voltage divider node of the first voltage divider unit. The drain of MOS transistor MP7 is electrically connected to the drain of MOS transistor MN5, the drain of MOS transistor MN6, the drain of MOS transistor MN7, and the gate of MOS transistor MN8, respectively. The drain of the MOS transistor MP8 is electrically connected to the gate of the MOS transistor MN10, the drain of the MOS transistor MN9, the drain of the MOS transistor MN8, and the gate of the MOS transistor MN7, respectively. The sources of MOS transistors MN5, MN6, MN7, MN8, MN9, and MN10 are all grounded. The drain of MOS transistor MN5 is electrically connected to the drain of MOS transistor MP9, the gate of MOS transistor MP9, and the gate of MOS transistor MP10, respectively. The drain of the MOS transistor MN10 is electrically connected to the drain of the MOS transistor MP10, which is the output terminal of the comparator CMP2.

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