A power module power loss measurement circuit

Abstract

The utility model discloses a kind of power module power loss measurement circuit, it is related to power loss measurement field, including with the same measurement power module model of to-be-measured power module, drive module and load, the positive terminal of measurement power module is connected with the output terminal of to-be-measured power module, the negative terminal of measurement power module is connected with the load, to-be-measured power module is connected with the drive module;The drive module is used to drive to-be-measured power module normal work, the upper tube and lower tube in measurement power module are accessed drive signal, the drive signal is used to make the upper tube and lower tube in measurement power module keep conducting, to obtain the static power loss of to-be-measured power module by measurement power module, and based on the static power loss of to-be-measured power module, the dynamic power loss of to-be-measured power module is obtained.The circuit can accurately decoupling measurement to the static power loss and dynamic power loss of power module.

Description

Technical Field

[0001] This utility model relates to the field of power loss measurement, and in particular to a power module power loss measurement circuit. Background Technology

[0002] The global energy crisis and increasingly serious environmental problems have driven the development of new energy technologies. In recent years, power electronic devices have played an increasingly important role in new energy applications. Among power electronic devices, the power module is one of the key components of the power converter, and its performance evaluation is crucial to ensuring the reliability and efficiency of the electronic system. This includes measuring the power loss of the power module. Power loss can be divided into two types: static loss and dynamic loss. Static loss is usually related to the power consumption of the device when there is no signal change, while dynamic loss is related to the transient power consumption of the device when the signal changes.

[0003] Existing techniques often rely on curve fitting to estimate static and dynamic losses, but the values ​​calculated by this method may differ significantly from the device's performance under actual operating conditions. Therefore, accurately measuring the dynamic and static losses of power modules is a problem that urgently needs to be solved. Utility Model Content

[0004] In response to the aforementioned problems and technical requirements, the applicant has proposed a power module power loss measurement circuit.

[0005] The technical solution of this utility model is as follows:

[0006] A power module power loss measurement circuit includes a measurement power module of the same model as the power module under test, a drive module, and a load, wherein...

[0007] The positive terminal of the power measurement module is connected to the output terminal of the power module under test, the negative terminal of the power measurement module is connected to the load, and the power module under test is connected to the drive module.

[0008] Both the power under test module and the power measurement module include an upper tube and a lower tube connected in series.

[0009] The driving module is used to drive the power module under test to work normally. The upper and lower transistors in the power measurement module are connected to the driving signal. The driving signal is used to keep the upper and lower transistors in the power measurement module conducting, so as to obtain the static power loss of the power module under test through the power measurement module, and obtain the dynamic power loss of the power module under test based on the static power loss of the power module under test.

[0010] A further technical solution is to determine the static power loss P of the power module under test. S1 and the dynamic power loss P of the power module under testD1 satisfy:

[0011]

[0012] Among them, P T1 The total power loss of the power module under test, P T2 To measure the total power loss of the power module, P S2 To measure the static power loss of the power module, T j1 For the junction temperature and T of the power module under test c1 For the case temperature and R of the power module under test th1(j-c) For the junction-to-case thermal resistance of the power module under test, T j2 To measure the junction temperature and T of the power module c2 To measure the case temperature and R of the power module th2(j-c) To measure the junction-to-case thermal resistance of the power module.

[0013] A further technical solution is that the driving module includes an upper transistor driving circuit and a lower transistor driving circuit. The upper transistor driving circuit includes resistors R1, R2, R3, R4, and R5, capacitors C1, C2, C3, C4, C5, and C6, transistors Q1 and Q2, a TVS diode T1, and an optocoupler IC1.

[0014] The first pin of the optocoupler IC1 is connected to one end of the resistor R1, and the third pin of the optocoupler IC1 is connected to one end of the resistor R2. One end of the resistor R1 is connected to the PWM_P signal, and one end of the resistor R2 is connected to the PWM_N signal.

[0015] The sixth pin of the optocoupler IC1 is connected to one end of capacitor C1 and the collector of transistor Q1. The collector of transistor Q1 is connected to the power supply voltage VCC_1. The fourth pin of the optocoupler IC1 is connected to one end of capacitor C2 and the collector of transistor Q2. The collector of transistor Q2 is grounded to the potential VEE_1. The other end of capacitor C1 is connected to the other end of capacitor C2.

[0016] Capacitors C3 and C5 are connected in parallel with capacitor C1, and capacitors C4 and C6 are connected in parallel with capacitor C2. The fifth pin of the optocoupler IC1 is connected to the base of transistor Q1 and the base of transistor Q2 through resistor R3. The emitter of transistor Q1 is connected to the gate of the upper transistor in the power module under test through resistor R4, and the emitter of transistor Q2 is connected to the emitter of the upper transistor in the power module under test through resistor R5.

[0017] A further technical solution is that the lower transistor driving circuit includes resistors R6, R7, R8, R9, and R10; capacitors C7, C8, C9, C10, C11, and C12; transistors Q3 and Q4; a TVS diode T2; and an optocoupler IC2.

[0018] The first pin of the optocoupler IC2 is connected to one end of the resistor R6, and the third pin of the optocoupler IC2 is connected to one end of the resistor R7. One end of the resistor R7 is connected to the PWM_P signal, and one end of the resistor R6 is connected to the PWM_N signal.

[0019] The sixth pin of the optocoupler IC2 is connected to one end of the capacitor C7 and the collector of the transistor Q3. The collector of the transistor Q3 is connected to the power supply voltage VCC_2. The fourth pin of the optocoupler IC2 is connected to one end of the capacitor C8 and the collector of the transistor Q4. The collector of the transistor Q4 is grounded to the potential VEE_2. The other end of the capacitor C7 is connected to the other end of the capacitor C8.

[0020] Capacitors C9 and C11 are connected in parallel with capacitor C7, and capacitors C10 and C12 are connected in parallel with capacitor C8. The fifth pin of the optocoupler IC2 is connected to the base of transistor Q3 and the base of transistor Q4 through resistor R8. The emitter of transistor Q3 is connected to the gate of the lower transistor in the power module under test through resistor R9, and the emitter of transistor Q4 is connected to the emitter of the lower transistor in the power module under test through resistor R10.

[0021] A further technical solution is that the TVS diode T1 is connected between the gate and emitter of the upper diode in the power module under test, and the TVS diode T2 is connected between the gate and emitter of the lower diode in the power module under test.

[0022] A further technical solution is that transistors Q3 and Q1 are NPN transistors, and transistors Q2 and Q4 are PNP transistors.

[0023] A further technical solution is that when the PWM_P signal is high and the PWM_N signal is low, the upper transistor in the power module under test is turned on and the lower transistor is turned off.

[0024] When the PWM_P signal is low and the PWM_N signal is high, the lower transistor in the power module under test is turned on and the upper transistor is turned off.

[0025] When both the PWM_P and PWM_N signals are at a high or low level, the upper and lower transistors in the power module under test are turned off.

[0026] A further technical solution includes a current sensor and an overcurrent protection module. The current sensor is used to sample and measure the negative terminal current of the power module and generate a sampling voltage. The overcurrent protection module is used to generate an OCD signal based on the sampling voltage. The OCD signal is used to control the output state of the PWM_P signal and the PWM_N signal to achieve overcurrent protection.

[0027] A further technical solution is that the overcurrent protection module includes resistors R11, R12, R13, R14, R15, R16, R17, R18, and R19; capacitors C13, C14, C15, and C16; comparator IC1A; and comparator IC1B.

[0028] One end of resistor R11 is connected to the sampling voltage, and the other end of resistor R11 is connected to analog ground through capacitor C13. The other end of resistor R11 is also connected to the inverting input of comparator IC1A. The inverting input of comparator IC1A is also connected to one end of resistor R17. The other end of resistor R17 is connected to the non-inverting input of comparator IC1B. The non-inverting input of comparator IC1B is connected to the output of comparator IC1B through resistor R18.

[0029] The non-inverting input of comparator IC1A is connected to one end of resistor R15. The other end of resistor R15 is connected to one end of resistor R12, one end of resistor R13, and one end of capacitor C14. The other end of resistor R12 is connected to the power supply voltage VA. The other end of resistor R13 is connected to the inverting input of comparator IC1B, one end of resistor R14, and one end of capacitor C15. The other ends of capacitor C14, capacitor C15, and resistor R14 are connected to analog ground.

[0030] The non-inverting input terminal of comparator IC1A is connected to the output terminal of comparator IC1A through resistor R16. The output terminal of comparator IC1A is connected to the output terminal of comparator IC1B to form an OCD signal output terminal. The OCD signal output terminal is connected to one end of resistor R19 and one end of capacitor C16. The other end of resistor R19 is connected to the power supply voltage VD, and the other end of capacitor C16 is connected to digital ground.

[0031] A further technical solution is that the load includes a reactor.

[0032] The beneficial technical effects of this utility model are:

[0033] The power module power loss measurement circuit provided by this utility model is equipped with a test power module connected in series with the output terminal of the power module under test. It can independently calculate the static power loss and total power loss of the power module under test. The dynamic power loss of the power module under test is obtained by subtracting the calculated total power loss from the static power loss. This allows for decoupled measurement of the static and dynamic power losses of the power module under test. The current flowing through the power module under test during measurement is the current value under actual operating conditions, making the calculation results closer to reality and the loss measurement results more accurate. Simultaneously, an overcurrent protection module is included to protect the circuit from overcurrent, improving the reliability and stability of the measurement circuit. Attached Figure Description

[0034] Figure 1 This is a circuit diagram showing the connection between the power under test module, the power measurement module, and the load in one embodiment of this utility model.

[0035] Figure 2 This is a circuit schematic diagram of one embodiment of the upper transistor drive circuit provided by this utility model.

[0036] Figure 3 This is a circuit schematic diagram of one embodiment of the lower transistor drive circuit provided by this utility model.

[0037] Figure 4 This is a circuit diagram of one embodiment of the overcurrent protection module provided by this utility model.

[0038] Figure 5 This is a schematic diagram of the overcurrent protection provided by this utility model.

[0039] Figure 6 This is a circuit diagram showing the connection between the power module under test, the power measurement module, and the load in another embodiment of this utility model. Detailed Implementation

[0040] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0041] This utility model provides a power module power loss measurement circuit, including a power measurement module of the same model as the power module under test, a drive module, and a load.

[0042] The positive terminal of the power measurement module is connected to the output terminal of the power module under test, the negative terminal of the power measurement module is connected to the load, and the power module under test is connected to the drive module.

[0043] Both the power under test module and the power measurement module include an upper tube and a lower tube connected in series.

[0044] The driving module is used to drive the power module under test to work normally. The upper and lower transistors in the power measurement module are connected to the driving signal. The driving signal is used to keep the upper and lower transistors in the power measurement module conducting, so as to obtain the static power loss of the power module under test through the power measurement module, and obtain the dynamic power loss of the power module under test based on the static power loss of the power module under test.

[0045] For details, please refer to Figure 1 In one embodiment of this utility model, the power under test module specifically refers to a half-bridge module M1, and the power measurement module specifically refers to a half-bridge module M2. The power under test module includes an upper IGBT (M11) and a lower IGBT (M12) connected in series in the forward direction, and the power measurement module includes an upper IGBT (M21) and a lower IGBT (M22) connected in series in the forward direction. In both the power under test module and the power measurement module, the upper and lower IGBTs are connected in parallel with an FRD in reverse direction, and the collector of the upper IGBT forms the positive terminal. The emitter of the upper IGBT is connected to the collector of the lower IGBT to form the output terminal, and the emitter of the lower IGBT forms the negative terminal. The negative terminal of the power measurement module is connected to a reactor L1. The reactor L1 is used to smooth the current in the circuit and acts as an inductive load. The positive and negative terminals of the power module under test are connected to the DC positive bus and the DC negative bus through terminals P1 and P2, respectively. The upper and lower transistors in the power module under test are usually controlled by the drive module to conduct alternately. When the devices in the power module under test switch between the on and off states, dynamic power loss will be generated, and the on-state voltage drop of the devices will generate static power loss. The sum of dynamic power loss and static power loss constitutes the total power loss of the power module under test.

[0046] In this application, a power module of the same model is used as a measurement power module connected in series with the output terminal of the power module under test (DUT). The upper and lower transistors within the measurement power module are kept conducting, ensuring that the measurement power module generates only the same static power loss as the DUT. The static power loss of the DUT can be obtained by calculating the static power loss of the measurement power module. Simultaneously, the total power loss of the DUT can be calculated using existing techniques. Subtracting the static power loss from the total power loss yields the dynamic power loss of the DUT, thus achieving decoupled measurement of the static and dynamic power losses of the DUT. The driving signal is used to control the voltage between the gate and emitter of the upper and lower transistors within the measurement power module, ensuring that the upper and lower transistors remain conducting.

[0047] Furthermore, the total power loss, static power loss, and dynamic power loss of the power module under test can be expressed as P, respectively. T1 P S1 P D1The total power loss and static power loss of the power module can be expressed as P, respectively. T2 P S2 As can be seen from the above explanation, P T1 =P S1 +P D1 P S1 =P T2 =P S2 In practice, a temperature sensor is used to measure the junction temperature T of the power module. j2 and the case temperature T of the power module c2 This allows you to calculate the total power loss P of the measured power module. T2 :

[0048]

[0049] Similarly, the junction temperature T of the power module under test is measured using a temperature sensor. j1 and the case temperature T of the power module under test c1 The total power loss P of the power module under test can then be calculated. T1 :

[0050]

[0051] Among them, R th1(j-c) For the junction-to-case thermal resistance, R of the power module under test th2(j-c) To measure the junction-to-case thermal resistance of the power module, since the power module under test and the power module being measured are of the same model, R... th1(j-c) =R th2(j-c) And R th1(j-c) R th2(j-c) This can be determined from the power module's datasheet. The calculated total power loss P of the measured power module is... T2 This refers to the static power loss P of the power module under test. S1 Then the dynamic power loss P of the power module under test D1 =P T1 -P T2 .

[0052] Further, please refer to Figure 2-3 The driving module includes an upper transistor driving circuit and a lower transistor driving circuit. The upper transistor driving circuit includes resistors R1, R2, R3, R4, and R5, capacitors C1, C2, C3, C4, C5, and C6, transistors Q1 and Q2, a TVS diode T1, and an optocoupler IC1.

[0053] The first pin (anode pin of the LED) of the optocoupler IC1 is connected to one end of resistor R1. The third pin (cathode pin of the LED) of the optocoupler IC1 is connected to one end of resistor R2. One end of resistor R1 is connected to a PWM_P signal, and one end of resistor R2 is connected to a PWM_N signal. The sixth pin (positive power supply pin) of the optocoupler IC1 is connected to one end of capacitor C1 and the collector of transistor Q1. The collector of transistor Q1 is connected to the power supply voltage VCC_1. The fourth pin (negative power supply pin) of the optocoupler IC1 is connected to one end of capacitor C2. The collector of transistor Q2 is connected to ground at potential VEE_1. The other end of capacitor C1 is connected to the other end of capacitor C2. Capacitors C3 and C5 are connected in parallel with capacitor C1, and capacitors C4 and C6 are connected in parallel with capacitor C2. The fifth pin (output pin) of optocoupler IC1 is connected to the base of transistors Q1 and Q2 through resistor R3. The emitter of transistor Q1 is connected to the gate of the upper transistor in the power module under test through resistor R4, and the emitter of transistor Q2 is connected to the emitter of the upper transistor in the power module under test through resistor R5.

[0054] Specifically, the working principle of the upper / lower IGBT drive circuit is consistent with existing technology. Resistors R1 and R2 are current-limiting resistors. The PWM_P and PWM_N signals are isolated by optocoupler IC1 and then enter transistors Q1 and Q2, driving the corresponding IGBTs through resistors R4 and R5. Transistor Q1 is an NPN transistor, and transistor Q2 is a PNP transistor. Transistor Q1 and resistor R4 determine the turn-on time, while transistor Q2 and resistor R5 determine the turn-off time. The TVS diode T1 is connected between the gate and emitter of the upper IGBT in the power module under test to protect against transient voltage surges in the drive signal. Capacitors C1, C3, and C5 provide positive charge buffering for the drive, while capacitors C2, C4, and C6 provide negative charge buffering for the drive.

[0055] The lower transistor drive circuit includes resistors R6, R7, R8, R9, and R10; capacitors C7, C8, C9, C10, C11, and C12; transistors Q3 and Q4; a TVS diode T2; and an optocoupler IC2.

[0056] The first pin (anode pin of the LED) of the optocoupler IC2 is connected to one end of resistor R6. The third pin (cathode pin of the LED) of the optocoupler IC2 is connected to one end of resistor R7. One end of resistor R7 is connected to the PWM_P signal, and one end of resistor R6 is connected to the PWM_N signal. The sixth pin (positive power supply pin) of the optocoupler IC2 is connected to one end of capacitor C7 and the collector of transistor Q3. The collector of transistor Q3 is connected to the power supply voltage VCC_2. The fourth pin (negative power supply pin) of the optocoupler IC2 is connected to one end of capacitor C8 and... The collector of transistor Q4 is connected to ground at potential VEE_2. The other end of capacitor C7 is connected to the other end of capacitor C8. Capacitors C9 and C11 are connected in parallel with capacitor C7. Capacitors C10 and C12 are connected in parallel with capacitor C8. The fifth pin (output pin) of optocoupler IC2 is connected to the base of transistors Q3 and Q4 through resistor R8. The emitter of transistor Q3 is connected to the gate of the lower transistor in the power module under test through resistor R9. The emitter of transistor Q4 is connected to the emitter of the lower transistor in the power module under test through resistor R10.

[0057] Similar to the upper IGBT drive circuit, in the lower IGBT drive circuit, resistors R6 and R7 are current-limiting resistors. The PWM_P and PWM_N signals are isolated by optocoupler IC2 and then enter transistors Q3 and Q4, respectively, driving the corresponding IGBTs through resistors R9 and R10. Transistor Q3 is an NPN transistor, and transistor Q4 is a PNP transistor. Transistor Q3 and resistor R9 determine the turn-on time, while transistor Q4 and resistor R10 determine the turn-off time. The TVS diode T2 is connected between the gate and emitter of the lower IGBT in the power module under test to protect against transient voltage surges in the drive signal. Capacitors C7, C9, and C11 provide positive charge buffering for the drive, while capacitors C8, C10, and C12 provide negative charge buffering for the drive.

[0058] The PWM_P and PWM_N signals are provided by the MCU. Generally, the turn-on timing of the upper and lower transistors of the power module under test is complementary to prevent the upper and lower transistors from shoot-through. The truth table of the PWM_P and PWM_N signals and the control of the upper and lower transistors is shown in Table 1.

[0059] Table 1. Truth Table of PWM_P Signal, PWM_N Signal and Control of Upper and Lower Transistors

[0060] 0 0 upper and lower pipe shut-off 1 0 Upper pipe is open, lower pipe is closed. 0 1 Lower pipe is open, upper pipe is closed. 1 1 upper and lower pipe shut-off

[0061] As shown in Table 1, when the PWM_P signal is high (i.e., logic "1") and the PWM_N signal is low (i.e., logic "0"), the upper transistor in the power module under test is turned on and the lower transistor is turned off; when the PWM_P signal is low and the PWM_N signal is high, the lower transistor in the power module under test is turned on and the upper transistor is turned off; when both the PWM_P signal and the PWM_N signal are high or low, both the upper and lower transistors in the power module under test are turned off, thus avoiding the risk of shoot-through between the upper and lower transistors from a hardware perspective.

[0062] Furthermore, the power module power loss measurement circuit also includes a current sensor and an overcurrent protection module. The current sensor is used to sample and measure the negative terminal current of the power module and generate a sampling voltage. The overcurrent protection module is used to generate an OCD signal based on the sampling voltage. The OCD signal is used to control the output state of the PWM_P signal and the PWM_N signal to achieve overcurrent protection.

[0063] Specifically, the current sensor (i.e. Figure 1 The sensor1 shown collects the negative terminal current of the power module and generates a corresponding sampling voltage (V_IN) which is output to the overcurrent protection module. The specific form of the current sensor can be consistent with the existing technology.

[0064] Please refer to Figure 4 The overcurrent protection module includes resistors R11, R12, R13, R14, R15, R16, R17, R18, and R19; capacitors C13, C14, C15, and C16; comparator IC1A; and comparator IC1B.

[0065] One end of resistor R11 is connected to the sampling voltage, and the other end of resistor R11 is connected to analog ground through capacitor C13. The other end of resistor R11 is also connected to the inverting input of comparator IC1A. The inverting input of comparator IC1A is also connected to one end of resistor R17. The other end of resistor R17 is connected to the non-inverting input of comparator IC1B. The non-inverting input of comparator IC1B is connected to the output of comparator IC1B through resistor R18.

[0066] The non-inverting input terminal of comparator IC1A is connected to one end of resistor R15. The other end of resistor R15 is connected to one end of resistor R12, one end of resistor R13, and one end of capacitor C14 to form a first connection point. The other end of resistor R12 is connected to the power supply voltage VA. The other end of resistor R13 is connected to the inverting input terminal of comparator IC1B, one end of resistor R14, and one end of capacitor C15 to form a second connection point. The other ends of capacitor C14, capacitor C15, and resistor R14 are connected to analog ground.

[0067] The non-inverting input terminal of comparator IC1A is connected to the output terminal of comparator IC1A through resistor R16. The output terminal of comparator IC1A is connected to the output terminal of comparator IC1B to form an OCD signal output terminal. The OCD signal output terminal is connected to one end of resistor R19 and one end of capacitor C16. The other end of resistor R19 is connected to the power supply voltage VD, and the other end of capacitor C16 is connected to digital ground.

[0068] Specifically, in the overcurrent protection module, resistors R2, R3, and R4 are connected in series to form a voltage divider network, which divides the power supply voltage VA to obtain the reference voltage VREF_P (i.e., the voltage at the first connection point) and the reference voltage VREF_N (i.e., the voltage at the second connection point). Comparator IC1A, resistors R15 and R16 form a hysteresis comparator, and comparator IC1B, resistors R17 and R18 form a hysteresis comparator. In this embodiment, the power supply voltage VA is 5V, and the power supply voltage VD is 3.3V. The OCD signal is output to the MCU. The MCU controls the output state of the PWM_P and PWM_N signals according to the OCD signal. When an overcurrent occurs, the OCD signal becomes a low level of 0V, the MCU stops the output of the PWM_P and PWM_N signals, and the power module under test stops working, thereby realizing overcurrent protection.

[0069] The sampled voltage is filtered by resistor R11 and capacitor C13 before entering the overcurrent protection module. In this embodiment, the current sensor outputs a sampled voltage of 1V to 4V based on the collected current. When the current is 0A, the sampled voltage is 2.5V. In this embodiment, the PWM signal operates at a certain switching frequency and the duty cycle changes according to a sinusoidal law. Therefore, the current flowing through the power measurement module changes according to a sinusoidal law. The positive half-cycle of the sinusoidal current flows through the upper and lower transistors of the power measurement module, and the negative half-cycle of the sinusoidal current flows through the FRD connected in antiparallel to the upper and lower transistors. Figure 5 A schematic diagram of overcurrent protection is shown, with the sampled voltage curves (represented as 0.1U, 0.2U, and 0.3U) corresponding to the first, second, and third currents with sequentially increasing values ​​plotted on [the diagram]. Figure 5 middle, Figure 5The horizontal axis represents time (s), and the vertical axis represents voltage (mV). For example... Figure 5 As shown, when the sampled current is within the normal current range (such as the first and second currents), the corresponding sampling voltage remains within the reference voltages VREF_N and VREF_P, the OCD signal is always 3.3V, and the MCU outputs PWM_P and PWM_N signals normally. When the sampled current exceeds the normal current threshold range (such as the third current), during the positive half-cycle of the sine wave, the corresponding sampling voltage V_IN > VREF_P. At this time, comparator IC1A flips, the OCD signal is pulled low from 3.3V to 0V, and the MCU stops outputting PWM_P and PWM_N signals. During the negative half-cycle of the sine wave, the corresponding sampling voltage V_IN < VREF_N. At this time, comparator IC1B flips, the OCD signal is pulled low from 3.3V to 0V, and the MCU stops outputting PWM_P and PWM_N signals. The normal current threshold range can be determined according to the actual situation. The reference voltages VREF_N and VREF_P are determined based on the normal current threshold range and the conversion relationship between the current sampled by the current sensor and the sampling voltage.

[0070] like Figure 6 As shown, in another embodiment of this utility model, the power loss measurement circuit can be applied to a three-phase bridge composed of power modules M1', M3, and M5. The three-phase bridge operates under inverter conditions, converting DC voltage into AC voltage. The positive terminals of power modules M1', M3, and M5 are all connected to the DC positive bus, and the negative terminals are all connected to the DC negative bus. All power modules are half-bridge modules. Power modules M1', M3, and M5 are all power modules under test. For each power module under test, a power measurement module, a drive module, a current sensor, and an overcurrent protection module are adapted to measure the dynamic and static power losses of power modules M1', M3, and M5 respectively, and to provide overcurrent protection.

[0071] Specifically, the output terminal of power module M1' is connected to the positive terminal of power measurement module M2', the output terminal of power module M3 is connected to the positive terminal of power measurement module M4, and the output terminal of power module M5 is connected to the positive terminal of power measurement module M6. In this embodiment, the negative terminals of power measurement modules M2', M4, and M6 are connected to the first phase input terminal, the second phase input terminal, and the third phase input terminal of three-phase reactor L1', respectively. The first to third phase output terminals of three-phase reactor L1' are connected, and three-phase reactor L1' is used to smooth the current in the circuit and act as an inductive load. The upper and lower transistors in power measurement modules M2', M4, and M6 are loaded with drive signals to keep both the upper and lower transistors conducting.

[0072] Power modules M1', M3, and M5 are driven by corresponding connected drive modules. The PWM signals (PWM_P and PWM_N signals) operate at a certain switching frequency, and their duty cycles vary sinusoidally. The current flowing through the power module under test is a sinusoidal wave with switching components. The module will generate static power loss (caused by the on-state voltage drop) and dynamic power loss (caused by device turn-on and turn-off). The total power loss of power modules M2', M4, and M6 is calculated to obtain the static power loss of power modules M1', M3, and M5. The total power loss of power modules M1', M3, and M5 is also calculated, and the total power loss of power modules M2', M4, and M6 is subtracted accordingly to obtain the dynamic power loss of power modules M1', M3, and M5. This achieves decoupled measurement of the static and dynamic power losses of power modules M1', M3, and M5. The calculation method for the total power loss of the measured power module and the power module under test is consistent with the above. The specific structure and driving method of the drive module are also consistent with the above embodiment, and will not be repeated here.

[0073] Power modules M2', M4, and M6 each correspond to an overcurrent protection module. Current sensors sensor2, sensor3, and sensor4 are used to collect and measure the negative terminal current of power modules M2', M4, and M6, respectively, and generate corresponding sampling voltages that are transmitted to the corresponding overcurrent protection modules. When the current flowing through power modules M2', M4, and M6 exceeds the normal current threshold range, the corresponding overcurrent protection module generates a low-level OCD signal. Upon detecting the low-level OCD signal, the MCU stops outputting PWM signals to the corresponding drive module. The specific structure and working principle of the overcurrent protection module are consistent with the above embodiment and will not be repeated here.

[0074] In the description of this specification, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. References to terms such as "an embodiment / mode" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode is included in at least one embodiment / mode of this application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode.

[0075] The above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A power module power loss measurement circuit, characterized in that, This includes a measurement power module, a drive module, and a load, all of which are of the same model as the power module under test. The positive terminal of the power measurement module is connected to the output terminal of the power module under test, the negative terminal of the power measurement module is connected to the load, and the power module under test is connected to the drive module. Both the power under test module and the power measurement module include an upper tube and a lower tube connected in series. The driving module is used to drive the power module under test to work normally. The upper and lower transistors in the power measurement module are connected to the driving signal. The driving signal is used to keep the upper and lower transistors in the power measurement module conducting, so as to obtain the static power loss of the power module under test through the power measurement module, and obtain the dynamic power loss of the power module under test based on the static power loss of the power module under test.

2. The power module power loss measurement circuit according to claim 1, characterized in that, Static power loss P of the power module under test S1 and the dynamic power loss P of the power module under test D1 satisfy: Among them, P T1 The total power loss of the power module under test, P T2 To measure the total power loss of the power module, P S2 To measure the static power loss of the power module, T j1 For the junction temperature and T of the power module under test c1 For the case temperature and R of the power module under test th1(j-c) For the junction-to-case thermal resistance of the power module under test, T j2 To measure the junction temperature and T of the power module c2 To measure the case temperature and R of the power module th2(j-c) To measure the junction-to-case thermal resistance of the power module.

3. The power module power loss measurement circuit according to claim 1, characterized in that, The driving module includes an upper transistor driving circuit and a lower transistor driving circuit. The upper transistor driving circuit includes resistors R1, R2, R3, R4, and R5; capacitors C1, C2, C3, C4, C5, and C6; transistors Q1 and Q2; a TVS diode T1; and an optocoupler IC1. The first pin of the optocoupler IC1 is connected to one end of the resistor R1, and the third pin of the optocoupler IC1 is connected to one end of the resistor R2. One end of the resistor R1 is connected to the PWM_P signal, and one end of the resistor R2 is connected to the PWM_N signal. The sixth pin of the optocoupler IC1 is connected to one end of capacitor C1 and the collector of transistor Q1. The collector of transistor Q1 is connected to the power supply voltage VCC_1. The fourth pin of the optocoupler IC1 is connected to one end of capacitor C2 and the collector of transistor Q2. The collector of transistor Q2 is grounded to the potential VEE_1. The other end of capacitor C1 is connected to the other end of capacitor C2. Capacitors C3 and C5 are connected in parallel with capacitor C1, and capacitors C4 and C6 are connected in parallel with capacitor C2. The fifth pin of the optocoupler IC1 is connected to the base of transistor Q1 and the base of transistor Q2 through resistor R3. The emitter of transistor Q1 is connected to the gate of the upper transistor in the power module under test through resistor R4, and the emitter of transistor Q2 is connected to the emitter of the upper transistor in the power module under test through resistor R5.

4. The power module power loss measurement circuit according to claim 3, characterized in that, The lower transistor drive circuit includes resistors R6, R7, R8, R9, and R10; capacitors C7, C8, C9, C10, C11, and C12; transistors Q3 and Q4; a TVS diode T2; and an optocoupler IC2. The first pin of the optocoupler IC2 is connected to one end of the resistor R6, and the third pin of the optocoupler IC2 is connected to one end of the resistor R7. One end of the resistor R7 is connected to the PWM_P signal, and one end of the resistor R6 is connected to the PWM_N signal. The sixth pin of the optocoupler IC2 is connected to one end of the capacitor C7 and the collector of the transistor Q3. The collector of the transistor Q3 is connected to the power supply voltage VCC_2. The fourth pin of the optocoupler IC2 is connected to one end of the capacitor C8 and the collector of the transistor Q4. The collector of the transistor Q4 is grounded to the potential VEE_2. The other end of the capacitor C7 is connected to the other end of the capacitor C8. Capacitors C9 and C11 are connected in parallel with capacitor C7, and capacitors C10 and C12 are connected in parallel with capacitor C8. The fifth pin of the optocoupler IC2 is connected to the base of transistor Q3 and the base of transistor Q4 through resistor R8. The emitter of transistor Q3 is connected to the gate of the lower transistor in the power module under test through resistor R9, and the emitter of transistor Q4 is connected to the emitter of the lower transistor in the power module under test through resistor R10.

5. The power module power loss measurement circuit according to claim 4, characterized in that, The TVS diode T1 is connected between the gate and emitter of the upper transistor in the power module under test, and the TVS diode T2 is connected between the gate and emitter of the lower transistor in the power module under test.

6. The power module power loss measurement circuit according to claim 4, characterized in that, Transistors Q3 and Q1 are NPN type transistors, and transistors Q2 and Q4 are PNP type transistors.

7. The power module power loss measurement circuit according to claim 4, characterized in that, When the PWM_P signal is high and the PWM_N signal is low, the upper transistor in the power module under test is turned on and the lower transistor is turned off. When the PWM_P signal is low and the PWM_N signal is high, the lower transistor in the power module under test is turned on and the upper transistor is turned off. When both the PWM_P and PWM_N signals are at a high or low level, the upper and lower transistors in the power module under test are turned off.

8. The power module power loss measurement circuit according to claim 4, characterized in that, It also includes a current sensor and an overcurrent protection module. The current sensor is used to sample and measure the negative terminal current of the power module and generate a sampling voltage. The overcurrent protection module is used to generate an OCD signal based on the sampling voltage. The OCD signal is used to control the output state of the PWM_P signal and the PWM_N signal to achieve overcurrent protection.

9. The power module power loss measurement circuit according to claim 8, characterized in that, The overcurrent protection module includes resistors R11, R12, R13, R14, R15, R16, R17, R18, and R19; capacitors C13, C14, C15, and C16; comparator IC1A; and comparator IC1B. One end of resistor R11 is connected to the sampling voltage, and the other end of resistor R11 is connected to analog ground through capacitor C13. The other end of resistor R11 is also connected to the inverting input of comparator IC1A. The inverting input of comparator IC1A is also connected to one end of resistor R17. The other end of resistor R17 is connected to the non-inverting input of comparator IC1B. The non-inverting input of comparator IC1B is connected to the output of comparator IC1B through resistor R18. The non-inverting input of comparator IC1A is connected to one end of resistor R15. The other end of resistor R15 is connected to one end of resistor R12, one end of resistor R13, and one end of capacitor C14. The other end of resistor R12 is connected to the power supply voltage VA. The other end of resistor R13 is connected to the inverting input of comparator IC1B, one end of resistor R14, and one end of capacitor C15. The other ends of capacitor C14, capacitor C15, and resistor R14 are connected to analog ground. The non-inverting input terminal of comparator IC1A is connected to the output terminal of comparator IC1A through resistor R16. The output terminal of comparator IC1A is connected to the output terminal of comparator IC1B to form an OCD signal output terminal. The OCD signal output terminal is connected to one end of resistor R19 and one end of capacitor C16. The other end of resistor R19 is connected to the power supply voltage VD, and the other end of capacitor C16 is connected to digital ground.

10. The power module power loss measurement circuit according to claim 1, characterized in that, The load includes a reactor.

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