A subway vehicle buf board test platform
Patent Information
- Application Number
- CN202521736201.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-14
- Publication Date
- 2026-09-25
- Estimated Expiration
- 2035-08-14
AI Technical Summary
目前通过搭建测试环境，对每路信号处理和状态监控电路进行逐一测试，测试过程存在需要设备较多、步骤繁琐、作业过程中接线存在安全隐患等问题，主要有：
[0014]相对于现有技术，本实用新型具有以下有益效果：通过模拟类信号发生单元发出用于进行模拟类信号测试的第二模拟测试信号供待测试BUF板进行测试，配备模拟类信号采样单元对模拟类信号采样单元反馈的第一采样信号，通过速度类信号发生单元发出用于进行速度类信号测试的第二速度测试信号供待测试BUF板进行测试，配备速度类信号采样单元对速度类信号采样单元反馈的第二采样信号，将该些单元集成为一个测试平台，避免在进行BUF板测试时，重新搭建测试环境，提高工作效率。
Smart Images
Figure CN224803143U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of BUF board testing technology for subway vehicles, and specifically to a BUF board testing platform for subway vehicles. Background Technology
[0002] The function of the traction unit buffer card (BUF board) is to provide interfaces for digital signals and the train control system (TMS). It processes externally input analog signals such as grid voltage, load, braking torque, and speed sensor signals, and outputs the processed signals to the traction system control processor card (SCP board). It also communicates with the TMS via RS485 communication. A BUF board malfunction can lead to issues such as "grid voltage issues on the display after pantograph lowering," "speed sensor failure," and "rear speed failure," thus affecting the traction system's functionality and causing train changes on the main line. Therefore, maintenance and functional testing of the BUF board are necessary.
[0003] The BUF board involves analog and digital signal processing circuits. The analog signals include 3 braking torque signals, 8 mains voltage signals, and 6 load signals. The digital signals include 8 speed signals, 8 power status monitoring signals, and 2 sets of RS-485 communication circuits. Currently, a test environment is being built to test each signal processing and status monitoring circuit individually. However, the testing process presents several challenges, including the need for numerous devices, cumbersome procedures, and potential safety hazards related to wiring during operation. These include: 1. Each BUF board needs to test 17 analog signal processing circuits and 18 speed signal processing and status monitoring circuits. Each signal processing and status monitoring circuit needs to be tested in a separate test environment, which results in low testing efficiency. 2. The testing process requires a lot of equipment. Utility Model Content
[0004] The purpose of this invention is to overcome the shortcomings and deficiencies in the existing technology and provide a subway vehicle BUF board testing platform that can improve testing efficiency.
[0005] This utility model is achieved through the following technical solution: A test platform for BUF boards in subway vehicles, comprising: The host computer is used to send test signals; The control unit is connected to the host computer and generates a first analog test signal and a first speed test signal based on the test signal. An analog signal generation unit, connected to the control unit and the BUF board under test, is used to process the first analog test signal to obtain a second analog test signal for testing the BUF board under test. An analog signal sampling unit is connected to the BUF board under test and the control unit, and is used to output the first sampling signal of the BUF board under test to the control unit. A speed signal generation unit is connected to the control unit and the BUF board under test. It is used to process the first speed test signal to obtain a second speed test signal for the BUF board under test to perform testing. A speed-type signal sampling unit is connected to the BUF board under test and the control unit, and is used to output the second sampling signal of the BUF board under test to the control unit.
[0006] As a further improvement of this utility model, the analog signal generating unit includes: An analog signal generation circuit, connected to the control unit, is used to receive the first analog test signal and process the first analog test signal to obtain the second analog test signal. Several analog signal control circuits are connected to the control unit to receive a first control signal and process the first control signal to obtain a second control signal. The first gating circuit is connected to the analog signal generation circuit, the analog signal control circuit, and the BUF board under test, and outputs the second analog test signal to the BUF board under test according to the second control signal.
[0007] As a further improvement of this utility model, the analog signal sampling unit includes: Several analog signal sampling circuits are connected to the BUF board under test to acquire the first feedback signal generated by the BUF board under test during the test, and process the first feedback signal to obtain the first sampled signal. Several analog signal sampling control circuits are connected to the control unit to receive a third control signal and process the third control signal to obtain a fourth control signal. The second gating circuit is connected to the analog signal sampling circuit, the control unit, and the analog signal sampling control circuit, and is used to send the first sampling signal to the control unit according to the fourth control signal.
[0008] As a further improvement of this utility model, the speed-type signal generating unit includes: A speed signal generation circuit, connected to the control unit, is used to receive the first speed test signal and process the first speed test signal to obtain the second speed test signal. Several speed-type signal control circuits are connected to the control unit to receive a fifth control signal and process the fifth control signal to obtain a sixth control signal. The third gating circuit is connected to the speed signal generation circuit, the speed signal control circuit, and the BUF board under test, and outputs the second speed test signal to the BUF board under test according to the sixth control signal.
[0009] As a further improvement of this utility model, the velocity signal sampling unit includes: Several speed-type signal sampling and control circuits are connected to the control unit to receive a seventh control signal and process the seventh control signal to obtain an eighth control signal. The fourth gating circuit, connected to the speed-type signal sampling control circuit, the control unit, and the speed-type signal sampling control circuit, is used to send the second sampling signal to the control unit according to the eighth control signal.
[0010] As a further improvement of this utility model, this utility model includes: an interconnection control unit, wherein the control unit includes: an STM32 microcontroller; The RS485 communication circuit of the BUF board under test is connected to the UART serial port of the STM32 microcontroller through the interconnection control unit.
[0011] As a further improvement of this utility model, the power feedback pin of the BUF board to be tested is connected to the I / O port of the STM32 microcontroller.
[0012] As a further improvement of this utility model, this utility model also includes: a WI-FI unit, through which the control unit is connected to the maintenance server.
[0013] As a further improvement of this utility model, this utility model also includes: a power supply unit, which is connected to the control unit, the analog signal generation and sampling unit, the speed signal generation and sampling unit, and the BUF board under test, for providing working power.
[0014] Compared with the prior art, this utility model has the following advantages: A second analog test signal for analog signal testing is emitted by an analog signal generation unit for testing the BUF board under test; an analog signal sampling unit is equipped to receive the first sampling signal fed back by the analog signal sampling unit; a second speed test signal for speed signal testing is emitted by a speed signal generation unit for testing the BUF board under test; and a speed signal sampling unit is equipped to receive the second sampling signal fed back by the speed signal sampling unit. Integrating these units into a test platform avoids the need to rebuild the test environment when testing the BUF board, thus improving work efficiency. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of the overall structure of the subway vehicle BUF board testing platform described in this utility model; Figure 2 This is a schematic diagram of the analog signal generation circuit described in this utility model; Figure 3 This is a schematic diagram of the analog signal control circuit described in this utility model; Figure 4 This is a schematic diagram of the structure of the first gating circuit of this utility model; Figure 5 This is a schematic diagram of the analog signal sampling circuit described in this utility model; Figure 6 This is a schematic diagram of the analog signal sampling control circuit described in this utility model; Figure 7 This is a pin connection diagram of the multiplexing chip U7 described in this utility model; Figure 8 This is a schematic diagram of the structure of the first signal amplification branch of this utility model; Figure 9 This is a schematic diagram of the speed signal generation circuit described in this utility model; Figure 10 This is a schematic diagram of the speed-type signal control circuit described in this utility model; Figure 11 This is a schematic diagram of the third gating circuit described in this utility model; Figure 12 This is a schematic diagram of the speed signal sampling control circuit described in this utility model; Figure 13 This is a schematic diagram of the fourth gating circuit described in this utility model; Figure 14 This is a schematic diagram of the interconnection control unit described in this utility model.
[0017] Explanation of reference numerals in the attached figures: 1. Host computer; 2. Control unit; 3. Analog signal generation unit; 31. Analog signal generation circuit; 32. Analog signal control circuit; 33. First gating circuit; 4. Analog signal sampling unit; 41. Analog signal sampling circuit; 42. Analog signal sampling control circuit; 43. Second gating circuit; 431. First signal amplification branch; 5. Speed signal generation unit; 51. Speed signal generation circuit; 52. Speed signal control circuit; 53. Third gating circuit; 6. Speed signal sampling unit; 61. Speed signal sampling control circuit; 62. Fourth gating circuit; 621. Second signal amplification branch; 7. WI-FI unit; 8. Power supply unit; 9. Interconnection control unit; 100. BUF board under test; 101. Maintenance server. Detailed Implementation
[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0019] This utility model provides a test platform for the BUF board of a subway vehicle, such as Figure 1 As shown, the system includes: a host computer 1, a control unit 2, an analog signal generation unit 3, an analog signal sampling unit 4, a speed signal generation unit 5, and a speed signal sampling unit 6. The host computer 1 is used to send test signals. The control unit 2 is connected to the host computer 1 and generates a first analog test signal and a first speed test signal based on the test signals. The analog signal generation unit 3 is connected to the control unit 2 and the BUF board 100 under test, and processes the first analog test signal to obtain a second analog test signal for testing the BUF board 100. The analog signal sampling unit 4 is connected to the BUF board 100 under test and the control unit 2, and outputs the first sampling signal of the BUF board 100 to the control unit 2. The speed signal generation unit 5 is connected to the control unit 2 and the BUF board 100 under test, and processes the first speed test signal to obtain a second speed test signal for testing the BUF board 100. The speed signal sampling unit 6 is connected to the BUF board 100 under test and the control unit 2, and outputs the second sampling signal of the BUF board 100 to the control unit 2.
[0020] The main functions of control unit 2 are implemented using an STM32 microcontroller.
[0021] Furthermore, the analog signal generation unit 3 includes: an analog signal generation circuit 31, several analog signal control circuits 32, and a first gating circuit 33. The analog signal generation circuit 31 is connected to the control unit 2 and is used to receive a first analog test signal and process the first analog test signal to obtain a second analog test signal. The analog signal control circuits 32 are connected to the control unit 2 and are used to receive a first control signal. The first gating circuit 33 is connected to the analog signal generation circuit 31, the analog signal control circuits 32, and the BUF board 100 under test, and outputs the second analog test signal to the BUF board 100 under test according to the first control signal.
[0022] like Figures 2-4 As shown, the analog signal generation circuit 31 includes operational amplifiers U48.1, U48.2, and U49.1. The first analog test signal CPU-AO output by the control unit 2 is conditioned by multiple operational amplifiers to generate the second analog test signal AO. Several analog signal control circuits 32 have the same structure, including logic gate chip U52.1 and optocoupler U13. The first control signals AOS-A, AOS-B, AOS-C, AOS-D, and AOS-ENABLE input to the control unit 2 are processed by each analog signal control circuit 32. After processing, the second control signals AOS-A1, AOS-B1, AOS-C1, AOS-D1, and AOS-ENABLE are obtained. The first gating circuit 33 includes a multiplexing chip U14. The second control signals AOS-A1, AOS-B1, AOS-C1, AOS-D1, and AOS-ENABLE control the multiplexing chip U14, so that the second analog test signal AO required for the test is applied in turn to the corresponding analog input channels AO1~AO16 of the BUF board 100 under test.
[0023] The analog signal sampling unit 4 includes: several analog signal sampling circuits 41, several analog signal sampling control circuits 42, and a second gating circuit 43. The analog signal sampling circuits 41 are connected to the BUF board 100 under test and are used to acquire the first feedback signal generated by the BUF board 100 under test during the test and process the first feedback signal to obtain the first sampling signal. The analog signal sampling control circuits 42 are connected to the control unit 2 and are used to receive the third control signal and process the third control signal to obtain the fourth control signal. The second gating circuit 43 is connected to the analog signal sampling circuits 41, the control unit 2, and the analog signal sampling control circuits and is used to send the first sampling signal to the control unit 2 according to the fourth control signal.
[0024] like Figures 5-8 As shown, the analog signal sampling circuit 41 includes an operational amplifier U42.1, model OPA217AIDR. Multiple analog signal sampling circuits 41 have the same structure. The analog signal sampling control circuit 42 includes a general-purpose logic gate chip U51.1 and an optocoupler U8. The second gating circuit 43 includes a first signal amplification branch 431 and a multiplexing chip U7. The first signal amplification branch 431 includes an operational amplifier U47.1, model OPA2170AIDR. The analog signal sampling circuit 41 processes the first feedback signals AI1~AI13 generated by the BUF board 100 under test during the test to obtain the first sampling signals AI1_1~AI1_13. The third control signals AIS-A, AIS-B, AIS-C, AIS-D, and AIS-ENABLE output by the control unit 2 are processed by several analog signal sampling circuits 41 to output the fourth control signals AIS-A1, AIS-B1, AIS-C1, AIS-D1, and AIS-ENABLE1 to control the operational amplifier U47.1. This causes the first sampling signals AI1_1~AI1_13, after being processed by the BUF board and conditioned by the analog signal conditioning circuit, to alternately act on the input channel AI of the multiplexing chip U7. After being amplified by the first signal amplification branch 431, they are input to the STM32 microcontroller AD sampling channel CPU-AI.
[0025] The speed signal generation unit 5 includes: a speed signal generation circuit 51, a speed signal control circuit 52, and a third gating circuit 53. The speed signal generation circuit 51 is connected to the control unit 2 and is used to receive a first speed test signal and process the first speed test signal to obtain a second speed test signal. The speed signal control circuit 52 is connected to the control unit 2 and is used to receive a fifth control signal and process the fifth control signal to obtain a sixth control signal. The third gating circuit 53 is connected to the speed signal generation circuit 51, the speed signal control circuit 52, and the BUF board 100 under test, and outputs the second speed test signal to the BUF board 100 under test according to the sixth control signal.
[0026] like Figures 9-11As shown, the speed signal generation circuit 51 includes a general-purpose logic gate chip U54.6 and an optocoupler U27. The speed signal control circuit 52 includes a general-purpose logic gate chip U54.6 and an optocoupler U27. The third gating circuit 53 includes a multiplexing chip U22. The first speed test signal CPU-VSG issued by the control unit 2 is processed by several speed signal generation circuits 51 to obtain the second speed test signal VSG1. The structures of the several speed signal control circuits 52 are the same. The control unit 2 issues a fifth control signal VSGS-A and a fifth control signal VSG. S-B, the fifth control signal VSGS-C, the fifth control signal VSGS-D, and the fifth control signal VSGS-ENABLE are processed by the speed signal control circuit 52 to obtain the sixth control signal VSGS-A, the sixth control signal VSGS-B, the sixth control signal VSGS-C, the sixth control signal VSGS-D, and the sixth control signal VSGS-ENABLE. These control the multiplexing chip U22, so that the second speed test signal VSG1 required for the test is applied in turn to the speed signal input channels VSO1~VSO8 of the BUF board 100 under test.
[0027] The speed-type signal sampling unit 6 includes: several speed-type signal sampling control circuits 61 and a second gating circuit 43. The speed-type signal sampling control circuits 61 are connected to the control unit 2 and are used to receive a seventh control signal and process the seventh control signal to obtain an eighth control signal. The fourth gating circuit 62 is connected to the speed-type signal sampling control circuits 61, the control unit 2, and the speed-type signal sampling control circuits 61 and is used to send a second sampling signal to the control unit 2 according to the eighth control signal.
[0028] like Figures 12-14As shown, the speed-type signal sampling control circuit 61 includes: a general-purpose logic gate chip U55.1 and an optocoupler U28. Several speed-type signal sampling control circuits 61 have the same structure. The fourth gating circuit 62 includes: a second signal amplification branch and a multiplexing chip U29. The second signal amplification branch includes: a general-purpose logic gate chip U55.6 and an optocoupler U34. The control unit 2 outputs the seventh control signal VSAS-A, the seventh control signal VSAS-B, the seventh control signal VSAS-C, the seventh control signal VSAS-D, and the seventh control signal VSAS-ENABLE, which are then processed by several speed-type signal sampling control circuits. After processing by control circuit 61, the eighth control signals VSAS-A1, VSAS-B1, VSAS-C1, VSAS-D1, and VSAS-ENABLE1 are obtained, which control the multiplexing chip U29. This causes the second sampling signals VSA1~VSA16, which are processed by the BUF board under test 100, to act alternately on the speed signal input channel VSA of the multiplexing chip U29. After processing by the general logic gate chip U55.6 and the optocoupler isolation U34, they are input to the speed signal sampling channel CPU-VSA of the STM32 microcontroller.
[0029] Furthermore, the RS485 communication circuit of the BUF board 100 under test is connected to the UART serial port of the STM32 microcontroller through the interconnection control unit 92, as shown in the figure. The interconnection control unit 92 includes a general logic gate chip U53.1, an optocoupler U20, and a relay U19. Its function is to control the on / off state of the coil of the relay U19 after the two sets of RS 485 communication circuit transmit and receive pins on the BUF board 100 under test are interconnected. The RS 485 communication selection control signal RS485-S issued by the control unit 2 is processed by the general logic gate chip U53.1 and isolated by the optocoupler U20, so as to control the actual selected RS 485 communication circuit test path. When relay U19 is not energized, the RS 485 communication signal output by control unit 2 is output via RS 485-DI to the first RS 485 communication circuit interface P2-C13 of the BUF board under test 100. After passing through the two interconnected A and B lines, it is output through the second RS 485 communication circuit interface P2-A7 of the BUF board under test 100 and input to the STM32 control unit 2 via RS 485-RO. When relay U19 is energized, the RS 485 communication signal output by the BUF board under test 100 is output via RS 485-DI to the second RS 485 communication circuit interface P2-C6 of the BUF board. After passing through the two interconnected A and B lines, it is output through the first RS 485 communication circuit interface P2-A14 of the BUF board under test 100 and input to the control unit 2 via RS 485-RO.
[0030] The power feedback pin of the BUF board 100 under test is connected to the I / O port of the STM32 microcontroller. This connection method enables power monitoring and timely alarm and prompt processing when power or power monitoring circuit abnormalities are detected, thus directly and effectively monitoring the power status.
[0031] In addition, this utility model also includes a WI-FI unit 7, through which the control unit 2 is connected to the maintenance server 101. The WI-FI unit 7 adopts a UART-WIFI transparent transmission module with ultra-low power consumption, and its main chip is ESP8266, supporting the wireless 802.11b / g / n standard.
[0032] This utility model also includes: a power supply unit 8, connected to the control unit 2, the analog signal generation and sampling unit, the speed signal generation and sampling unit, and the BUF board 100 under test, for providing operating power. The power supply unit 8 includes: a power module and a linear regulator chip. The power supply unit 8 further converts the DC110V power output from the AC220V to DC110V switching power supply into ±15V, ±12V, 5V, and 3.3V power supplies through the power module and the linear regulator, respectively powering the BUF board under test and the lower-level machine in the test platform.
[0033] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.
Claims
1. A test platform for BUF boards in subway vehicles, characterized in that, include: The host computer is used to send test signals; The control unit is connected to the host computer and generates a first analog test signal and a first speed test signal based on the test signal. An analog signal generation unit, connected to the control unit and the BUF board under test, is used to process the first analog test signal to obtain a second analog test signal for testing the BUF board under test. An analog signal sampling unit is connected to the BUF board under test and the control unit, and is used to output the first sampling signal of the BUF board under test to the control unit. A speed signal generation unit is connected to the control unit and the BUF board under test. It is used to process the first speed test signal to obtain a second speed test signal for the BUF board under test to perform testing. A speed-type signal sampling unit is connected to the BUF board under test and the control unit, and is used to output the second sampling signal of the BUF board under test to the control unit.
2. The subway vehicle BUF board testing platform according to claim 1, characterized in that, The analog signal generation unit includes: An analog signal generation circuit, connected to the control unit, is used to receive the first analog test signal and process the first analog test signal to obtain the second analog test signal. Several analog signal control circuits are connected to the control unit to receive a first control signal and process the first control signal to obtain a second control signal. The first gating circuit is connected to the analog signal generation circuit, the analog signal control circuit, and the BUF board under test, and outputs the second analog test signal to the BUF board under test according to the second control signal.
3. The subway vehicle BUF board testing platform according to claim 1, characterized in that, The analog signal sampling unit includes: Several analog signal sampling circuits are connected to the BUF board under test to acquire the first feedback signal generated by the BUF board under test during the test, and process the first feedback signal to obtain the first sampled signal. Several analog signal sampling control circuits are connected to the control unit to receive a third control signal and process the third control signal to obtain a fourth control signal. The second gating circuit is connected to the analog signal sampling circuit, the control unit, and the analog signal sampling control circuit, and is used to send the first sampling signal to the control unit according to the fourth control signal.
4. The subway vehicle BUF board testing platform according to claim 1, characterized in that, The velocity-type signal generation unit includes: A speed signal generation circuit, connected to the control unit, is used to receive the first speed test signal and process the first speed test signal to obtain the second speed test signal. Several speed-type signal control circuits are connected to the control unit to receive a fifth control signal and process the fifth control signal to obtain a sixth control signal. The third gating circuit is connected to the speed signal generation circuit, the speed signal control circuit, and the BUF board under test, and outputs the second speed test signal to the BUF board under test according to the sixth control signal.
5. The subway vehicle BUF board testing platform according to claim 1, characterized in that, The velocity-type signal sampling unit includes: Several speed-type signal sampling and control circuits are connected to the control unit to receive a seventh control signal and process the seventh control signal to obtain an eighth control signal. The fourth gating circuit, connected to the speed-type signal sampling control circuit, the control unit, and the speed-type signal sampling control circuit, is used to send the second sampling signal to the control unit according to the eighth control signal.
6. The subway vehicle BUF board testing platform according to claim 1, characterized in that, Also includes: An interconnection control unit, the control unit including: an STM32 microcontroller; The RS485 communication circuit of the BUF board under test is connected to the UART serial port of the STM32 microcontroller through the interconnection control unit.
7. The subway vehicle BUF board testing platform according to claim 6, characterized in that, The power feedback pin of the BUF board under test is connected to the I / O port of the STM32 microcontroller.
8. The subway vehicle BUF board testing platform according to claim 1, characterized in that, Also includes: The control unit is connected to the maintenance server via a Wi-Fi unit.
9. The subway vehicle BUF board testing platform according to claim 1, characterized in that, Also includes: The power supply unit is connected to the control unit, the analog signal generation and sampling unit, the speed signal generation and sampling unit, and the BUF board under test, and is used to provide working power.