Semiconductor burn-in test circuit and apparatus

Abstract

The utility model discloses a kind of semiconductor aging test circuit and equipment, belong to integrated circuit technical field, this semiconductor aging test circuit, including three temperature test area, SIP encapsulation inside the chip to be measured has interconnected FPGA, Flash and DDR device, the inside of the chip to be measured is also integrated with function aging module, for function aging test, configuration interface circuit and the chip to be measured are connected, for providing JTAG interface to the chip to be measured;The chip to be measured is connected with the JTAG interface of aging system by the JTAG interface provided by configuration interface circuit, and aging system applies electrical stress, thermal stress and dynamic signal to the chip to be measured, and the clock pin of the clock pin of the PL end and the PS end of the chip to be measured is provided with two-way excitation clock signal by excitation board. By providing and SIP encapsulation the aging test circuit matched with the chip to be measured is aged and tested, the chip to be measured is set in three temperature test area, reduce the test influence of extreme temperature to relevant circuit.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, and in particular to a semiconductor aging test circuit and equipment. Background Technology

[0002] System-in-Package (SiP) is a packaging concept that integrates all or most of the electronic functions of a system or subsystem onto a single, integrated substrate. Chips are bonded to this substrate in 2D or 3D configurations. SiP can assemble multiple chips, and can also integrate a dedicated processor, DRAM, flash memory, and passive components such as resistors, capacitors, connectors, and antennas, all mounted on the same substrate. This means that a complete functional unit can be built into a multi-chip package; therefore, only a small number of external components are needed to make it function.

[0003] While the failure mechanisms and patterns of individual functional modules in SiP-packaged finished chips are similar to those of other single-chip integrated circuits, they also require semiconductor / integrated circuit aging testing to screen and eliminate early-failure integrated circuits, ensuring the reliability of the final marketed integrated circuits. The aging test system for SiP-packaged finished chips not only needs to cover its internal test modules but also meet stringent testing requirements. Therefore, the aging test circuits used for single-chip integrated circuits are not entirely suitable for SiP-packaged finished chips. Thus, there is an urgent need to provide a aging test circuit suitable for SiP-packaged finished chips for aging testing.

[0004] It should be noted that the information disclosed in the background section of this utility model is intended only to enhance the understanding of the general background of this utility model, and should not be regarded as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0005] The purpose of this invention is to provide a semiconductor aging test circuit and equipment to solve the problem that the aging test circuits used in single-chip integrated circuits are not entirely applicable to finished chips in SIP packages.

[0006] To solve the above-mentioned technical problems, this utility model provides a semiconductor aging test circuit, comprising:

[0007] The three-temperature test area is used to set up the chip under test. The chip under test has interconnected FPGA, Flash and DDR devices in a SIP package. The chip under test also integrates a functional aging module for functional aging test.

[0008] A configuration interface circuit is provided, which is connected to the chip under test and is used to provide a JTAG interface to the chip under test.

[0009] In the aging system, the chip under test is connected to the JTAG interface of the aging system through the JTAG interface provided by the configuration interface circuit, and the aging system applies electrical stress, thermal stress and dynamic signals to the chip under test.

[0010] An excitation board provides two excitation clock signals to the clock pins of the PL and PS terminals of the chip under test. The excitation board also provides excitation control signal pins connected to the corresponding pins of the PL terminal of the chip under test to realize the testing function of the aging system.

[0011] The configuration interface circuit, aging system, and excitation board are all located outside the three-temperature test area.

[0012] Preferably, only the chip under test is set in the three-temperature test area, and the three-temperature test area is a circular area with the chip under test as the center and a preset distance as the radius.

[0013] Preferably, it further includes an I / O test circuit, which is connected to the chip under test and is used to verify the functionality of the input / output ports of the chip under test.

[0014] Preferably, it further includes a power management circuit and a power interface circuit, wherein the power interface circuit is connected to the power management circuit, and the power management circuit is interconnected with the chip under test.

[0015] Preferably, it also includes a debugging interface connected to the chip under test.

[0016] Preferably, the chip under test is further connected to a clock management circuit, which provides a clock signal to the test interface of the chip under test.

[0017] Preferably, the aging system is also connected to a push-button switch for turning the aging system on, off, and reset, and the control terminal of the push-button switch is connected to the pin of the excitation board that provides the excitation control signal.

[0018] Preferably, the PL terminal and PS terminal of the chip under test are respectively connected to a first indicator light to indicate the working status.

[0019] Preferably, the DONE interface of the chip under test is also connected to a second indicator light to indicate the working status.

[0020] A semiconductor aging test device includes the semiconductor aging test circuit described above.

[0021] In the semiconductor aging test circuit provided by this utility model, aging tests are performed by providing an aging test circuit that matches the SIP packaged chip under test. The chip under test is placed in a three-temperature test area to reduce the impact of extreme temperatures on the test of related circuits. An FPGA, Flash, and functional aging module are packaged inside the chip under test. The FPGA can control the internal Flash to realize the solidification, storage, and configuration of the aging bit stream, thereby realizing the automatic loading of multiple cycles of aging bit stream. Furthermore, the test circuit of this utility model can also perform ATPG aging and functional aging, which can fully include the full resource test of the entire SIP circuit, ensuring high-quality completion of reliability screening, accelerating the exposure of potential defects, and ensuring the stability of the chip throughout its life cycle.

[0022] The semiconductor aging test equipment and the semiconductor aging test circuit provided by this utility model belong to the same utility model concept. Therefore, the semiconductor aging test equipment provided by this utility model has at least all the advantages of the semiconductor aging test circuit provided by this utility model, which will not be repeated here. Attached Figure Description

[0023] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the scope of the present invention. Wherein:

[0024] Figure 1 This is a structural diagram of a aging test circuit according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of a JTAG signal circuit according to an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the ATPG aging signal interface according to an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the Done light and reset button circuit according to an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales.

[0029] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first," "second," and "third" can explicitly or implicitly include one or at least two of those features. The term "proximal" usually refers to the end closer to the operator, and the term "distal" usually refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," usually refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "joined" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this utility model, the placement of one element on another element usually only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated in the content. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0030] Research has found that aging test systems for finished SIP-packaged chips not only need to cover their internal test modules, but also need to meet stringent testing requirements. The aging test circuits used for single-chip integrated circuits are not entirely suitable for finished SIP-packaged chips.

[0031] Based on this, the core idea of ​​this utility model is to provide an aging test circuit that matches the SIP packaged chip under test for aging testing. The chip under test is placed in a three-temperature test area to reduce the impact of extreme temperatures on the testing of related circuits. An FPGA, Flash, and functional aging module are packaged inside the chip under test. The FPGA can control the internal Flash to realize the solidification, storage, and configuration of the aging bit stream, thereby realizing the automatic loading of multiple cyclic aging bit streams. Furthermore, the test circuit of this utility model can also perform ATPG aging and functional aging, which can fully include the full resource testing of the entire SIP circuit, ensuring high-quality completion of reliability screening, accelerating the exposure of potential defects, and ensuring the stability of the chip throughout its life cycle.

[0032] For details, please refer to Figures 1-4 This is a schematic diagram of an embodiment of the present utility model. Figure 1 As shown, a semiconductor aging test circuit includes:

[0033] The three-temperature test area is used to set up the chip under test. The chip under test has interconnected FPGA, Flash and DDR devices in a SIP package. The chip under test also integrates a functional aging module for functional aging test.

[0034] A configuration interface circuit is provided, which is connected to the chip under test and is used to provide a JTAG interface to the chip under test.

[0035] In the aging system, the chip under test is connected to the JTAG interface of the aging system through the JTAG interface provided by the configuration interface circuit, and the aging system applies electrical stress, thermal stress and dynamic signals to the chip under test.

[0036] An excitation board provides two excitation clock signals to the clock pins of the PL and PS terminals of the chip under test. The excitation board also provides excitation control signal pins connected to the corresponding pins of the PL terminal of the chip under test to realize the testing function of the aging system.

[0037] The configuration interface circuit, aging system, and excitation board are all located outside the three-temperature test area.

[0038] In one embodiment, the aging test circuit provided in this application consists of an excitation board and an aging system. The excitation board is responsible for providing external excitation signals to the integrated circuit aging test circuit, such as partial power supply and clock signals required during testing. The aging system is mainly used to control the aging mode of the finished integrated circuit under test. Through an interface connection with the finished integrated circuit, it can read information such as the junction temperature of the device and realize the open / short circuit testing function of the finished integrated circuit. During the aging process of the finished integrated circuit, the aging system monitors the junction temperature of the device in real time (the actual operating temperature of the PN junction inside the semiconductor device, which is usually higher than the package temperature) to realize the aging protection function.

[0039] The chip under test (DUT) is a high-performance SiP control chip that integrates a high-performance FPGA (containing a multi-core processor with an ARM architecture), Flash memory, DDR memory, and other electrical components in a SiP package. This chip also needs to be able to operate normally at temperatures ranging from -55°C to 125°C. Existing aging test circuits often cannot meet the temperature and functional testing requirements of DUTs with SiP-packaged FPGAs. The aging test circuits provided in this invention are specifically designed according to the structure of the DUT, meeting the unique test modules and stringent testing requirements of the applicable chip, thus possessing considerable uniqueness. It is understood that the test circuits of this application can be applied to SiP-packaged chips or semiconductor devices containing FPGAs (containing a multi-core processor with an ARM architecture), Flash memory, DDR memory, and other electrical components.

[0040] In one embodiment, only the chip under test is placed within the three-temperature testing area. The three-temperature testing area is a circular area with the chip under test as the center and a preset distance as the radius. The preset distance is approximately 10cm. Figure 1 As shown, the chip under test is set within the three-temperature test area, while other circuits are set outside the three-temperature test area. Circuits affected by temperature are moved to the greatest extent possible, such as moving the circuits most affected by temperature to the position furthest away from the chip under test, reducing the impact of extreme temperatures on the test of related circuits, and ensuring that the relocation of related circuits has the least impact on the entire test circuit system.

[0041] For example, the excitation board is a key component in an automated test equipment (ATE), mainly used to generate and transmit test signals to the chip under test (DUT). The excitation board is specifically designed according to the size of the DUT, the test temperature requirements, and the test module. In this application, the excitation board mainly outputs excitation clock signals and excitation control signals. The excitation board outputs two excitation clock signals and connects them to the dedicated clock pins of the device's PL (programmable logic) and PS (processing system) terminals, respectively. The PL clock frequency is 100MHz, and the PS clock frequency is 50.0MHz, both of which are LVCMOS33 level signals. The excitation control signals are connected to 29 specific pins of the PL terminal of the DUT to realize the test function of the aging system and output the test results to the designated pins for real-time monitoring.

[0042] More preferably, the aging system is also connected to a push-button switch for turning the aging system on and off and resetting it. The control terminal of the push-button switch is connected to the pin of the excitation board that provides the excitation control signal. The excitation control signal also controls the reset function of the aging system via the push-button switch. For example, multiple push-button switches can be combined to form a system as shown in the example. Figure 4 The reset button circuit shown.

[0043] Aging systems are reliability testing devices that accelerate the exposure of potential defects by applying electrical stress, thermal stress, and dynamic signals. They are primarily used to screen chips that fail early and ensure product stability during long-term use. In the actual aging test process, the chip under test is placed on the test station and the test fixture is installed and fixed. Then, power is supplied by an external power system and the excitation board is turned on to begin the aging test of the device under test.

[0044] like Figure 2 As shown, this application also provides a JTAG signal circuit. Configuration interface circuits typically refer to hardware circuits used to load configuration data into programmable devices (such as FPGAs). JTAG is an international standard test and debug interface, commonly used for chip configuration, debugging, and boundary scans. Both the chip under test (DUT) and the aging system have JTAG interfaces. The device's JTAG interface connects to the aging system's JTAG function interface, enabling the reading of junction and other information from the device, and supporting BSCAN (Boundary Scan, a technology for chip testing and debugging, part of the JTAG standard, widely used for testing, debugging, and fault analysis of digital circuits) detection functions to achieve open and short circuit testing. During the aging process, the aging system monitors the device's junction temperature in real time, implementing aging protection functions.

[0045] Specifically, it also includes an I / O test circuit, which is connected to the chip under test and is used to verify the functionality of the input / output ports of the chip under test.

[0046] The I / O test circuit is a key module in integrated circuit testing, primarily used to verify the electrical characteristics, signal integrity, and functional reliability of the chip's input / output ports. In a practical I / O circuit structure, external pull-up and pull-down resistors (10kΩ) are used to implement the I / O bias circuit function. The pull-up resistor is connected to the VCCO or VCCAUX power supply, and the pull-down resistor is connected to GND. A custom-designed test program for transmitting and receiving data using encoded (e.g., 0x55 / AA) enables communication testing between the chip's I / O ports. In actual testing, the test rate can reach 400Mbps, which meets current testing requirements.

[0047] Specifically, it also includes a power management circuit and a power interface circuit, wherein the power interface circuit is connected to the power management circuit, and the power management circuit is interconnected with the chip under test.

[0048] Understandably, separating the power management circuit and the power interface circuit allows for independent control of power distribution and protection. The power management circuit is the core module in an electronic system responsible for power conversion, distribution, and protection, and its design directly affects the stability, efficiency, and reliability of the equipment. Even better, the power management circuit is a PMIC (Power Management Microcontroller), capable of dynamic load adjustment. The PMIC matches the DUT (Distributed Under Test) power consumption in real time, preventing overvoltage / undervoltage (e.g., ±5% tolerance). Magnetic coupling isolators (such as the ADIADuM series) can also be used between functional modules to avoid power supply noise crosstalk.

[0049] The power interface circuit is a core module in electronic equipment that enables power transmission, signal control, and protection functions. Its design directly affects the stability, safety, and energy efficiency of the equipment. The power interface circuit is the physical channel for energy transmission, ensuring the safe and efficient input / output of electrical energy; the power management circuit is the central hub for energy regulation, responsible for global optimization and dynamic response.

[0050] like Figure 1 As shown, the entire test circuit also includes a debugging interface connected to the chip under test (DUT). The debugging interface TESTPAD provides a debugging interface to the DUT for debugging hardware and software aspects. On the hardware side, it provides a series of interfaces focusing on signal integrity detection and automation equipment (such as PCB test points and gigabit Ethernet analyzers), while on the software side, it focuses on test process management and collaboration tools (such as checklist-driven agile testing).

[0051] The chip under test (DUT) is also connected to a clock management circuit, which provides clock signals, including a system clock signal Sysclk and a reset clock signal Reclk, to the DUT's test interface. The clock management circuit is a core module of digital and mixed-signal systems, responsible for generating, distributing, and optimizing clock signals to ensure timing synchronization and power efficiency. In this application, the aforementioned debugging interface includes a test interface. Through the test interface provided by the debugging interface, the clock management circuit provides multiple frequency clock signals to the test interface. When multiple test interfaces simultaneously perform tests at different frequencies, it manages and distributes the clock signals, avoiding interference between signals of different frequencies and thus preventing any impact on test accuracy.

[0052] More preferably, the PL and PS terminals of the chip under test are each connected to a first indicator light to indicate the operating status. The DONE interface of the chip under test is also connected to a second indicator light to indicate the operating status.

[0053] like Figure 4The second indicator light and reset button circuit of the DONE interface shown output two excitation clock signals through the excitation board and are respectively connected to the dedicated clock pin of the chip under test (DUT) to provide a reference clock. The test status of the DUT is observed through 5 LEDs and 1 test point. The PL (programmable logic) and PS (processing system) terminals each have 2 working indicator lights. The DONE status is indicated by one light, while the ATPG test status is monitored through one test point. The dual monitoring of the PS and PL terminals and their different test functions—the PS terminal mainly monitors the operating capabilities of the ARM architecture processor and the internal firmware test status, while the PL terminal mainly tests the chip's programmable logic resources and interconnect modules. Further specialized testing and monitoring can also be performed using an oscilloscope, multimeter, or logic analyzer.

[0054] During aging tests on the chip under test, a collaborative aging monitoring mechanism is implemented between the PL and PS terminals. The PL terminal performs high-speed signal injection (such as the ATPG scan chain), while the PS terminal analyzes parameter drift (such as leakage current IDDQ) via the AXI bus. Five LEDs are used to indicate the PL, PS, and DONE statuses, enabling status visualization. The test points can also be adapted to logic analyzers (such as Teledyne LeCroy) for rapid fault location.

[0055] This product's aging test includes two types: ATPG (Automatic Test Mode Generation) aging and functional aging. ATPG-based aging test is a core technology for integrated circuit reliability verification. Its core objective is to accelerate the detection of circuit aging effects and screen for potential defects by generating specific test vectors. Functional aging test is a core step in integrated circuit reliability verification. Its core objective is to accelerate the exposure of potential defects and screen for early failures by simulating the long-term operating state of the chip under extreme conditions, ensuring the stability and reliability of the chip throughout its entire life cycle. Figure 3 The ATPG aging signal interface is shown.

[0056] In one implementation, the functional aging module is integrated into the SIP firmware function; that is, the functional aging module is integrated into the Flash and DDR devices packaged together with the main control FPGA chip. By combining ATPG (Automatic Test Mode Generation) and functional aging (simulating extreme operating conditions), the functional aging module can achieve multi-stress superposition.

[0057] In one implementation, the ATPG test process is adjusted based on SC aging (stress conditions) to dynamically adjust the ATPG vector density, accelerate the exposure of defects such as gate oxide breakdown, and achieve test vector optimization. The SIP firmware integrates the protocol stack (such as SIP signaling) and hardware driver to support communication protocol verification during the aging process and achieve firmware collaboration.

[0058] The device under test (DUT) in this application is a finished chip packaged in SIP with an FPGA chip as the main controller and Flash and DDR as peripheral devices. Unlike other FPGA chips or chips with FPGA as the main controller, the DUT in this application is packaged with Flash, and the FPGA and Flash are internally connected during packaging. Therefore, the aging test can realize the storage and configuration loading functions of the aging bit stream (i.e., the instruction stream used to configure the DUT to the aging state) through the built-in FLASH of the device's PS terminal. Before the device is subjected to aging test, the aging bit stream is first solidified into the internal FLASH of the device through the output of the FPGA main controller chip inside the DUT via STL (system-level test). During aging, the bit stream in the FLASH is automatically loaded in a loop according to the process. After aging is completed, the firmware Flash is erased and cleared again by STL test.

[0059] The test circuit outputs two clock signals via an excitation board, each connected to a dedicated clock pin on the device to provide a reference clock. The device's test status is observed using five LEDs and one test point. The PL (programmable logic) and PS (processing system) terminals each have two indicator lights, with one LED indicating the device's DONE status. The ATPG test status is monitored through one test point. The dual monitoring of the PS and PL terminals, with different testing functions, involves the PS terminal primarily monitoring the ARM architecture processor's operational capabilities and internal firmware testing, while the PL terminal primarily tests the chip's programmable logic resources and interconnect modules. Further specialized testing and monitoring can also be performed using an oscilloscope, multimeter, or logic analyzer.

[0060] The integrated circuit aging test system of this application has an aging status indicator and a reset button circuit, which can monitor the aging status in real time during the aging test, and can also reset and exit the aging test state in time when an abnormality is detected.

[0061] The aging test circuit is matched with the finished integrated circuit under test. It has certain uniqueness and is composed of multiple sub-module circuits. The modules are highly independent and mature, which reduces manufacturing costs and makes it easier to achieve collaboration between modules. In addition, there are various test interfaces or management circuits connected to the chip modules, so troubleshooting can be done easily when circuit problems occur.

[0062] The aging test circuit design of this application features a three-temperature test area, enabling testing at three temperatures: -55℃, 25℃, and 125℃. Within this three-temperature test area, PCB layout optimization (e.g., keeping heat-sensitive modules away from the temperature zones) maximizes the relocation of circuits highly affected by temperature, minimizing the impact of extreme temperatures on related circuits and avoiding the influence of temperature stress on the stability of other circuits (such as power management and clock circuits). Furthermore, the relocation of related circuits ensures minimal impact on the test system. Structures such as copper foil heat dissipation layers or thermal vias can be placed at the boundaries of the three-temperature test area to accelerate heat conduction, ensure temperature control accuracy (±1℃), and reduce the impact on other circuit areas.

[0063] Unlike other FPGA chips or chips controlled by FPGA, the chip under test in this application can realize the solidified storage and configuration of aging bit streams through FPGA control of the internal Flash, thereby realizing the automatic cyclic loading of multiple aging bit streams.

[0064] The indicator light and reset button circuit of the integrated circuit aging test circuit of this application can monitor the aging status in real time during the aging test, and can also reset and exit the aging test state in time when an abnormality is detected.

[0065] Based on the same technical concept, this application also provides a semiconductor aging test device, including the semiconductor aging test circuit as described above.

[0066] Based on the same technical concept, this application also provides a semiconductor aging test method, which uses the semiconductor aging test circuit as described above, and further includes performing the following aging test on the chip under test within a temperature range of -55℃ to 125℃:

[0067] An ATPG aging test was performed on the PL terminal of the chip under test.

[0068] The functional aging module within the chip under test is invoked to perform functional aging tests, which are used to test the PS-side circuit, Flash, and DDR devices of the chip under test.

[0069] In the aging test, the chip under test also controls the solidification, storage and configuration of the internal Flash aging bit stream through FPGA control.

[0070] In one embodiment, the firmware storage and configuration of the aging bitstream in the internal Flash of the chip under test controlled by the FPGA includes: before the chip under test is subjected to aging test, the aging bitstream is first fixed into the Flash of the chip under test through the output of the FPGA inside the chip under test via STL test; during aging, the bitstream in the Flash is automatically loaded in a cycle according to the process; after aging is completed, the firmware Flash is erased and cleared again via STL test.

[0071] In one embodiment, the first indicator light on the PL terminal of the chip under test (DUT) is used to monitor the operating capability of the ARM architecture processor and the internal ATPG test status. The first indicator light on the PS terminal of the DUT is used to monitor the test status of the programmable logic resources and interconnect modules of the DUT. Furthermore, the excitation control signal also controls the reset function of the aging system through a push-button switch, which is used to reset and exit the aging test state in case of an abnormality.

[0072] The semiconductor aging test circuit and equipment provided in this application have the following advantages:

[0073] The integrated circuit aging test circuit is composed of multiple mature and independent sub-modules.

[0074] The aging test circuit is deeply matched with the chip under test and has a high degree of irreplaceability.

[0075] It can be tested under three temperature conditions. The temperature range is from -55℃ to 125℃, and it has the ability to complete tests stably and accurately under extreme temperature conditions.

[0076] Test status can be observed via indicator lights and test points. The PL (Programmable Logic) and PS (Processing System) terminals each have their own indicator lights. The PS and PL terminals provide dual monitoring with distinct testing functions: the PS terminal primarily monitors the ARM architecture processor's operational capabilities and internal ATPG test status, while the PL terminal primarily tests the programmable logic resources and interconnect modules of the chip under test. Further specialized testing and monitoring can be performed using an oscilloscope, multimeter, or logic analyzer.

[0077] The aging tests performed on the semiconductor aging test circuit in this application include two types: ATPG aging and functional aging. The functional aging part integrates SIP firmware functions and mainly tests the PS-side circuit and peripheral packaged devices such as Flash and DDR, meeting the special requirements of SIP packaged chip testing. The ATPG aging test tests the interconnect resource modules and programmable resource modules of the circuit under test, that is, the aging test of the PL-side resources. Ensuring that the aging test can completely cover the full resource testing of the entire SIP circuit can guarantee high-quality reliability screening, accelerate the exposure of potential defects, and ensure the stability of the chip throughout its life cycle.

[0078] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present utility model.

Claims

1. A semiconductor aging test circuit, characterized in that, include: The three-temperature test area is used to set up the chip under test. The chip under test has interconnected FPGA, Flash and DDR devices in a SIP package. The chip under test also integrates a functional aging module for functional aging test. A configuration interface circuit is provided, which is connected to the chip under test and is used to provide a JTAG interface to the chip under test. In the aging system, the chip under test is connected to the JTAG interface of the aging system through the JTAG interface provided by the configuration interface circuit, and the aging system applies electrical stress, thermal stress and dynamic signals to the chip under test. An excitation board provides two excitation clock signals to the clock pins of the PL and PS terminals of the chip under test. The excitation board also provides excitation control signal pins connected to the corresponding pins of the PL terminal of the chip under test, so as to realize the testing function of the aging system. The configuration interface circuit, aging system, and excitation board are all located outside the three-temperature test area.

2. The semiconductor aging test circuit according to claim 1, characterized in that, Only the chip under test is set in the three-temperature test area, which is a circular area with the chip under test as the center and a preset distance as the radius.

3. The semiconductor aging test circuit according to claim 1, characterized in that, It also includes an I / O test circuit, which is connected to the chip under test and is used to verify the function of the input and output ports of the chip under test.

4. The semiconductor aging test circuit according to claim 1, characterized in that, It also includes a power management circuit and a power interface circuit, wherein the power interface circuit is connected to the power management circuit, and the power management circuit is interconnected with the chip under test.

5. The semiconductor aging test circuit according to claim 1, characterized in that, It also includes a debugging interface connected to the chip under test.

6. The semiconductor aging test circuit according to claim 5, characterized in that, The chip under test is also connected to a clock management circuit, which provides a clock signal to the test interface of the chip under test.

7. The semiconductor aging test circuit according to claim 1, characterized in that, The aging system is also connected to a push-button switch for turning the aging system on, off, and reset. The control terminal of the push-button switch is connected to the pin of the excitation board that provides the excitation control signal.

8. The semiconductor aging test circuit according to claim 1, characterized in that, The PL and PS terminals of the chip under test are each connected to a first indicator light to indicate the working status.

9. The semiconductor aging test circuit according to claim 1, characterized in that, The DONE interface of the chip under test is also connected to a second indicator light to indicate its working status.

10. A semiconductor aging test apparatus, characterized in that, Includes the semiconductor aging test circuit as described in any one of claims 1-9.

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