A ladder temperature encoding circuit based on parallel anti-jitter of multi-path hysteresis comparators

Abstract

The utility model discloses a kind of ladder temperature encoding circuit based on multiple hysteresis comparator parallel anti-jitter, including NTC temperature acquisition circuit, multiple inverting hysteresis comparison circuit and priority encoding circuit;Multiple inverting hysteresis comparison circuit is connected in parallel between, the inverting input end of comparator is connected with the output end of NTC temperature acquisition circuit, resistance R1 and resistance R2 are connected in series and constitute reference network, the intermediate node of reference network is connected as reference voltage source to the non-inverting input end of comparator, resistance R3 is connected between the output end and non-inverting input end of comparator, the output end of comparator is configured resistance R4 as state holding element;The input end of priority encoder each pin and the output end of multiple inverting hysteresis comparison circuit establish orderly connection, and the output end of priority encoding circuit is used to output the encoding result of different temperature interval.The utility model introduces hysteresis comparator technology, effectively eliminates tiny signal jump by setting upper and lower threshold, and enhances anti-jitter ability.

Description

Technical Field

[0001] This utility model relates to the field of temperature control system technology, specifically to a stepped temperature encoding circuit based on parallel anti-jitter multi-channel hysteresis comparators. Background Technology

[0002] The accuracy of testing equipment plays a crucial role in maintaining the stable operation of the power grid. However, high-temperature environments can significantly accelerate the aging process of testing equipment and may even cause safety hazards. Therefore, optimizing temperature control technology becomes particularly critical.

[0003] Air-cooled temperature control technology has been widely adopted due to its economic efficiency and practicality. Under suitable conditions, such as keeping the CPU temperature below 90°C and the ambient temperature no higher than 40°C, air-cooled temperature control demonstrates significant effectiveness. However, fan vibration not only generates noise interference but can also lead to long-term performance degradation and affect device stability. Fan vibration is closely related to the formulation of temperature control strategies; unreasonable settings often result in unstable fan operation. Therefore, finely adjusting the temperature control strategy and scientifically setting temperature thresholds and response times are of great significance for ensuring stable fan operation, improving user experience, and ensuring device safety.

[0004] Currently, mainstream temperature control systems mainly rely on temperature probes for real-time monitoring, while the CPU dynamically adjusts the fan speed based on preset temperature thresholds. However, when the temperature approaches the threshold, the relatively simple speed adjustment strategy often leads to fan vibration, creating a positive feedback loop that causes fluctuating temperature readings and affects the accurate judgment of the temperature status. Utility Model Content

[0005] To address the aforementioned technical problems, this invention proposes a stepped temperature encoding circuit based on parallel multi-channel hysteresis comparators for jitter reduction. This purely hardware circuit utilizes NTC thermistors, comparators, priority encoders, resistors, capacitors, and other components. Through accurate temperature zone division and smooth fan speed control, this circuit effectively reduces jitter and ensures stable operation of the equipment in high-temperature environments.

[0006] To achieve the above objectives, this utility model provides the following technical solution: a stepped temperature encoding circuit based on parallel anti-jitter multi-channel hysteresis comparators, including an NTC temperature acquisition circuit, a multi-channel inverting hysteresis comparator circuit, and a priority encoding circuit;

[0007] Multiple inverting hysteresis comparator circuits are connected in parallel. Each inverting hysteresis comparator circuit includes a comparator U1A, resistors R1, R2, R3, and R4. The inverting input of comparator U1A is connected to the output of the NTC temperature acquisition circuit. Resistors R1 and R2 are connected in series to form a reference network. The intermediate node of the reference network serves as a reference voltage source connected to the non-inverting input of comparator U1A. Resistor R3 is connected across the output and non-inverting input of comparator U1A. Resistor R4 is configured at the output of comparator U1A as a state holding element. The multiple inverting hysteresis comparator circuit consists of n circuits, with outputs TEMP1, TEMP2, ..., TEMPn, where n ≥ 2.

[0008] The priority encoding circuit includes a priority encoder U2. Each pin of the input terminal of the priority encoder U2 is connected in an orderly manner to the output terminal of the n-channel inverting hysteresis comparator circuit. TEMP1 corresponds to the lowest temperature range, TEMPn corresponds to the highest temperature range, the input channel with the highest priority of the priority encoder U2 corresponds to TEMP1, and the input channel with the lowest priority corresponds to TEMPn. The output terminal of the priority encoding circuit is used to output the encoding results of different temperature ranges.

[0009] Furthermore, the NTC temperature acquisition circuit includes an NTC thermistor R6 and a resistor R5; one end of the NTC thermistor R6 is connected to the power ground GND; the other end of the NTC thermistor R6 is connected to one end of the resistor R5; and the other end of the resistor R5 is connected to the power supply VDD.

[0010] Furthermore, the inverting hysteresis comparator circuit includes resistors R1, R2, R3, and R4, capacitor C1, and comparator U1A; one pin of resistor R1 is connected to the power supply VDD; the other pin of resistor R1 is connected to one pin of resistor R2 and also to the non-inverting input pin of comparator U1A; the other pin of resistor R2 is connected to the power supply ground GND; one pin of resistor R3 is connected to the non-inverting input pin of comparator U1A; the other pin of resistor R3 is connected to the comparator U1A... The output pins of the capacitor are connected to one end of the resistor R4; the other end of the resistor R4 is connected to the power supply VDD; one end of the capacitor C1 is connected to the power supply VDD and to the positive power supply pin of the comparator U1A; the other end of the capacitor C1 is connected to the power supply ground GND; the negative power supply pin of the comparator U1A is connected to the power supply ground GND; the intermediate node connecting the other end of the NTC thermistor R6 and one end of the resistor R5 is connected to the inverting input pin of the comparator U1A.

[0011] Furthermore, the n-channel inverting hysteresis comparator circuit is an 8-channel inverting hysteresis comparator circuit, with output terminals TEMP1, TEMP2, ..., TEMP8 respectively; the priority encoding circuit includes ports IO1, IO2, IO3, IO4 and a priority encoder U2; the priority encoder U2 includes: input pins D7-D0, enable pin EI, and output pins A0, A1, A2, GS; the input pins D7-D0 of the priority encoder U2 are respectively connected to the output terminal TEMP1 of the 8-channel inverting hysteresis comparator circuit. TEMP8 is connected in sequence; the enable pin EI of priority encoder U2 is connected to the power ground GND; the output pin A0 of priority encoder U2 is connected to port IO1; the output pin A1 of priority encoder U2 is connected to port IO2; the output pin A2 of priority encoder U2 is connected to port IO3; the output pin GS of priority encoder U2 is connected to port IO4; port IO4 is the highest bit of the code, IO1 is the lowest bit of the code, and the code value IO[4:1] = 1111 & 0111 ~ 0000, a total of 9 codes, dividing 9 temperature ranges.

[0012] The technical effects and advantages provided by this utility model in the above technical solution are as follows:

[0013] 1. This utility model introduces hysteresis comparator technology, sets upper and lower thresholds, eliminates minute signal jumps, reduces fan vibration, and improves anti-vibration capability;

[0014] 2. The hysteresis comparator of this utility model features a multi-channel parallel design, outputting a stepped temperature signal to improve the accuracy of temperature judgment;

[0015] 3. In this invention, temperature changes are processed in segments by a hysteresis comparator and then converted into interval codes by an encoder, simplifying the control logic.

[0016] 4. This utility model supports multi-probe acquisition and multi-encoder expansion, comprehensively improving system reliability and safety through temperature monitoring;

[0017] 5. This utility model reduces noise, improves equipment stability, and enhances user experience by reducing fan vibration and temperature fluctuations. Attached Figure Description

[0018] Figure 1 This is a circuit structure diagram of the present invention;

[0019] Figure 2 This is the truth graph for SN74HC148. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0021] Example

[0022] This embodiment describes a stepped temperature encoding circuit based on parallel multi-channel hysteresis comparators for jitter suppression, comprising an NTC temperature acquisition circuit, a multi-channel inverting hysteresis comparator circuit, and a priority encoding circuit, which are connected sequentially as follows: Figure 1 As shown.

[0023] The NTC temperature acquisition circuit includes an NTC thermistor R6 and a resistor R5. One pin of the NTC thermistor R6 is connected to the power ground (GND); the other pin of the NTC thermistor R6 is connected to one pin of the resistor R5; the other pin of the resistor R5 is connected to the power supply (VDD). Temperature acts as an input quantity on the NTC thermistor R6, producing an impedance change. The midpoint of the series connection between resistor R5 and the NTC thermistor R6 serves as the output terminal, generating a corresponding voltage change in response to the temperature change.

[0024] In this embodiment, the multi-channel inverting hysteresis comparator circuit is an 8-channel inverting hysteresis comparator circuit, which is connected in parallel. The comparators in the 8-channel inverting hysteresis comparator circuit are named sequentially as (U1A, U1B, ..., U4A, U4B). The inverting hysteresis comparator circuit includes resistors R1 (R9), R2 (R8), R3 (R7), R4 (R10), capacitor C1 (C2), and comparator U1A (U4B). One pin of resistor R1 (R9) is connected to the power supply VDD; the other pin of resistor R1 (R9) is connected to one pin of resistor R2 (R8) and also to the non-inverting input pin of comparator U1A (U4B); the other pin of resistor R2 (R8) is connected to the power ground GND; one pin of resistor R3 (R7) is connected to the non-inverting input pin of comparator U1A (U4B); the other pin of resistor R3 (R7) is connected to the output pin of comparator U1A (U4B) and also to the non-inverting input pin of resistor R4 (R10). One end of resistor R10 is connected; the other end of resistor R4 (R10) is connected to power supply VDD; one end of capacitor C1 (C2) is connected to power supply VDD and to the positive power supply pin of comparator U1A (U4B); the other end of capacitor C1 (C2) is connected to power ground GND; the negative power supply pin of comparator U1A (U4B) is connected to power ground GND; the intermediate node connecting the other end of NTC thermistor R6 and one end of resistor R5 is connected to the inverting input pin of comparator U1A (U4B); the output pins of comparators (U1A, U1B, ..., U4A, U4B) are named TEMPn (n = 1, 2, ..., 8) for ease of subsequent description.

[0025] The core precision hysteresis comparator module of the inverting hysteresis comparator circuit is comparator U1A (U4B). The inverting input of comparator U1A (U4B) is connected to the output of the NTC temperature acquisition circuit. Resistors R1 (R9) and R2 (R8) are connected in series to form a reference network. The middle node serves as a reference voltage source connected to the non-inverting input of comparator U1A (U4B). The feedback network is connected between the output and non-inverting input of comparator U1A (U4B) through resistor R3 (R7), forming a closed-loop feedback regulation mechanism to dynamically adjust the dual thresholds (upper limit Vrefn_TH+ and lower limit Vrefn_TH-). Resistor R4 (R10) is configured at the output of comparator U1A (U4B) as a state holding element. Together with the open-drain output of comparator U1A (U4B), a push-pull level conversion structure is constructed to ensure that the output TEMPn can quickly establish a stable high and low level state when the temperature exceeds the limit / recovers.

[0026] The priority encoding circuit mainly includes priority encoder U2, whose capacitor and power supply are omitted, but still function as part of the priority encoding circuit. The input pin D7 of priority encoder U2 is connected to the output pin TEMP1 of comparator U1A. The input pins D6 to D1 of priority encoder U2 are connected to the output pins TEMP2 to TEMP7 of the 8-channel inverting hysteresis comparator circuit in sequence. The input pin D0 of priority encoder U2 is connected to the output pin TEMP8 of comparator U4B. The enable pin EI of priority encoder U2 is connected to power ground GND. The output pin A0 of priority encoder U2 is connected to port IO1. The output pin A1 of priority encoder U2 is connected to port IO2. The output pin A2 of priority encoder U2 is connected to port IO3. The output pin GS of priority encoder U2 is connected to port IO4. Port IO4 is the highest bit of the encoding, and IO1 is the lowest bit of the encoding. The encoding value IO[4:1] = 1111 & 0111 ~ 0000, a total of 9 codes, which can divide 9 temperature ranges.

[0027] The core module of the priority encoding circuit is the priority encoder U2. Its input pins (D7~D0) are connected in an orderly manner to the outputs (TEMP1~TEMP8) of the multi-channel inverting hysteresis comparator. TEMP1 corresponds to the lowest temperature range, and TEMP8 corresponds to the highest temperature range. The highest priority input channel D7 of the priority encoder U2 corresponds to TEMP1, and the lowest priority input channel D0 corresponds to TEMP8. The output terminal IO[4:1] of the priority encoding circuit is used to output the encoding results of different temperature ranges.

[0028] The specific working principle is as follows:

[0029] Figure 1 In the NTC temperature acquisition circuit described, the power supply VDD = 5V, the NTC thermistor R6 is 1% / 10K / B = 3450K, and the resistor R5 is 1% / 10K. According to the resistance-temperature characteristic table, R6 = 10K at 25℃. To facilitate the description of the working principle, the temperature is divided into 9 temperature ranges, as shown in Table 1. The resistor R5 and the NTC thermistor R6 are connected in series for voltage division, and the output is connected to the inverting input of the comparator. The impedance of the inverting input is relatively large, approximately an open circuit (a few mV deviation), and the Vin voltage at different temperature boundaries can be calculated.

[0030] Table 1

[0031] -40＜T1≤40℃ R6 = 10K / 25℃ (non-boundary) Vin = 2.5V / 25℃ 40＜T2≤45℃ R6 = 5.782K / 40℃ Vin = 1.832V / 40℃ 45＜T3≤50℃ R6 = 4.867K / 45℃ Vin = 1.637V / 45℃ 50＜T4≤55℃ R6 = 4.116 K / 50℃ Vin = 1.458V / 50℃ 55＜T5≤60℃ R6 = 3.498K / 55℃ Vin = 1.296V / 55℃ 60＜T6≤65℃ R6 = 2.986 K / 60℃ Vin = 1.15V / 60℃ 65＜T7≤70℃ R6 = 2.56K / 65℃ Vin = 1.019V / 65℃ 70＜T8≤75℃ R6 = 2.203K / 70℃ Vin = 0.903V / 70℃ 75＜T9≤150℃ R6 = 1.904K / 75℃ Vin = 0.8V / 75℃

[0032] Figure 1In the inverse hysteresis comparison circuit described therein, the resistor R1 adopts 1% / 10K; the resistor R2 adopts 1% / 5.782K. Considering that such a resistor may not exist in practical situations, the resistor R2 / R8 can be replaced by a 1K adjustable resistor connected in series with a 1% chip resistor, so that the 1K adjustable resistor has higher adjustment accuracy than a single 10K adjustable resistor; the model of the comparator U1A is LM393. The traditional design uses a single-limit comparator for discrimination, that is, when the non-inverting input terminal Vp of the comparator is greater than the inverting input terminal Vn, the output terminal Vo outputs a high level, and when Vp is less than Vn, Vo outputs a low level; the divided voltage Vp(Vref1) of the voltage dividing resistors R1 and R2 is 1.832V; when the temperature rises to 40°C, the resistance value of the thermistor decreases from 10K (assuming the initial temperature is 25°C) to 5.782K (at 40°C), at this time Vn(Vin) decreases from 2.5V to 1.832V (as shown in Table 1); when the temperature is higher than 40°C, Vin continues to decrease, and when Vin<Vref1, the comparator output terminal Vo outputs a high level (TEMP1=1), at this time the trigger flag triggers the main controller, and the main controller performs acceleration speed regulation on the fan, resulting in a temperature decrease; when the temperature is lower than 40°C, Vin increases, and when Vin>Vref1, the comparator output terminal Vo outputs a low level (TEMP1=0), at this time the trigger flag is invalid, the main controller performs deceleration speed regulation on the fan, which further leads to an increase in temperature; finally a positive feedback is formed, and the speed regulation is repeatedly performed back and forth around 40°C, resulting in fan jitter and noise generation.Compared with the single-limit comparator, a hysteresis comparator circuit is adopted, in which the feedback network is connected across the output terminal and the non-inverting input terminal of the comparator U1A via the resistor R3; when the temperature rises from 25°C and is lower than 40°C, Vin>Vref1, TEMP1=0, the end of the resistor R3 connected to the output terminal of the comparator is equivalent to being connected to the power supply GND (that is, output low voltage Vol), which is equivalent to the parallel connection of R2 and R3. According to the parallel resistance principle, the introduction of R3 actually reduces the equivalent impedance of R2, so that Vref1 decreases. Vref1_TH- is set as the lower threshold after the decrease, and the corresponding temperature increases by X1°C additionally; when the temperature is higher than (40+X1)°C, Vin<Vref1_TH-, TEMP1=1, at this time the end of the resistor R3 connected to the output terminal of the comparator is equivalent to being connected to the power supply VDD (that is, output high voltage Voh), which is equivalent to the parallel connection of R1 and R3. Similarly, the introduction of R3 actually reduces the equivalent impedance of R1, so that Vref1 increases. Vref1_TH+ is set as the upper threshold after the increase, and the corresponding temperature decreases by X2°C; at this moment, since Vp was originally Vref1_TH-, when TEMP1 switches to 1, Vp instantly becomes Vref1_TH+, and because Vin<Vref1_TH+, TEMP1 still remains at high level instead of decelerating immediately. Only when the temperature is lower than (40-X2)°C, TEMP1 switches to 0 and the speed will be reduced again. There is a temperature difference of (X1+X2)°C in between, so even if the fan speed regulation causes the temperature to drop, the flag state will not be changed immediately, thereby eliminating frequent jitter of the fan. According to the node current method and Ohm's law, the threshold calculation formula is obtained as follows:.

[0033]

[0034] Let Vol=0, R3=m·R2

[0035]

[0036] Let Voh→VDD, R3=m·R2, R4=n·R3, then n+1→1, and n≠0

[0037] The corresponding threshold can be set, and the coefficient m can be calculated according to the formula, or the corresponding threshold can be calculated by giving the coefficient m. The smaller the m, the wider the range of the upper and lower thresholds, the larger the (X1+X2)℃ value, and the stronger the anti-interference ability. The larger the m value, the narrower the range of the upper and lower thresholds, the smaller the (X1+X2)℃ value, and the weaker the anti-interference ability. To simplify the design, R3 can also be set to be fixed, which will not be elaborated here. Similarly, resistor R9 uses 1% / 10K, and resistor R8 uses 1% / 1.904K. Assuming R7 = 10·R9, substituting into the above calculation formula, we can obtain the upper and lower threshold values ​​Vref8_TH+ and Vref8_TH-. Based on the threshold voltage, we can deduce the temperature range of the NTC thermistor from (75-Y2)℃ to (75+Y1)℃. It should be noted that the upper threshold voltage corresponds to the lower temperature limit, and the lower threshold voltage corresponds to the upper temperature limit. In other words, when the temperature is higher than (75+Y1)℃, TEMP8 = 1; when the temperature is lower than (75-Y2)℃, TEMP8 = 0. In addition, to make Voh approach VDD, resistor R4 can be chosen to be 1% 1K for easier calculation.

[0038] Figure 1 The priority encoding circuit described above mainly includes priority encoder U2, model number SN74HC148; its truth diagram is as follows: Figure 2 As shown. The input pins D7 to D0 of the priority encoder U2 have decreasing priorities in sequence; therefore, the highest priority pin D7 should be connected to the output pin TEMP1 with the highest priority in the temperature range, and the other pins are connected in sequence. The output pin A0 of the priority encoder U2 is connected to port IO1; the output pin A1 of the priority encoder U2 is connected to port IO2; the output pin A2 of the encoder U2 is connected to port IO3; the output pin GS of the priority encoder U2 is connected to port IO4; the EO pin of the priority encoder U2 can be used as an encoder extension to connect to the next level EI pin. The circuit principle after the extension is the same, which will not be described in detail here; in addition, port IO4 is the highest bit of the encoding, and IO1 is the lowest bit of the encoding. The available encoding values ​​IO[4:1] = 1111 & 0111 ~ 0000, a total of 9 codes, can be used to divide 9 temperature ranges as shown in Table 2.

[0039] Table 2

[0040]

[0041]

[0042] In summary, this invention employs hysteresis comparator technology to set a threshold and eliminate jumps, thereby enhancing anti-jitter capability; it adopts a multi-channel parallel design to flexibly set the hysteresis interval and output a stepped temperature signal, which can improve system stability; the temperature interval is segmented and converted into interval encoding, and the priority encoder simplifies the temperature control strategy; it supports multi-probe acquisition and expansion, which can better achieve precise temperature identification and accurate control.

[0043] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0044] The preferred embodiments of this utility model disclosed above are merely illustrative of the present utility model. These preferred embodiments do not exhaustively describe all details, nor do they limit the utility model to any specific implementation. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A stepped temperature encoding circuit based on parallel anti-jitter multi-channel hysteresis comparators, characterized in that: Includes an NTC temperature acquisition circuit, a multi-channel inverting hysteresis comparator circuit, and a priority encoding circuit; Multiple inverting hysteresis comparator circuits are connected in parallel. Each inverting hysteresis comparator circuit includes a comparator U1A, resistors R1, R2, R3, and R4. The inverting input of comparator U1A is connected to the output of the NTC temperature acquisition circuit. Resistors R1 and R2 are connected in series to form a reference network. The intermediate node of the reference network serves as a reference voltage source connected to the non-inverting input of comparator U1A. Resistor R3 is connected across the output and non-inverting input of comparator U1A. Resistor R4 is configured at the output of comparator U1A as a state holding element. The multiple inverting hysteresis comparator circuit consists of n circuits, with outputs TEMP1, TEMP2, ..., TEMPn, where n ≥ 2. The priority encoding circuit includes a priority encoder U2. Each pin of the input terminal of the priority encoder U2 is connected in an orderly manner to the output terminal of the n-channel inverting hysteresis comparator circuit. TEMP1 corresponds to the lowest temperature range, TEMPn corresponds to the highest temperature range, the input channel with the highest priority of the priority encoder U2 corresponds to TEMP1, and the input channel with the lowest priority corresponds to TEMPn. The output terminal of the priority encoding circuit is used to output the encoding results of different temperature ranges.

2. The stepped temperature encoding circuit based on parallel anti-jitter multi-channel hysteresis comparators according to claim 1, characterized in that: The NTC temperature acquisition circuit includes an NTC thermistor R6 and a resistor R5; one pin of the NTC thermistor R6 is connected to the power ground GND; the other pin of the NTC thermistor R6 is connected to one pin of the resistor R5; the other pin of the resistor R5 is connected to the power supply VDD.

3. The stepped temperature encoding circuit based on parallel anti-jitter multi-channel hysteresis comparators according to claim 2, characterized in that: The inverting hysteresis comparator circuit includes resistors R1, R2, R3, and R4, capacitor C1, and comparator U1A. One pin of resistor R1 is connected to the power supply VDD; the other pin of resistor R1 is connected to one pin of resistor R2 and also to the non-inverting input pin of comparator U1A; the other pin of resistor R2 is connected to the power supply ground GND; one pin of resistor R3 is connected to the non-inverting input pin of comparator U1A; the other pin of resistor R3 is connected to the output of comparator U1A. One end of the capacitor is connected to the pin of the NTC thermistor R6 and the other end of the resistor R4; the other end of the resistor R4 is connected to the power supply VDD; one end of the capacitor C1 is connected to the power supply VDD and the positive power supply pin of the comparator U1A; the other end of the capacitor C1 is connected to the power supply ground GND; the negative power supply pin of the comparator U1A is connected to the power supply ground GND; the intermediate node connecting the other end of the NTC thermistor R6 and one end of the resistor R5 is connected to the inverting input pin of the comparator U1A.

4. A stepped temperature encoding circuit based on parallel anti-jitter multi-channel hysteresis comparators according to claim 1, characterized in that: The n-channel inverting hysteresis comparator circuit is an 8-channel inverting hysteresis comparator circuit, with outputs TEMP1, TEMP2, ..., TEMP8 respectively. The priority encoding circuit includes ports IO1, IO2, IO3, IO4, and a priority encoder U2. The priority encoder U2 includes input pins D7-D0, an enable pin EI, and output pins A0, A1, A2, and GS. The input pins D7-D0 of the priority encoder U2 are respectively connected to the outputs TEMP1-TEMP8 of the 8-channel inverting hysteresis comparator circuit. MP8 is connected in sequence; the enable pin EI of priority encoder U2 is connected to the power ground GND; the output pin A0 of priority encoder U2 is connected to port IO1; the output pin A1 of priority encoder U2 is connected to port IO2; the output pin A2 of priority encoder U2 is connected to port IO3; the output pin GS of priority encoder U2 is connected to port IO4; port IO4 is the highest bit of the code, IO1 is the lowest bit of the code, and the code value IO[4:1] = 1111 & 0111 ~ 0000, a total of 9 codes, dividing 9 temperature ranges.

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