Single bus communication circuit

Abstract

The utility model relates to a single bus communication circuit, single bus communication circuit includes: data link, the data bus of single root line forms data channel, and utilizes the data channel formed to carry out the bus communication required, control link is connected with data link adaptation, is used for configuring the bus communication mode of data link, wherein, when control link detects and determines the data bus of connected data link to be in the fault state, and the fault state of data bus is caused by the bus equipment that hangs on data link, control link configuration bus communication mode is the bus mode that separates from. The utility model can effectively avoid the bus paralysis caused by bus equipment failure, improve the security and reliability of bus communication.

Description

Technical Field

[0001] This utility model relates to a communication circuit, and more particularly to a single-bus communication circuit. Background Technology

[0002] In existing technologies, there are various communication scenarios that use buses, such as current sensors using RS485 or serial single bus communication methods. Generally, RS485 communication bus requires two wires and the communication address needs to be set in advance. When the bus device fails, it can easily lead to the paralysis of the entire bus.

[0003] Although a single-wire serial bus only requires one wire, there are still issues such as the need to pre-set the address and the potential for the entire bus to fail when a bus device malfunctions.

[0004] Therefore, improving the reliability of bus communication is a pressing technical challenge that needs to be addressed in bus-based communication scenarios. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a single-bus communication circuit that can effectively avoid bus paralysis caused by bus device failure and improve the security and reliability of bus communication.

[0006] According to the technical solution provided by this utility model, a single-bus communication circuit is provided, the single-bus communication circuit comprising: A data link is a data channel formed based on a single-wire data bus, and the required bus communication is performed using the formed data channel. A control link, adapted and connected to the data link, is used to configure the bus communication mode of the data link, wherein... When the control link detects that the data bus of the connected data link is in a fault state, and the fault state of the data bus is caused by the bus device connected to the data link, the control link configures the bus communication mode to bus disconnect mode; so that the bus device is disconnected from the data bus, and the data can be transmitted as required through the data channel of the data link.

[0007] When multiple single-bus communication circuits exist, all single-bus communication circuits are connected in series via a data bus. For each single-bus communication circuit, the data link within the single-bus communication circuit includes at least a bus data receiving circuit and a bus data transmitting circuit disposed on the data bus, wherein... The bus device is adapted to connect with the bus data receiving circuit and the bus data transmitting circuit. For any two adjacent single-bus communication circuits, the bus data transmitting circuit of the preceding single-bus communication circuit is adapted and connected to the bus data receiving circuit of the following single-bus communication circuit through the data bus.

[0008] The bus data receiving circuit includes a first data receiving unit and a second data receiving unit, and the bus data transmitting circuit includes a first data transmitting unit, a second data transmitting unit, and a third data transmitting unit, wherein... The second data receiving unit is connected to the second data transmitting unit via a data bus; For any data link, the bus device is adapted to connect with the first data receiving unit, the first data transmitting unit, and the third data transmitting unit so that the bus device is attached to the data link.

[0009] The first data receiving unit includes a tri-state gate U3A and a NOT gate U2E, wherein, The tri-state gate U3A can use a chip of model SN74HCS125DYYR. The input terminal of the tri-state gate U3A is connected to pin 1 of interface J1 to achieve connection with the data bus. The output terminal of the tri-state gate U3A is connected to the bus device. The VCC terminal of the tri-state gate U3A is connected to the power supply VCC_3.3V and one end of capacitor C7. The other end of capacitor C7 is connected to the GND terminal and SGND of the tri-state gate U3A. The enable terminal of the tri-state gate U3A is connected to the output terminal of the NOT gate U2E. The input terminal of the NOT gate U2E is connected to the receive enable signal. The input terminal of the NOT gate U2E is also connected to SGND through resistor R10.

[0010] The second data receiving unit includes a tri-state gate U1A, resistor R1, and resistor R4, wherein... Tri-state gates U1A and U3A can use the same model chip. The input terminal of tri-state gate U1A and one end of resistor R1 are connected to pin 1 of interface J1. The other end of resistor R1 is connected to the power supply VCC_3.3V. The VCC terminal of tri-state gate U1A is connected to one end of capacitor C4, one end of capacitor C6, and the cathode of diode chip D1. The other ends of capacitors C4 and C6 are connected to the GND and SGND terminals of tri-state gate U1A, respectively. Diode chip D1 can be a BAT5AC chip, which contains two diodes. The cathodes of the two diodes are connected to each other to form the cathode of diode chip D1. In addition, the anode of one diode is connected to the power supply VCC_3.3V, and the anode of the other diode is connected to pin 1 of interface J1.

[0011] The first data transmission unit may include a tri-state gate U1D and a NOT gate U2D, wherein, The input of the tri-state gate U1D is connected to the control link adapter, and the output of the tri-state gate U1D is connected to the data bus and pin 1 of interface J2. The enable terminal of the tri-state gate U1D is connected to the output terminal of the NOT gate U2D, and the input terminal of the NOT gate U2D is connected to the transmit enable signal. When the transmit enable signal TX_EN is high, the NOT gate U2D outputs a low level, thereby driving the tri-state gate U1D to conduct. When the tri-state gate U1D is conducting, the bus device can send data to the data bus through the tri-state gate U1D. When the output of the NOT gate U2D is high, the tri-state gate U1D is turned off. The second data transmission unit may include a tri-state gate U1B, a resistor R8, and a resistor R2. The output of tri-state gate U1Bd is connected to the output of tri-state gate U1A via a data bus. The input of tri-state gate U1B is connected to pin 1 of interface J2 and one end of resistor R2. The other end of resistor R2 is connected to power supply VCC_3.3V. The enable terminal of tri-state gate U1B is connected to SGND via resistor R8. The enable terminal of tri-state gate U1B also receives the transmission direction control signal. When the data bus is idle, it is pulled high through resistor R2. Since the enable terminal of tri-state gate U1B is connected to SGND through resistor R8, when the transmit direction control signal is not high, tri-state gate U1B is in the conducting state, and the data output by tri-state gate U1A can be transmitted to pin 1 of interface J2 through tri-state gate U1B. When the transmit direction control signal is high, tri-state gate U1B is turned off, and the data output by tri-state gate U1A cannot be transmitted to pin 1 of interface J2. The third data transmission unit includes a tri-state gate U1C, wherein the input of tri-state gate U1C is connected to the input of the control processor, the output of tri-state gate U1C is connected to the output of tri-state gate U1B, and the enable terminal of tri-state gate U1C receives a bus fault status signal. When the data bus is in a fault state, the bus fault state signal is low, and the tri-state gate U1C is turned on; when the data bus is in a normal state, the bus fault signal is high, and the tri-state gate U1C is turned off.

[0012] The control link includes a data transceiver control circuit, a processor operation detection circuit, and a bus fault detection circuit, wherein... The bus fault detection circuit is connected to the data bus within the data link and is used to detect the fault status of the data bus. The processor operation detection circuit is connected to the bus device and the data transceiver control circuit to detect the operating status of the bus device; The data transceiver control circuit is connected to the bus device and data link adapter to configure the bus communication mode of the data link.

[0013] The bus fault detection circuit includes NOT gate U8F and NOT gate U8E, wherein, The input terminal of NOT gate U8F is connected to the data bus. The output terminal of NOT gate U8F is connected to one end of resistor R15, one end of resistor R18, one end of capacitor C15, and one end of resistor R25. The other end of resistor R15 is connected to the cathode of diode D2. The other end of resistor R81 is connected to one end of resistor R22, one end of capacitor C16, the anode of diode D2, and the input terminal of NOT gate U8E. The other ends of capacitor C15 and resistor R25 are connected to the base terminal of PNP transistor Q1. The source terminal of PNP transistor Q1 is connected to the other end of resistor R22. The other end of capacitor C16 and the drain terminal of PNP transistor Q1 are both connected to SGND. The output of NOT gate U8E serves as the output of bus fault detection circuit 7. When the data bus connected to NOT gate U8F is low, the data bus is inverted by NOT gate U8F and charged by resistor R18. When the data bus remains low for a period of time or longer, and the voltage on capacitor C16 reaches the minimum voltage of 1.9V required for the high level input of NOT gate U8E, NOT gate U8E outputs a low-level bus fault status signal. When the data bus returns to a high level, it is inverted by NOT gate U8F, and then the charge in capacitor C16 is quickly released through resistor R15, diode D2, capacitor C15, resistor R22 / R25, and PNP transistor Q1. The input of NOT gate U8E is low, and NOT gate U8E outputs a high-level bus fault status signal.

[0014] The data transceiver control circuit includes a transceiver enable generation unit, a receive direction control signal generation unit, and a transmit direction control signal generation unit, wherein... The transmit / receive enable generation unit can generate receive enable signals and transmit enable signals, the receive direction control signal generation unit can generate receive direction control signals, and the transmit direction control signal generation unit can generate transmit direction control signals. The transmit / receive enable generation unit includes a D flip-flop U9 and an NOT gate U8D. The input terminal of the NOT gate U8D is connected to one end of resistor R20, one end of capacitor C14, and one end of resistor R17. The other ends of resistor R20 and capacitor C14 are both connected to SGND. The other end of resistor R17 is connected to the cathode of Schottky diode D3. The anode of Schottky diode D3 is connected to capacitor C13 and one end of resistor R19. The other end of resistor R19 is connected to SGND. The other end of capacitor C13 is connected to the bus device operation signal. The output of NOT gate U8D is connected to the D flip-flop U9. The enable pins of tri-state gates U6C and U3D are connected. The input pin of tri-state gate U6C is connected to SGND via resistor R21, and the input pin of tri-state gate U6C is also connected to the data receive control signal in the data transmit / receive control signal. The input pin of tri-state gate U3D is connected to SGND via resistor R23, and the input pin of tri-state gate U3D is also connected to the data transmit control signal in the data transmit / receive control signal. The GND terminal of D flip-flop U9 is connected to SGND. The D terminal of D flip-flop U9 is connected to the power supply VCC_3.3V through resistor R14. The D terminal of D flip-flop U9 is connected to SGND through resistor R13. The CLK terminal of D flip-flop U9 is connected to the bus device running status signal. The VCC terminal of D flip-flop U9 is connected to the power supply VCC_3.3V and one end of capacitor C10. The other end of capacitor C10 is connected to SGND. The Q terminal of the D flip-flop U9 is connected to one end of resistor R12 and the input terminal of tri-state gate U6B. The enable terminal of tri-state gate U6B is connected to the output terminal of OR gate U11B. One input terminal of OR gate U11B is connected to the output terminal of tri-state gate U6C, one end of resistor R16 and the first input terminal of OR gate U5D. The other input terminal of OR gate U11B is connected to the output terminal of tri-state gate U3D, one end of resistor R26 and the first input terminal of OR gate U11A. The other ends of resistor R16 and resistor R26 are both connected to SGND. The output of tri-state gate U6B is connected to the second input of OR gate U5D, one end of resistor R24 ​​and the second input of OR gate U11A. The other end of resistor R24 ​​is connected to SGND. The VCC terminal of OR gate U11A is connected to power supply VCC_3.3V and one end of capacitor C17. The other end of capacitor C17 and GND terminal of OR gate U11A are both connected to SGND. The output of OR gate U5D outputs a receive enable signal, and the output of OR gate U11A outputs a send enable signal.

[0015] The receiving direction control signal generation unit includes an XOR gate U7A and a NOT gate U8A. The first input terminal of the XOR gate U7A and the input terminal of the NOT gate U8A are connected to the input terminal of the tri-state gate U6C. The second input terminal of the XOR gate U7A is connected to the input terminal of the tri-state gate U3D. The output terminal of the XOR gate U7A is connected to the first input terminal of the OR gate U5C. The second input terminal of the OR gate U5C is connected to the output terminal of the NOT gate U8B. The input terminal of the NOT gate U8B is connected to the output terminal of the OR gate U5D. The output of OR gate U5C is connected to the first input of AND gate U10A, the second input of AND gate U10A is connected to the output of NOT gate U8A, the output of AND gate U10A is connected to the first input of AND gate U10B, and the second input of AND gate U10B is connected to the Q terminal of D flip-flop U9. The receiving direction control signal can be output through the output of AND gate U10B. The VCC terminal of NOT gate U8A is connected to power supply VCC_3.3V and one end of capacitor C12. The other end of capacitor C12 and the GND terminal of NOT gate U8A are both connected to SGND. The VCC terminal of XOR NOT gate U7A is connected to power supply VCC_3.3V and one end of capacitor C8. The other end of capacitor C8 and the GND terminal of XOR NOT gate U7A are both connected to SGND. The VCC terminal of AND gate U10A is connected to power supply VCC_3.3V and one end of capacitor C9. The other end of capacitor C9 and the GND terminal of AND gate U10A are both connected to SGND. The transmission direction control signal generation unit includes AND gate U10C, AND gate U12A, and AND gate U12B, wherein, The first input of AND gate U10C is connected to the output of OR gate U5D, and the second input of AND gate U10C is connected to the output of OR gate U11A; the first input of AND gate U12A is connected to the output of XOR NOT gate U7A, the second input of AND gate U12A is connected to the output of NOT gate U13C, and the input of NAND gate U13C is connected to the input of tri-state gate U3D. One input of AND gate U12B is connected to the output of AND gate U10C, and the other input of AND gate U12B is connected to the output of AND gate U12A. The output of AND gate U12B outputs the transmission direction control signal.

[0016] The advantages of this invention are: when a data bus failure is caused by a bus device, the control link is configured to switch the bus communication mode to bus disconnection mode, allowing the bus device to disconnect from the corresponding data link. This effectively avoids bus paralysis caused by bus device failure and improves the security and reliability of bus communication. Address allocation processing can determine the communication address of each single-bus communication circuit, avoiding the inconvenience of pre-setting communication addresses in existing technologies and improving the convenience and adaptability of single-bus communication. Attached Figure Description

[0017] Figure 1 This is a circuit block diagram of one embodiment of the single-bus communication circuit of this utility model.

[0018] Figure 2 This is a system block diagram of one embodiment of the single-bus communication system of this utility model.

[0019] Figure 3 This is a circuit schematic diagram of one embodiment of the bus data receiving circuit of this utility model.

[0020] Figure 4 This is a circuit schematic diagram of one embodiment of the bus data transmission circuit of this utility model.

[0021] Figure 5 This is a circuit diagram of one embodiment of the fault alarm circuit of this utility model.

[0022] Figure 6 This is a circuit diagram of one embodiment of the data transceiver control circuit of this utility model.

[0023] Figure 7 This is a circuit diagram of one embodiment of the processor operation detection circuit of this utility model.

[0024] Figure 8 This is a circuit diagram of one embodiment of the bus occupancy detection circuit of this utility model.

[0025] Figure 9 This is a circuit schematic diagram of one embodiment of the bus fault detection circuit of this utility model.

[0026] Figure 10 This is the truth table for the trigger U9 of this utility model.

[0027] Explanation of reference numerals in the attached diagram: 1-Bus data receiving circuit, 2-Bus data transmitting circuit, 3-Fault alarm circuit, 4-Data transceiver control circuit, 5-Processor operation detection circuit, 6-Bus occupancy detection circuit, 7-Bus fault detection circuit, 8-Control processor, 9-Current sensor, 10-Single bus communication circuit, 11-Terminal block, 12-Main unit, 13-Main unit processor, and 14-Data / power supply switching circuit. Detailed Implementation

[0028] The present invention will be further described below with reference to the specific accompanying drawings and embodiments.

[0029] To effectively avoid bus paralysis caused by bus device failure and improve the security and reliability of bus communication, this utility model provides a single-bus communication circuit 10. Specifically, the single-bus communication circuit 10 includes: A data link is a data channel formed based on a single-wire data bus, and the required bus communication is performed using the formed data channel. A control link, adapted and connected to the data link, is used to configure the bus communication mode of the data link, wherein... When the control link detects that the data bus of the connected data link is in a fault state, and the fault state of the data bus is caused by the bus device connected to the data link, the control link configures the bus communication mode to the bus disconnect mode. After entering the bus-off mode, bus devices are prohibited from receiving data from the data link and sending data to the data link. The data channel formed by the data link is configured to be in a bidirectional data flow state, so that the bus devices are disconnected from the data bus and data can be transmitted as required through the data channel of the data link.

[0030] It should be understood that bus devices can be existing devices that require bus communication. Figure 1 and Figure 2 An embodiment of a bus device is shown in the figure. Figure 1 and Figure 2 In this invention, the bus device includes a control processor 8 and several current sensors 9 adapted and connected to the control processor 8. Of course, the bus device can also take other forms, depending on whether it can meet the requirements of bus communication; these will not be listed here. It should be noted that when the bus device includes the control processor 8 and the current sensors 9, the control processor 8 has data processing capabilities. Therefore, the bus device in this invention mainly refers to the control processor 8, and the following description uses the control processor 8 to characterize the bus device. Furthermore, a single bus specifically refers to a single-wire data bus. The use of a single wire to form a data bus is consistent with existing technology and will not be elaborated here.

[0031] When using a single-wire data bus for bus communication, the voltage level on the data bus should be related to the communication state. For example, in the idle state, the data bus voltage level can be high, while when data transmission is being performed, the data bus voltage level should generally be low. Of course, the data bus voltage level can also be in other states. The following explanation uses the example of a high voltage level in the idle state and a low voltage level during data transmission. For a single-wire data bus, the bus failure condition can be consistent with existing technology. For example, if the data bus voltage level remains low for an extended period, it can be considered that the data bus is in a bus failure state.

[0032] The single-bus communication circuit 10 of this invention includes a data link and a control link. The data link forms a data channel for required bus communication. It should be understood that the data link includes a data bus, and bus communication can include acquiring data from the data bus, sending data to the data bus, or transmitting data using the data bus to meet the requirements of bus communication. The control link configures the bus communication mode of the data link, i.e., controls the operating state of the data link to ensure that its operating state meets the requirements of bus communication.

[0033] In practical implementation, when the data bus is in a fault state, and the fault state is caused by a bus device, the control link is configured to switch the bus communication mode to bus disconnect mode. This separates the bus device from the data bus within the single-bus communication circuit. In bus disconnect mode, the bus device cannot receive data from the data link, nor can it send data to the data link. However, the data channel of the data link should be in a bidirectional data flow state. Thus, in bus disconnect mode, the data link mainly performs data transmission and cannot interact with the bus device. After separating the bus device that caused the fault state from the data bus, since there is no source causing the fault state, the data bus can recover from the bus paralysis, thereby improving the security and reliability of bus communication.

[0034] It should be noted that a data bus failure specifically refers to a data bus paralysis state. When the data channel is in a bidirectional data flow state, the data link within the current single-bus communication circuit only functions as a data transmission line. The detection and confirmation of a data bus failure state, as well as the configuration of the bus communication mode to off-bus mode, will be explained in detail below.

[0035] In one embodiment of this utility model, when multiple single-bus communication circuits 10 exist, all the single-bus communication circuits 10 are connected in series via a data bus, wherein... For any single-bus communication circuit 10, when the control link within the single-bus communication circuit 10 detects that the connected data bus is in a fault state, the following applies: Disconnect the single-bus communication circuits 10 adjacent to the current single-bus communication circuit 10 respectively. If the data link of the current single-bus communication circuit 10 can recover from the fault state, the bus device connected to the current single-bus communication circuit 10 sends a neighbor fault message to the data link. If all single-bus communication circuits 10 adjacent to the current single-bus communication circuit 10 are disconnected, and the data bus of the current single-bus communication circuit 10 is still in a fault state, then the bus communication mode of the current single-bus communication circuit 10 is configured as the bus disconnect mode.

[0036] It should be understood that in bus communication, there should generally be multiple single-bus communication circuits 10 in operation. In this case, all single-bus communication circuits 10 should be connected in series through the data bus, that is, the data links of all single-bus communication circuits 10 should be adapted and connected, such as at least making the data buses in each single-bus communication circuit 10 connected accordingly, specifically to meet the requirement of connecting the single-bus communication circuits 10 in series.

[0037] When multiple single-bus communication circuits 10 exist, each single-bus communication circuit 10 may be in a fault state. Therefore, the control link within each single-bus communication circuit 10 should have the ability to detect faults in the data bus. When a fault is detected in the data bus, the single-bus communication circuits 10 adjacent to the current single-bus communication circuit 10 can be disconnected. For example, if there are five serially connected single-bus communication circuits 10, and the current single-bus communication circuit is the second-ranked single-bus communication circuit 10, the first-ranked and third-ranked single-bus communication circuits 10 should be disconnected respectively. When disconnecting the first and third single-bus communication circuits 10 in the sequence, they can be disconnected sequentially or simultaneously, depending on the fault state after disconnection. For example, if the data link of the current single-bus communication circuit 10 can be restored from the fault state after disconnecting one adjacent single-bus communication circuit 10, then disconnecting the other adjacent single-bus communication circuit 10 is unnecessary. Otherwise, the other adjacent single-bus communication circuit 10 should be disconnected. Of course, if the data link of the current single-bus communication circuit 10 fails to be restored from the fault state, both adjacent single-bus communication circuits 10 should be disconnected simultaneously.

[0038] As explained above, the data link of the current single-bus communication circuit 10 can recover from a fault state. Specifically, this means that the data bus of the current single-bus communication circuit 10 can recover from a prolonged low-level state, such as returning to a high-level state. Disconnecting all single-bus communication circuits 10 adjacent to the current single-bus communication circuit 10 specifically means disconnecting one adjacent single-bus communication circuit 10 individually or simultaneously disconnecting two adjacent single-bus communication circuits 10. Disconnecting adjacent single-bus communication circuits 10 specifically means putting the data bus within the adjacent single-bus communication circuit 10 into a disabled state. In this state, data transmission cannot be performed using the disabled data bus. The method of disconnecting adjacent single-bus communication circuits 10 will be explained in detail below.

[0039] It should be understood that when a bus fault caused by an adjacent single-bus communication circuit 10 is ruled out, it is determined that the fault state within the current single communication bus circuit 10 should be caused by the corresponding bus device. Specifically, the corresponding bus device refers to the device connected to the data bus within the current communication bus circuit 10. As explained above, the bus communication mode of the current single-bus communication circuit 10 should be configured as off-bus mode. The configuration of the bus communication mode as off-bus mode can be found in the above explanation and will not be repeated here. Of course, when there is only one single-bus communication circuit 10, the bus communication mode should be directly configured as off-bus mode.

[0040] In one embodiment of this utility model, for any single-bus communication circuit 10, when the single-bus communication circuit 10 is adjacent to two functional unit circuits respectively, the bus communication mode configured in the control link within the current single-bus communication circuit 10 further includes a one-way transmission mode, a one-way reception mode, and / or a two-way reception and transmission mode, wherein, The functional unit circuit is either the host 12 or the single-bus communication circuit 10; When the bus communication mode is unidirectional transmission mode, the bus device is prohibited from receiving data from the data link. The bus device can send data to the data link and send the data to the next and adjacent single bus communication circuit 10 via the data link. When the bus communication mode is unidirectional receiving mode, the bus device can receive data from the data link and is prohibited from sending data to the data link, and the data channel is in a bidirectional data flow state. When the bus communication mode is bidirectional receive and transmit mode, the bus device can receive data from the data link and send data to the data link, and the data channel is in a bidirectional data flow state. When the data channel is in a bidirectional data flow state, the data in the data channel can be transmitted in the direction pointing towards the host 12 or in the direction away from the host 12.

[0041] It should be understood that in the operating scenario of the single-bus communication circuit 10, in addition to multiple single-bus communication circuits 10 connected in series, a host 12 is generally also included. The host 12 is connected to one of the single-bus communication circuits 10, such as... Figure 2 As shown, it is understandable that Figure 2 The diagram only shows the case where a single-bus communication circuit 10 is connected to the host 12. When multiple single-bus communication circuits 10 exist, the corresponding single-bus communication circuits 10 are connected in series with the host 12. Figure 2 Following the single-bus communication circuit 10, in addition to the single-bus communication circuit 10 located at the tail end, each single-bus communication circuit 10 is generally connected to two functional unit circuits. These functional unit circuits can be the host 12 or the single-bus communication circuit, such as... Figure 2 In the process, for the single-bus communication circuit that is ranked first, the two functional unit circuits should be the host 12 and the single-bus communication circuit 10, respectively. For the single-bus communication circuit 10 except for the one located at the tail end, both functional unit circuits should be single-bus communication circuits.

[0042] To meet the communication requirements between the host 12 and each single-bus communication circuit 10, the bus communication mode of each single-bus communication circuit 10 may include a one-way transmitting mode, a one-way receiving module, and / or a two-way receiving and transmitting mode. In the one-way transmitting mode, the bus device cannot receive data from the data link, but can send data to the data link. The data sent to the data link can be transmitted to the next adjacent single-bus communication circuit 10. At this time, the data channel can also realize direct data transmission, such as for... Figure 2 In the embodiments, Figure 2 The single-bus communication circuit 10 in the text is the current single-bus communication circuit, and the single-bus communication circuit 10 is ranked first. When there is an adjacent single-bus communication circuit 10, in the one-way transmission mode, the host 12 can directly transmit data to the single-bus communication circuit ranked second via the data bus of the single-bus communication circuit 10 ranked first. In addition, the bus device corresponding to the single-bus communication circuit 10 ranked first can send data to the bus communication circuit 10 ranked second via the data link. The working conditions of the one-way transmission mode in other cases can be referred to the example here.

[0043] It should be noted that receiving data from the data link specifically refers to obtaining data from the data bus within the data link, while sending data to the data link specifically refers to sending data to the data bus within the data link. The following situations all represent the same meaning, and can be referred to here for explanation.

[0044] When the bus communication mode is unidirectional receive mode, the bus device can receive data from the data link but cannot send data to the data link, and the data channel is in a bidirectional flow state, as described above for... Figure 2 In the example, if the first-ranked single-bus communication circuit 10 is the current single-bus communication circuit 10, then after the host 12 sends data to the data bus, the bus device corresponding to the current single-bus communication circuit 10 can receive data from the connected data link. Furthermore, the data sent by the host 12 to the data bus can be directly sent to the second-ranked single-bus communication circuit 10 via the data channel formed by the current single-bus communication circuit 10. In addition, since the data channel is in a bidirectional data flow state, when the second-ranked single-bus communication circuit 10 can send data to the data bus, both the first-ranked single-bus communication circuit 10 and the host 12 can receive the data sent to the data bus by the second-ranked single-bus communication circuit 10. The operation of other unidirectional receiving modes can be referred to here for explanation, and will not be listed in detail here.

[0045] When the bus communication mode is bidirectional receive and transmit, the bus device can receive data from the data link and also send data to the data link, and the data channel is in a bidirectional data flow state. For example, regarding... Figure 2In one example, host 12 can send data to single-bus communication circuit 10 which is ranked first, and single-bus communication circuit 10 which is ranked first can also send data to host 12 or single-bus communication circuit 10 which is ranked second.

[0046] also, Figure 2 An embodiment of host 12 is also shown in the figure. Figure 2 In this system, the host 12 may include a host processor 13 and a data / power switching circuit 14. The host 12 is connected to the single-bus communication circuit 10 (which is the first in sequence) via a terminal block 11 to supply power to the single-bus communication circuit 10 and to send data to or receive data from the data bus. The host processor 13 is the main functional unit of the host 12 and can process data. The data / power switching circuit 14 can switch between data and / or power supply. The host processor 13 and the data / power switching circuit 14 can adopt existing commonly used forms, depending on whether they meet the working requirements of the host 12, and will not be described in detail here.

[0047] In one embodiment of this utility model, an address allocation process is performed once in each round of bus communication to determine the communication address of each single-bus communication circuit 10, wherein... When performing address allocation processing, the following are included: All single-bus communication circuits 10 are configured to be in data interception mode simultaneously, and at least one single-bus communication circuit 10 is configured to send an address request command. For any two serially connected single-bus communication circuits 10, both in data interception mode, the first single-bus communication circuit 10 first receives an address allocation instruction, configures the corresponding bus device to obtain one communication address from the address allocation instruction, and forms a new address allocation instruction based on the remaining communication addresses. Then, the single-bus communication circuit 10 sends the instruction to the second single-bus communication circuit 10 via the data bus, so that the second single-bus communication circuit 10 obtains another communication address from the received address allocation instruction. The first single-bus communication circuit 10 is a single-bus communication circuit 10 adjacent to the host 12, and the second single-bus communication circuit 10 is a single-bus communication circuit far away from the host 12.

[0048] As described in the background section, in single-bus communication, a communication address should be configured for each single-bus communication circuit 10 to identify it, thereby improving the reliability of subsequent bus communication. In one embodiment of this invention, the communication address is not maintained after each round of bus communication. Therefore, an address allocation process should be performed in each round of bus communication. It should be noted that each round of bus communication specifically refers to starting a new bus communication, such as bus communication after the host 12 is connected to the corresponding serially connected single-bus communication circuit 10, or bus communication when a new single-bus communication circuit 10 is connected. The specific cases of each round of bus communication will not be illustrated here.

[0049] In practical implementation, when performing address allocation processing, each single-bus communication circuit 10 should be configured to be in data interception mode, and at least one single-bus communication circuit 10 should send an address request command to the host 12. It should be noted that "sending an address request command from a single-bus communication circuit 10 to the host 12" specifically refers to the bus device connected to the single-bus communication circuit 10 sending an address request command to the host 12 via the data bus. For example, if the bus device uses... Figure 1 and Figure 2 In the embodiment, the control processor 8 sends an address request instruction to the host 12.

[0050] Generally, at least one single-bus communication circuit 10 should be configured to actively send an address request command to the host 12. After receiving the address request command, the host 12 will send a mode configuration command to the data bus to configure all single-bus communication circuits 10 to be in data interception mode. Specifically, when multiple single-bus communication circuits 10 send address request commands to the host 12 simultaneously, the host 12 will ignore the other address request commands after receiving the first one sent. It should be noted that the address request command and mode configuration command can be selected as needed to enable interaction between the host 12 and the selected device. For example, the generation and parsing of address request commands and mode configuration commands can be implemented according to agreed-upon command rules. The details of the command rules will not be elaborated here.

[0051] It should be understood that the single-bus communication circuit 10 receiving the address allocation instruction specifically refers to the bus device connected to the single-bus communication circuit 10 receiving the address allocation instruction. After receiving the address allocation instruction, the bus device will extract one communication address from the address allocation instruction, and the remaining communication addresses will form a new address allocation instruction. The bus device will send the new address allocation instruction to the data link, and then send it to the next single-bus communication circuit 10 via the data bus, so that the single-bus communication circuit 10 that receives the new address allocation instruction will repeat the above-mentioned communication address acquisition and new address allocation instruction transmission.

[0052] In practice, each address allocation instruction includes several communication addresses. The number of communication addresses in the address allocation instruction is generally consistent with the number of serially connected single-bus communication circuits 10. When a communication address is extracted, the new address allocation instruction maintains the same encoding form as the initial address allocation instruction. The difference is that the number of communication addresses in the two instructions is different, so that the communication addresses can be extracted by subsequent bus devices.

[0053] Since there is a one-to-one correspondence between the bus devices and the single-bus communication circuit 10, the address allocation process is completed after the bus device obtains the corresponding communication address. Furthermore, after obtaining the communication address, the bus device can send address confirmation information of its own communication address to the host 12, so that the host 12 can subsequently identify the corresponding bus device. The address confirmation information sent by the bus device and the method by which the host 12 identifies the corresponding bus device based on the address confirmation information are consistent with existing technologies and will not be elaborated here.

[0054] In one embodiment of this utility model, for each single-bus communication circuit 10, the data link within the single-bus communication circuit 10 includes at least a bus data receiving circuit 1 and a bus data transmitting circuit 2 disposed on the data bus, wherein... The bus device is adapted and connected to the bus data receiving circuit 1 and the bus data transmitting circuit 2. For any two adjacent single-bus communication circuits 10, the bus data transmitting circuit 2 of the preceding single-bus communication circuit 10 is adapted and connected to the bus data receiving circuit 1 of the following single-bus communication circuit 10 through the data bus. When the bus communication mode is off-bus mode, the bus device is prohibited from receiving data through the bus data receiving circuit 1 and from sending data to the data bus through the bus data sending circuit 2. The bus data receiving circuit 1 and the bus data sending circuit 2 are both configured to be in the open state, so that the data channel formed by the bus data receiving circuit 1 and the bus data sending circuit 2 is in the bidirectional data flow state. When the bus communication mode is unidirectional transmission mode, the bus device is prohibited from receiving data through the bus data receiving circuit 1, and only the bus data transmitting circuit 2 is configured to be in the pass state, so that the bus device can send data to the next single bus communication circuit 10 through the bus data transmitting circuit 2. When the bus communication mode is a one-way receiving mode, the bus device receives data through the bus data receiving circuit 1, but the bus device is prohibited from sending data to the data bus through the bus data sending circuit 2. At the same time, both the bus data receiving circuit 1 and the bus data sending circuit 2 are configured to be in the open state, so that the data channel formed by the bus data receiving circuit 1 and the bus data sending circuit 2 is in the bidirectional data flow state. When the bus communication mode is bidirectional receive and send mode, the bus device receives data through the bus data receiving circuit 1 and can send data to the data bus through the bus data sending circuit 2. At the same time, both the bus data receiving circuit 1 and the bus data sending circuit 2 are configured to be in a closed state, so that the data channel formed by the bus data receiving circuit 1 and the bus data sending circuit 2 is in a bidirectional data flow state.

[0055] In addition, when the single-bus communication circuit is configured to be in data interception mode, both the bus data receiving circuit 1 and the bus data sending circuit 2 are configured to be in a non-circuit state, so that the bus device can receive the address allocation instruction from the bus data receiving circuit 1, and after obtaining a communication address in the address allocation instruction, send the new address allocation instruction to the next adjacent single-bus communication circuit 10 via the bus data sending circuit 2.

[0056] Figure 1 and Figure 2 The figure illustrates one embodiment of a data link. As shown in the figure, the data link may include a bus data receiving circuit 1 and a bus data transmitting circuit 2, and the bus data receiving circuit 1 is connected to the bus data transmitting circuit 2 through a data bus. Figure 1 and Figure 2 In the bus device embodiment shown, the control processor 8 within the bus device is connected to the bus data receiving circuit 1 and the bus data transmitting circuit 2. When the data link uses the bus data receiving circuit 1 and the bus data transmitting circuit 2, for any two adjacent single-bus communication circuits 10, the bus data transmitting circuit 2 of the preceding single-bus communication circuit 10 is adapted and connected to the bus data receiving circuit 1 of the following single-bus communication circuit 10 through the data bus; furthermore, when the single-bus communication circuit 10 is connected to the host 12, the bus data receiving circuit 1 is connected to the host 12 through the data bus-terminal block 11-data bus.

[0057] It should be noted that when the data link adopts Figure 1 as well as Figure 2In the embodiments shown, configuring the bus communication mode is mainly achieved by configuring the operation of the bus data receiving circuit 1 and the bus data transmitting circuit 2. Specifically, configuring the bus data receiving circuit 1 to be in a closed state means that data on the data bus can be transmitted through the bus data receiving circuit 1. Similarly, configuring the bus data transmitting circuit 2 to be in a closed state also means that data on the data bus can be transmitted through the bus data transmitting circuit 1. When the data channel is in a bidirectional data flow state, it specifically means that data on the data bus can be transmitted both along the direction from the bus data receiving circuit 1 to the bus data transmitting circuit 2 and along the direction from the bus data transmitting circuit 2 to the bus data receiving circuit 1. All cases where the data channel of this utility model is in a bidirectional data flow state have the same meaning, and can be referred to the description herein.

[0058] The prohibition of bus devices receiving data via bus data receiving circuit 1 specifically means that bus devices cannot obtain data from the data bus via bus data receiving circuit 1; the situation is the opposite of the prohibition when bus devices receive data via bus data receiving circuit 1. The prohibition of bus devices sending data to the bus data bus via bus data sending circuit 2 specifically means that data within the bus device cannot be sent to the data bus via bus data sending circuit 2; the situation is the opposite of the prohibition when bus devices send data to the bus data bus via bus data sending circuit 2.

[0059] As can be seen from the above description, when the bus communication mode is a one-way transmission mode, data cannot be transmitted from the bus data receiving circuit 1 to the bus data sending circuit 2, and the bus device cannot receive data on the data bus through the bus data receiving circuit 1. However, the bus device can send data to the data bus through the bus data sending circuit 2. At this time, the data can be transmitted to the next single bus communication circuit 10.

[0060] When the bus communication mode is a one-way receiving mode, the data on the data bus can be received by the bus data receiving circuit 1, and the bus device can also obtain the data through the bus data receiving circuit 1, but it cannot send the data to the data bus through the bus data sending circuit 1. In addition, the data that passes through the bus data receiving circuit 1 can be transmitted to the bus data sending circuit 2, and the data that passes through the bus data sending circuit 2 can also be transmitted to the bus data receiving circuit 1.

[0061] When the bus communication mode is bidirectional receive and transmit mode, the bus device receives data through the bus data receiving circuit 1 and can send data to the data bus through the bus data transmitting circuit 2. At the same time, both the bus data receiving circuit 1 and the bus data transmitting circuit 2 are configured to be in the pass state.

[0062] In one embodiment of this utility model, the bus data receiving circuit 1 includes a first data receiving unit and a second data receiving unit, and the bus data transmitting circuit 2 includes a first data transmitting unit, a second data transmitting unit, and a third data transmitting unit, wherein... The second data receiving unit is connected to the second data transmitting unit via a data bus; For any data link, the bus device is adapted to connect with the first data receiving unit, the first data transmitting unit, and the third data transmitting unit so that the bus device is attached to the data link. When the control link configuration data receiving first unit is in working state, the bus device can receive data from the data link through the data interpretation first unit; When the second unit for receiving control link configuration data is in working state, the bus data receiving circuit is in the open state. When the control link configuration data transmission first unit is in working state, the bus device sends data to the data bus in the data link through the data transmission first unit; When the second unit for transmitting control link configuration data is in working state, the bus data transmission circuit is in the open state. When the data bus within the data link is in a fault state, the third data transmission unit is in working state, and the bus device can send data to the data bus within the data link through the third data transmission unit.

[0063] Figure 3 The figure shows an embodiment of the bus data receiving circuit 1. In the figure, interface J1 is the data receiving power supply interface. As can be seen from the above description, interface J1 can be connected to the host 12 or another data transmission second unit of the single-bus communication circuit 10, and can provide power. Figure 3 In the middle, pin 3 of interface J1 is connected to SGND, and pin 4 of interface J1 is connected to power supply VCC_3.3V.

[0064] The first data receiving unit includes a tri-state gate U3A and a NOT gate U2E. The tri-state gate U3A can be a chip of model SN74HCS125DYYR, and the NOT gate U2E can be a chip of model 74LS32. The input terminal of the tri-state gate U3A is connected to pin 1 of interface J1, thereby enabling connection to the data bus. The output terminal of the tri-state gate U3A is connected to the control processor 8. The VCC terminal of the tri-state gate U3A is connected to the power supply VCC_3.3V and one end of capacitor C7. The other end of capacitor C7 is connected to the GND terminal and SGND terminal of the tri-state gate U3A. The enable terminal of the tri-state gate U3A is connected to the output terminal of the NOT gate U2E. The input terminal of the NOT gate U2E is connected to the receive enable signal, and the input terminal of the NOT gate U2E is also connected to SGND through resistor R10. Figure 3In this context, RX_EN is the receive enable signal.

[0065] When the output of NOT gate U2E is low, tri-state gate U3A is in the ON state. At this time, the first data receiving unit is in the working state, and the data at pin 1 of interface J1 can be received by the control processor 8 through tri-state gate U3A. When the output of NOT gate U2E is low, the receive enable signal should be high.

[0066] Figure 3 In the data receiving second unit, there are three components: a tri-state gate U1A, a resistor R1, and a resistor R4. Tri-state gate U1A and tri-state gate U3A can use the same chip model. The input terminal of tri-state gate U1A and one end of resistor R1 are connected to pin 1 of interface J1. The other end of resistor R1 is connected to the power supply VCC_3.3V. The VCC terminal of tri-state gate U1A is connected to one end of capacitor C4, one end of capacitor C6, and the cathode of diode chip D1. The other ends of capacitors C4 and C6 are connected to the tri-state gate U1A. The GND and SGND terminals of the 1A gate are connected. Diode chip D1 can be a BAT5AC chip. Diode chip D1 contains two diodes, with their cathodes interconnected to form the cathode terminal of diode chip D1. Additionally, the anode of one diode is connected to the power supply VCC_3.3V, and the anode of the other diode is connected to pin 1 of interface J1. In operation, the two diodes will not conduct simultaneously; the other diode will only conduct when the power supply VCC_3.3V fails. The enable terminal of the tri-state gate U1A is connected to receive the direction control signal and is connected to SGND through resistor R4. Figure 3 In this context, Left_En is the receiving direction control signal.

[0067] When the data bus is idle, it can be pulled high through resistor R1 and power supply VCC_3.3V. When the receive direction control signal is low, tri-state gate U1A is in the conducting state. At this time, data at pin 1 of interface J1 can be transmitted from the input to the output of tri-state gate U1A, which can then flow to the second data transmission unit. Diode chip D1 charges capacitors C4 and C6 to ensure that tri-state gate U1A is powered normally when the data link is powered down. In specific implementations, when tri-state gate U1A and tri-state gate U1B are composed of two tri-state gate circuits within the same chip, the power supply to tri-state gate U1B can be guaranteed to be normal.

[0068] Figure 4An embodiment of the bus data transmission circuit 2 is shown. In the figure, the bus data transmission circuit 2 may include an interface J2, which can be connected to an interface J1 in the adjacent single bus communication circuit 10. The first pin of the interface J2 is connected to the data bus, the third pin of the interface J2 is connected to SGND, and the fourth pin of the interface J2 is connected to the power supply VCC_3.3V.

[0069] Depend on Figure 4 It can be seen that the first data transmission unit may include a tri-state gate U1D and a NOT gate U2D. The tri-state gate U1D can use the same model chip as the tri-state gate U3A, and the NOT gate U2D can use the same model chip as the aforementioned U2E. The input terminal of the tri-state gate U1D is connected to the output terminal of the control processor 8, and the output terminal of the tri-state gate U1D is connected to the data bus and pin 1 of interface J2. The enable terminal of the tri-state gate U1D is connected to the output terminal of the NOT gate U2D, and the input terminal of the NOT gate U2D is connected to the transmit enable signal. Figure 4 In this circuit, TX_EN is the transmit enable signal. When the transmit enable signal TX_EN is high, the NOT gate U2D outputs a low level, thereby driving the tri-state gate U1D to conduct. When the tri-state gate U1D is conducting, the control processor 8 can send data to the data bus via the tri-state gate U1D, thus enabling the bus devices to send data to the data bus via the bus data transmission circuit 2. It can be understood that when the output of the NOT gate U2D is high, the tri-state gate U1D is off, and the bus devices cannot send data to the data bus via the bus data transmission circuit 2. It should be noted that when the tri-state gate U1D is in the conducting state, the first data transmission unit is in the working state.

[0070] The second data transmission unit may include a tri-state gate U1B, resistor R8, and resistor R2. The output of tri-state gate U1B is connected to the output of tri-state gate U1A via a data bus. The input of tri-state gate U1B is connected to pin 1 of interface J2 and one end of resistor R2. The other end of resistor R2 is connected to the power supply VCC_3.3V. The enable terminal of tri-state gate U1B is connected to SGND via resistor R8, and the enable terminal of tri-state gate U1B also receives the transmission direction control signal. Figure 4 In this context, Right_EN is the transmit direction enable signal.

[0071] When the data bus is idle, it can be pulled high via resistor R2. Since the enable pin of tri-state gate U1B is connected to SGND via resistor R8, when the transmit direction control signal is not high, tri-state gate U1B is in the on state, and the data output from tri-state gate U1A can be transmitted to pin 1 of interface J2 via tri-state gate U1B. When the transmit direction control signal is high, tri-state gate U1B is off, and the data output from tri-state gate U1A cannot be transmitted to pin 1 of interface J2. It should be noted that when tri-state gate U1B is in the on state, the second data transmission unit is in operation.

[0072] The third data transmission unit includes a tri-state gate U1C, wherein the input of tri-state gate U1C is connected to the input of the control processor, the output of tri-state gate U1C is connected to the output of tri-state gate U1B, and the enable terminal of tri-state gate U1C receives a bus fault status signal. Figure 4 In this context, Bus_Error is the bus fault status signal. When the data bus is in a fault state, the bus fault status signal is low, and the tri-state gate U1C is turned on, and the third data transmission unit is in operation. When the data bus is in a normal state, the bus fault signal is high, and the tri-state gate U1C is turned off.

[0073] In the above description, when troubleshooting the data bus fault and it is necessary to disconnect the adjacent single-bus communication circuit 10, only the tri-state gate U1C in the bus data transmission circuit 2 is in the conducting state. At this time, when the driving single-bus communication circuit 10 is also in data interception mode, the data of the bus device is sent to the data bus via the tri-state gate U1C. In specific implementation, the tri-state gate U1C can adopt the same form as the tri-state gate U3A. In the following description, unless otherwise specified, the tri-state gates and NOT gates all adopt the chip types mentioned above, and will not be described one by one here.

[0074] It should be noted that the receive direction control signal, transmit direction control signal, receive enable signal, and transmit enable signal are all generated by the data transceiver control circuit within the control link described below. For details on the generation method and process, please refer to the corresponding descriptions below.

[0075] In one embodiment of this utility model, the control link includes a data transceiver control circuit 4, a processor operation detection circuit 5, and a bus fault detection circuit 7, wherein... The bus fault detection circuit 7 is connected to the data bus in the data link, and is used to detect the fault status of the data bus, generate a bus fault status signal, and send the bus fault status signal to the bus device and the data link. The processor operation detection circuit 5 is connected to the bus device and the data transceiver control circuit 4. It is used to detect the operation status of the bus device, generate a bus device operation status signal, and send the generated bus device operation status signal to the data transceiver control circuit 4. The data transceiver control circuit 4 is connected to the bus device and the data link adapter. It receives the bus device operation signal from the bus device, the bus device operation status signal sent by the processor operation detection circuit 5, and the data transceiver control signal sent by the bus device to configure the bus communication mode of the data link.

[0076] Figure 1 and Figure 2 The diagram illustrates one embodiment of the control link. As shown, the control link should include at least a data transceiver control circuit 4, a processor operation detection circuit 5, and a bus fault detection circuit 7. The bus fault detection circuit 7 can detect faults in the data bus within the single-bus communication circuit 10 and generates a bus fault status signal. When the data bus is in a fault state, the bus fault status signal is low; otherwise, the bus data fault status signal is high.

[0077] Figure 9 The figure shows an embodiment of the bus fault detection circuit 7. As can be seen from the figure, the bus fault detection circuit may include NOT gate U8F and NOT gate U8E, wherein... The input terminal of NOT gate U8F is connected to the data bus. The output terminal of NOT gate U8F is connected to one end of resistor R15, one end of resistor R18, one end of capacitor C15, and one end of resistor R25. The other end of resistor R15 is connected to the cathode of diode D2. The other end of resistor R81 is connected to one end of resistor R22, one end of capacitor C16, the anode of diode D2, and the input terminal of NOT gate U8E. The other ends of capacitor C15 and resistor R25 are connected to the base terminal of PNP transistor Q1. The source terminal of PNP transistor Q1 is connected to the other end of resistor R22. The other end of capacitor C16 and the drain terminal of PNP transistor Q1 are both connected to SGND.

[0078] The output of NOT gate U8E serves as the output of bus fault detection circuit 7. When the data bus connected to NOT gate U8F is low, the signal is inverted by NOT gate U8F and charged by resistor R18 to capacitor C16. When the data bus remains low for at least 2.2 seconds (the aforementioned holding time is 2.2 seconds), and the voltage on capacitor C16 reaches the minimum voltage of 1.9V required for a high-level input of NOT gate U8E, NOT gate U8E outputs a low-level bus fault status signal. Figure 9In this context, Bus_Error is the bus fault status signal. When the data bus returns to a high level, the signal is inverted by NOT gate U8F, and then quickly discharged through resistor R15, diode D2, capacitor C15, resistor R22 / R25, and PNP transistor Q1. This causes the input of NOT gate U8E to be low, and the NOT gate U8E then outputs a high-level bus fault status signal.

[0079] The control processor 8 can be a commonly used microcontroller or other processor type. Figure 7 The figure shows an embodiment of the processor operation detection circuit 5. The processor operation detection circuit 5 may include a watchdog U4, wherein the watchdog U4 may be a CN825S chip. The VCC terminal of the watchdog U4 is connected to the power supply VCC_3.3V and one end of the capacitor C2, and the other end of the capacitor C2 is grounded. Watchdog U4 Connect the power supply VCC_3.3V through resistor R, and connect the GND terminal of watchdog U4 to SGND. Figure 7 In this context, DWI is the bus device operation signal, and MCU_Error is the bus device operation status signal output by the watchdog U4.

[0080] Generally, when the controller processor 8 is operating normally, the bus device operation signal is a square wave signal with a frequency range of 1Hz to 20MHz. This bus device operation signal should be applied to the WDI pin of the watchdog U4. If the watchdog U4 detects that the bus device operation signal has been held at a high or low level for more than 1.6 seconds, it will first pull the RESET pin high for 200ms, and then pull it low again for 1.6 seconds. When the frequency of the bus device operation signal is between 1Hz and 20MHz, the RESET pin of the watchdog U4 remains low; otherwise, the RESET pin goes high.

[0081] As can be seen from the above description, under normal operation of the control processor 8, the bus device operation status signal is at a low level; under abnormal operation of the control processor 8, the bus device operation status signal is at a high level.

[0082] Depend on Figure 1 and Figure 2It is understood that the control processor 8 and the processor operation detection circuit 5 are both connected to the data transceiver control circuit 4, and the data transceiver control circuit 4 is adapted to connect to the bus data receiving circuit 1 and the bus data transmitting circuit 2. Specifically, the data transceiver control circuit 4 receives the bus device operation signal from the bus device, the bus device operation status signal sent by the processor operation detection circuit 5, and the data transceiver control signal sent by the bus device, and generates a receive enable signal, a receive direction control signal, a transmit enable signal, and a transmit direction control signal to configure the bus communication mode of the data link. The method and process of configuring the bus communication mode of the data link can be referred to the above description.

[0083] In one embodiment of this utility model, based on the bus device operation signal, the bus device operation status signal, and the data transceiver control signal, the data transceiver control circuit 4 generates at least a receive enable signal, a receive direction control signal, a transmit enable signal, and a transmit direction control signal. When the receive enable signal is valid, the bus device can receive data from the data bus within the data link; When both the receiving direction control signal and the transmitting direction control signal are valid, the data channel is in a bidirectional data flow state. When the enable signal is active, the bus device can send data to the data bus of the data link.

[0084] Specifically, when configuring the bus communication mode using the generated receive enable signal, receive direction control signal, transmit enable signal, and transmit direction control signal, refer to the descriptions of the different bus communication modes mentioned above; they will not be repeated here. To generate the receive enable signal, receive direction control signal, transmit enable signal, and transmit direction control signal, the data transceiver control circuit 4 should include a transceiver enable generation unit, a receive direction control signal generation unit, and a transmit direction control signal generation unit. The transceiver enable generation unit generates the receive enable signal and the transmit enable signal, the receive direction control signal generation unit generates the receive direction control signal, and the transmit direction control signal generation unit generates the transmit direction control signal. Figure 6 The diagram shows a circuit schematic of one embodiment of the data transceiver control circuit 4. The following is a detailed explanation. Figure 6 An example is given for the data transmission and reception control generation circuit 4.

[0085] Figure 6In the middle, the transmit / receive enable generation unit includes a D flip-flop U9 and an NOT gate U8D. The input terminal of the NOT gate U8D is connected to one end of resistor R20, one end of capacitor C14, and one end of resistor R17. The other end of resistor R20 and the other end of capacitor C14 are both connected to SGND. The other end of resistor R17 is connected to the cathode of Schottky diode D3. The anode of Schottky diode D3 is connected to capacitor C13 and one end of resistor R19. The other end of resistor R19 is connected to SGND. The other end of capacitor C13 is connected to the bus device operation signal. The output of NOT gate U8D is connected to the D flip-flop U9. The enable pins of tri-state gate U6C and tri-state gate U3D are connected. The input pin of tri-state gate U6C is connected to SGND via resistor R21. The input pin of tri-state gate U6C is also connected to the data receive control signal within the data transmit / receive control signal. Figure 6 In this context, RX_EN0_IN is the data receive control signal; the input of the tri-state gate U3D is connected to SGND through resistor R23, and the input of the tri-state gate U3D is also connected to the data transmit control signal within the data transmit / receive control signal. Figure 6 In this context, TX_EN0_IN is the data transmission control signal.

[0086] The GND terminal of D flip-flop U9 is connected to SGND. The D terminal of D flip-flop U9 is connected to the power supply VCC_3.3V through resistor R14. The D terminal of D flip-flop U9 is connected to SGND through resistor R13. The CLK terminal of D flip-flop U9 is connected to the bus device running status signal. The VCC terminal of D flip-flop U9 is connected to the power supply VCC_3.3V and one end of capacitor C10. The other end of capacitor C10 is connected to SGND. The Q terminal of the D flip-flop U9 is connected to one end of resistor R12 and the input terminal of tri-state gate U6B. The enable terminal of tri-state gate U6B is connected to the output terminal of OR gate U11B. One input terminal of OR gate U11B is connected to the output terminal of tri-state gate U6C, one end of resistor R16 and the first input terminal of OR gate U5D. The other input terminal of OR gate U11B is connected to the output terminal of tri-state gate U3D, one end of resistor R26 and the first input terminal of OR gate U11A. The other ends of resistor R16 and resistor R26 are both connected to SGND. The output of tri-state gate U6B is connected to the second input of OR gate U5D, one end of resistor R24 ​​and the second input of OR gate U11A. The other end of resistor R24 ​​is connected to SGND. The VCC terminal of OR gate U11A is connected to power supply VCC_3.3V and one end of capacitor C17. The other end of capacitor C17 and GND terminal of OR gate U11A are both connected to SGND. The output of OR gate U5D outputs a receive enable signal, and the output of OR gate U11A outputs a send enable signal.

[0087] Specifically, the tri-state gates U3D, U6B, and U6C can use the SN74HCS125DYYR chip, and the D flip-flop U9 can use the SN74LVC1G74DCUR flip-flop.

[0088] Figure 9 In the process, the receiving direction control signal generation unit includes an XOR gate U7A and a NOT gate U8A. The first input terminal of the XOR gate U7A and the input terminal of the NOT gate U8A are connected to the input terminal of the tri-state gate U6C. The second input terminal of the XOR gate U7A is connected to the input terminal of the tri-state gate U3D. The output terminal of the XOR gate U7A is connected to the first input terminal of the OR gate U5C. The second input terminal of the OR gate U5C is connected to the output terminal of the NOT gate U8B. The input terminal of the NOT gate U8B is connected to the output terminal of the OR gate U5D. The output of OR gate U5C is connected to the first input of AND gate U10A, the second input of AND gate U10A is connected to the output of NOT gate U8A, the output of AND gate U10A is connected to the first input of AND gate U10B, and the second input of AND gate U10B is connected to the Q terminal of D flip-flop U9. The receiving direction control signal can be output through the output of AND gate U10B.

[0089] The VCC terminal of NOT gate U8A is connected to power supply VCC_3.3V and one end of capacitor C12. The other end of capacitor C12 and the GND terminal of NOT gate U8A are both connected to SGND. The VCC terminal of XOR NOT gate U7A is connected to power supply VCC_3.3V and one end of capacitor C8. The other end of capacitor C8 and the GND terminal of XOR NOT gate U7A are both connected to SGND. The VCC terminal of AND gate U10A is connected to power supply VCC_3.3V and one end of capacitor C9. The other end of capacitor C9 and the GND terminal of AND gate U10A are both connected to SGND.

[0090] In specific implementation, the XOR gate U7A can use a chip with the model number SN74HCS7266, the AND gate U10A and AND gate U10B can both use a chip with the model number 74LS08, and the NOT gate U8A and NOT gate U8B can both use a chip with the model number 74LS32.

[0091] Figure 9 In the middle, the transmission direction control signal generation unit includes AND gate U10C, AND gate U12A, and AND gate U12B, wherein, The first input of AND gate U10C is connected to the output of OR gate U5D, and the second input of AND gate U10C is connected to the output of OR gate U11A; the first input of AND gate U12A is connected to the output of XOR NOT gate U7A, the second input of AND gate U12A is connected to the output of NOT gate U13C, and the input of NAND gate U13C is connected to the input of tri-state gate U3D. One input of AND gate U12B is connected to the output of AND gate U10C, and the other input of AND gate U12B is connected to the output of AND gate U12A. The output of AND gate U12B outputs the transmission direction control signal.

[0092] Specifically, AND gates U10C, U12A, and U12B can use the same type of chip as the aforementioned AND gates. The VCC terminal of AND gate U12A is connected to the power supply VCC_3.3V and one end of capacitor C18. The other end of capacitor C18 and the GND terminal of AND gate U12A are both connected to SGND.

[0093] As can be seen from the above explanation, Figure 9 In this circuit, DWI is the bus device operation signal. This signal charges capacitor C14 via capacitor C13, resistor R19, Schottky diode D3, and resistor R17. When the voltage across capacitor C14 is greater than or equal to the minimum high-level voltage (1.9V) of the NOT gate U8D input, the NOT gate U8D outputs a low level. At this time, the D flip-flop U9... The terminal is low level, by Figure 10 The truth table diagram of D flip-flop U9 shows that, in the D flip-flop U9... The terminal is high level and When the terminal is low, regardless of whether the CLK terminal of D flip-flop U9 or the level group of the D port is high, the Q terminal of D flip-flop U9 is always high.

[0094] When the bus device operation signal level remains unchanged, the voltage across capacitor C14 is released by R20, the input of NOT gate U8D becomes low, and the output of NOT gate U8D becomes high. From the truth table of D flip-flop U9, we know that in the D flip-flop U9... The terminal is high level and When the CLK terminal of D flip-flop U9 is at a high level, and the D port of D flip-flop U9 is at a low level (the D port has been pulled down to a low level by resistor R13), then the Q terminal of D flip-flop U9 will be at a low level.

[0095] The following is combined Figure 9 The data transceiver circuit 4 shown in the figure illustrates the specific method of configuring the bus communication mode, specifically: Out of bus mode: DWI error (holding high or low level), NOT gate U8D outputs high level. When the bus device running status signal (MCU_Error signal) goes high (i.e., on the rising edge), the truth table will be used to determine the output. Figure 10It can be seen that in this state, the Q pin of the D flip-flop U9 outputs a low level, the tri-state gates U6C and U3D are both in the off state, while the tri-state gate U6B is in the on state and outputs a low level. At this time, the OR gate U5D outputs a low-level receive enable signal (RX_EN), and the OR gate U11A outputs a low-level transmit enable signal (TX_EN).

[0096] Since the Q pin of D flip-flop U9 outputs a low level, AND gate U10B outputs a low-level receive direction control signal, i.e., the Left_En signal is low. Furthermore, since both the receive enable signal (RX_EN) and the transmit enable signal (TX_EN) are low, AND gate U12B outputs a low-level transmit direction control signal (the Right_En signal is low).

[0097] Based on the above explanation, we can conclude that: tri-state gate U3A is closed, tri-state gate U11D is closed and bus transmission is disabled, and tri-state gates U1A and U1B are both in the on state.

[0098] Data capture mode: When DWI is normal (square wave signal), since the output of NOT gate U8D is low, when the OE terminal (enable terminal) of tri-state gates U6C and U3D is low, both tri-state gates U6C and U3D are in the on state. When the data receive control signal (RX_EN0_IN) at the input terminal of tri-state gate U6C and the data transmit control signal (TX_EN0_IN) at the input terminal of tri-state gate U3D are low, the corresponding output terminals of tri-state gates U6C and U3D are also low. At this time, the output of OR gate U11B is low, the OE terminal of tri-state gate U6B is low, and tri-state gate U6B is in the on state.

[0099] Since the Q output of D flip-flop U9 is high, the output of tri-state gate U6B is high, which in turn makes the corresponding inputs of OR gates U5D and U11A high, and the corresponding outputs of OR gates U5D and U11A high. Therefore, the receive enable signal (RX_EN) and the transmit enable signal (TX_EN) are both high. As explained above, when the receive enable signal is high, the output of NOT gate U2E is low, thus driving tri-state gate U3A to conduct. When the transmit enable signal is high, the output of NOT gate U2D is low, thus driving tri-state gate U1D to conduct.

[0100] Both inputs (RX_EN0_IN, TX_EN0_IN) of the XOR gate U7A are low, while the output of the XOR gate U7A is high. The receive enable signal is inverted by the NOT gate U8B and outputs a low level. The OR gate U5C outputs a high level, and the signal RX_EN0_IN is inverted by the NOT gate U8A and outputs a high level, which in turn causes the AND gate U10A to output a high level. Since the Q output of the D flip-flop U9 is high, the AND gate U10B outputs a high level (the receive direction control signal Left_En is high).

[0101] Since both the receive enable signal and the transmit enable signal are high, AND gate U10C outputs a high level. Since XOR gate U7A outputs a high level, the signal TX_EN0_IN is inverted by NOT gate U13C and outputs a high level. AND gate U12A outputs a high level, and thus AND gate U12B outputs a high level (the transmit direction control signal Right_En is high). Tri-state gates U1A and U1B are both turned off.

[0102] One-way transmission mode: When configuring one-way transmission mode, the data transmission control signal (TX_EN0_IN) should be high and the data reception control signal (RX_EN0_IN) should be low. As can be seen from the above description, the transmit enable signal (TX_EN) is high and the receive enable signal (RX_EN) is low. At this time, tri-state gate U1D is turned on and tri-state gate U3A is turned off. The receive direction control signal is high and the transmit direction control signal is low. Tri-state gate U1A is turned off and tri-state gate U1B is turned on.

[0103] One-way receive mode: When configuring one-way receive mode, the data transmission control signal (TX_EN0_IN) should be low and the data reception control signal (RX_EN0_IN) should be high. According to the above description, if the transmit enable signal (TX_EN) is low and the receive enable signal (RX_EN) is high, then: tri-state gate U1D is closed, tri-state gate U3A is turned on, the receive direction control signal is low, the transmit direction control signal is low, tri-state gate U1A is turned on, and tri-state gate U1B is turned on.

[0104] Bidirectional receive and transmit mode: When configuring bidirectional receive and transmit mode, the data transmit control signal should be high and the data receive control signal (RX_EN0_IN) should be high. According to the above description, the transmit enable signal (TX_EN) is high and the receive enable signal (RX_EN) is high, the tri-state gate U1D is turned on and the tri-state gate U3A is turned on. The receive direction control signal is low and the transmit direction control signal is low, the tri-state gate U1A is turned on and the tri-state gate U1B is turned on.

[0105] As explained above, when the bus device operation signal, which indicates a bus device malfunction, is abnormal, the system can directly enter the bus disconnect mode. That is, entering bus disconnect mode is primarily based on the abnormal bus device operation signal, without considering the corresponding signal states of the data transmission and reception control signals generated by the control processor 8. When configuring data interception mode, one-way transmission mode, one-way reception mode, and bidirectional transmission / reception mode, the corresponding signal states of the data transmission and reception control signals generated by the control processor 8 are required. It should be noted that the data transmission and reception control signals can be generated by the control processor 8 after interaction with the host 12. For example, the host 12 can specify the corresponding control processor 8 to generate the corresponding data transmission and reception control signals.

[0106] In one embodiment of this utility model, the control link further includes a fault alarm circuit 3 and a bus occupancy detection circuit 6, wherein... Bus occupancy detection circuit 6, bus fault detection circuit 7 and processor operation detection circuit 5 are all connected to fault alarm circuit 3. Fault alarm circuit 3 is adapted to connect to the data bus in the single bus communication circuit 10. When the bus device operation status signal generated by the processor operation detection circuit 5 indicates that the bus device is normal, the bus occupancy detection circuit 6 is driven to work based on the normal bus device operation status signal, and the bus occupancy detection circuit 6 generates a bus occupancy status signal, which includes bus occupancy status or bus unoccupancy status. When the bus occupancy status signal is "bus not occupied" and the bus device operation status signal is "bus device abnormal", the fault alarm circuit 3 outputs a bus device fault alarm signal and sends the bus device fault alarm signal to the connected data bus.

[0107] To further improve the security and reliability of bus communication, the control link may also include a fault alarm circuit 3 and a bus occupancy detection circuit 6. The bus occupancy detection circuit 6 can detect the occupancy status of the data bus. As explained above, when the data bus is at a low level, it can be considered that the data bus is occupied, and data can be considered to exist on the data bus. When the data bus is at a high level, it can be considered that the data bus is not occupied, and data can be considered to exist on the data bus. It should be understood that the data on the data bus can be the data types mentioned above or other data that can be controlled by the processor 8. The details of the data will not be elaborated here.

[0108] Figure 8The diagram illustrates one embodiment of the bus occupancy detection circuit 6. As shown in the diagram, the bus occupancy detection circuit 6 includes an OR gate U5B, wherein both inputs of the OR gate U5B are connected to the data bus, and the output of the OR gate U5B is connected to one end of the resistor R11 and the input of the tri-state gate U6A. The tri-state gate U6A serves as the output of the bus occupancy detection circuit 6, that is, the output of the tri-state gate U6A can output a bus occupancy status signal; the other end of the resistor R11 is connected to the power supply VCC_3.3V, which is a 3.3V voltage. The enable terminal of tri-state gate U6A is connected to the bus device operation status signal. The VCC terminal of tri-state gate U66A is connected to the power supply VCC_3.3V and one end of capacitor C11. The other end of capacitor C11 and the GND terminal of tri-state gate U6A are both connected to the SGND terminal.

[0109] When the bus device running status signal is low (bus device / control processor 8 is running), tri-state gate U6A is turned on, and the input of tri-state gate U6A is clamped to a high level by pull-up resistor R11. When the data bus level is pulled low, the output of OR gate U5B is low, pulling the input of tri-state gate U6A low, and tri-state gate U6A outputs a low level, thus obtaining a low-level bus occupancy status signal. When the bus is idle, tri-state gate U6A outputs a high level, thus obtaining a high-level bus occupancy status signal. Therefore, when the bus occupancy status signal is in a bus occupancy state, the bus occupancy status signal is low; when the bus is not in an occupancy state, the bus occupancy status signal is high. Figure 8 In this context, Bus_Buys represents the bus occupancy status signal. As explained above, when the bus device's operating status is high, it indicates a bus device malfunction, and at this time, the tri-state gate U6A will be turned off.

[0110] Figure 5 The figure shows an embodiment of the fault alarm circuit 3. As can be seen from the figure, the fault alarm circuit 3 may include a NOT gate U2F. The input terminal of the NOT gate U2F receives the bus fault status signal. The output terminal of the NOT gate U2F is connected to the first input terminal of the OR gate U5A. The second input terminal of the OR gate U5A is connected to the bus device operation status signal. The output terminal of the OR gate U5A is connected to the input terminal of the tri-state gate U3C. The output terminal of the tri-state gate U3C is connected to one end of the resistor R9 and the input terminal of the NOT gate U2C. The enable terminal of the tri-state gate U3C receives the bus occupancy status signal. The other end of the resistor R8 is connected to SGND. The output of NOT gate U2C is connected to one end of resistor R3 and the enable terminal of tri-state gate U3B. The other end of resistor R3 is connected to power supply VCC_3.3V. The input of tri-state gate U3B is connected to the output of NOT gate U2B. The input of NOT gate U2B is connected to SGND via resistor R7. The output of tri-state gate U3B is connected to one end of resistor R6 and the input of NOT gate U2A. The output of NOT gate U2 is connected to one end of capacitor C3, and the output of NOT gate U2 forms the output of fault alarm circuit 3. The other ends of capacitor C3 and resistor R6 are both connected to SGND. The VCC terminal of NOT gate U2A is connected to power supply VCC_3.3V and one end of capacitor C1. The other end of capacitor C1 and the GND terminal of NOT gate U2A are both connected to SGND.

[0111] for Figure 5 As shown in the fault alarm circuit 3, capacitor C3, resistor R6, resistor R7, NOT gate U2A, and NOT gate U2B form a multivibrator, which can be used to generate a bus device fault alarm signal. Tri-state gate U3B acts as the switch for the multivibrator. OR gate U5A and NOT gate U2F serve as the selection circuit.

[0112] As explained above, when the bus device operation status signal indicates a bus device malfunction, the signal is high, and OR gate U5A outputs a high level. Conversely, when the bus fault status signal indicates a fault exists, the signal is low, and NOT gate U2F outputs a high level. Utilizing the characteristics of OR gate U5A, it is known that OR gate U5A will always output a high level. When the bus occupancy status signal (Bus_Buys) is low, tri-state gate U3C is open, which, via NOT gate U2C, drives tri-state gate U3B to conduct, causing the multivibrator to oscillate and generate a fault alarm signal. When the data bus is occupied, the bus occupancy status signal is high, and tri-state gate U3C is closed to disable the multivibrator and prevent interference with data on the data bus.

Claims

1. A single-bus communication circuit, characterized in that, The single-bus communication circuit includes: A data link is a data channel formed based on a single-wire data bus, and the required bus communication is performed using the formed data channel. A control link, adapted and connected to the data link, is used to configure the bus communication mode of the data link, wherein... When the control link detects that the data bus of the connected data link is in a fault state, and the fault state of the data bus is caused by the bus device connected to the data link, the control link configures the bus communication mode to bus disconnect mode; so that the bus device is disconnected from the data bus, and the data can be transmitted as required through the data channel of the data link.

2. The single-bus communication circuit according to claim 1, characterized in that: When multiple single-bus communication circuits exist, all single-bus communication circuits are connected in series via a data bus. For each single-bus communication circuit, the data link within the single-bus communication circuit includes at least a bus data receiving circuit and a bus data transmitting circuit disposed on the data bus, wherein... The bus device is adapted to connect with the bus data receiving circuit and the bus data transmitting circuit. For any two adjacent single-bus communication circuits, the bus data transmitting circuit of the preceding single-bus communication circuit is adapted and connected to the bus data receiving circuit of the following single-bus communication circuit through the data bus.

3. The single-bus communication circuit according to claim 2, characterized in that: The bus data receiving circuit includes a first data receiving unit and a second data receiving unit, and the bus data transmitting circuit includes a first data transmitting unit, a second data transmitting unit, and a third data transmitting unit, wherein... The second data receiving unit is connected to the second data transmitting unit via a data bus; For any data link, the bus device is adapted to connect with the first data receiving unit, the first data transmitting unit, and the third data transmitting unit so that the bus device is attached to the data link.

4. The single-bus communication circuit according to claim 3, characterized in that: The first data receiving unit includes a tri-state gate U3A and a NOT gate U2E, wherein, The tri-state gate U3A can use a chip of model SN74HCS125DYYR. The input terminal of the tri-state gate U3A is connected to pin 1 of interface J1 to achieve connection with the data bus. The output terminal of the tri-state gate U3A is connected to the bus device. The VCC terminal of the tri-state gate U3A is connected to the power supply VCC_3.3V and one end of capacitor C7. The other end of capacitor C7 is connected to the GND terminal and SGND of the tri-state gate U3A. The enable terminal of the tri-state gate U3A is connected to the output terminal of the NOT gate U2E. The input terminal of the NOT gate U2E is connected to the receive enable signal. The input terminal of the NOT gate U2E is also connected to SGND through resistor R10.

5. The single-bus communication circuit according to claim 4, characterized in that: The second data receiving unit includes a tri-state gate U1A, resistor R1, and resistor R4, wherein... Tri-state gates U1A and U3A can use the same model chip. The input terminal of tri-state gate U1A and one end of resistor R1 are connected to pin 1 of interface J1. The other end of resistor R1 is connected to the power supply VCC_3.3V. The VCC terminal of tri-state gate U1A is connected to one end of capacitor C4, one end of capacitor C6, and the cathode of diode chip D1. The other ends of capacitors C4 and C6 are connected to the GND and SGND terminals of tri-state gate U1A, respectively. Diode chip D1 can be a BAT5AC chip, which contains two diodes. The cathodes of the two diodes are connected to each other to form the cathode of diode chip D1. In addition, the anode of one diode is connected to the power supply VCC_3.3V, and the anode of the other diode is connected to pin 1 of interface J1.

6. The single-bus communication circuit according to claim 3, characterized in that: The first data transmission unit may include a tri-state gate U1D and a NOT gate U2D, wherein, The input of the tri-state gate U1D is connected to the control link adapter, and the output of the tri-state gate U1D is connected to the data bus and pin 1 of interface J2. The enable terminal of the tri-state gate U1D is connected to the output terminal of the NOT gate U2D, and the input terminal of the NOT gate U2D is connected to the transmit enable signal. When the transmit enable signal TX_EN is high, the NOT gate U2D outputs a low level, thereby driving the tri-state gate U1D to conduct. When the tri-state gate U1D is conducting, the bus device can send data to the data bus through the tri-state gate U1D. When the output of the NOT gate U2D is high, the tri-state gate U1D is turned off. The second data transmission unit may include a tri-state gate U1B, a resistor R8, and a resistor R2. The output of tri-state gate U1Bd is connected to the output of tri-state gate U1A via a data bus. The input of tri-state gate U1B is connected to pin 1 of interface J2 and one end of resistor R2. The other end of resistor R2 is connected to power supply VCC_3.3V. The enable terminal of tri-state gate U1B is connected to SGND via resistor R8. The enable terminal of tri-state gate U1B also receives the transmission direction control signal. When the data bus is idle, it is pulled high through resistor R2. Since the enable terminal of tri-state gate U1B is connected to SGND through resistor R8, when the transmit direction control signal is not high, tri-state gate U1B is in the conducting state, and the data output by tri-state gate U1A can be transmitted to pin 1 of interface J2 through tri-state gate U1B. When the transmit direction control signal is high, tri-state gate U1B is turned off, and the data output by tri-state gate U1A cannot be transmitted to pin 1 of interface J2. The third data transmission unit includes a tri-state gate U1C, wherein the input of tri-state gate U1C is connected to the input of the control processor, the output of tri-state gate U1C is connected to the output of tri-state gate U1B, and the enable terminal of tri-state gate U1C receives a bus fault status signal. When the data bus is in a fault state, the bus fault state signal is low, and the tri-state gate U1C is turned on; when the data bus is in a normal state, the bus fault signal is high, and the tri-state gate U1C is turned off.

7. The single-bus communication circuit according to any one of claims 1 to 6, characterized in that, The control link includes a data transceiver control circuit, a processor operation detection circuit, and a bus fault detection circuit, wherein... The bus fault detection circuit is connected to the data bus within the data link and is used to detect the fault status of the data bus. The processor operation detection circuit is connected to the bus device and the data transceiver control circuit to detect the operating status of the bus device; The data transceiver control circuit is connected to the bus device and data link adapter to configure the bus communication mode of the data link.

8. The single-bus communication circuit according to claim 7, characterized in that, The bus fault detection circuit includes NOT gate U8F and NOT gate U8E, wherein, The input terminal of NOT gate U8F is connected to the data bus. The output terminal of NOT gate U8F is connected to one end of resistor R15, one end of resistor R18, one end of capacitor C15, and one end of resistor R25. The other end of resistor R15 is connected to the cathode of diode D2. The other end of resistor R81 is connected to one end of resistor R22, one end of capacitor C16, the anode of diode D2, and the input terminal of NOT gate U8E. The other ends of capacitor C15 and resistor R25 are connected to the base terminal of PNP transistor Q1. The source terminal of PNP transistor Q1 is connected to the other end of resistor R22. The other end of capacitor C16 and the drain terminal of PNP transistor Q1 are both connected to SGND. The output of NOT gate U8E serves as the output of bus fault detection circuit 7. When the data bus connected to NOT gate U8F is low, the data bus is inverted by NOT gate U8F and charged by resistor R18. When the data bus remains low for a period of time or longer, and the voltage on capacitor C16 reaches the minimum voltage of 1.9V required for the high level input of NOT gate U8E, NOT gate U8E outputs a low-level bus fault status signal. When the data bus returns to a high level, it is inverted by NOT gate U8F, and then the charge in capacitor C16 is quickly released through resistor R15, diode D2, capacitor C15, resistor R22 / R25, and PNP transistor Q1. The input of NOT gate U8E is low, and NOT gate U8E outputs a high-level bus fault status signal.

9. The single-bus communication circuit according to claim 7, characterized in that, The data transceiver control circuit includes a transceiver enable generation unit, a receive direction control signal generation unit, and a transmit direction control signal generation unit, wherein... The transmit / receive enable generation unit can generate receive enable signals and transmit enable signals, the receive direction control signal generation unit can generate receive direction control signals, and the transmit direction control signal generation unit can generate transmit direction control signals. The transmit / receive enable generation unit includes a D flip-flop U9 and an NOT gate U8D. The input terminal of the NOT gate U8D is connected to one end of resistor R20, one end of capacitor C14, and one end of resistor R17. The other ends of resistor R20 and capacitor C14 are both connected to SGND. The other end of resistor R17 is connected to the cathode of Schottky diode D3. The anode of Schottky diode D3 is connected to capacitor C13 and one end of resistor R19. The other end of resistor R19 is connected to SGND. The other end of capacitor C13 is connected to the bus device operation signal. The output of NOT gate U8D is connected to the D flip-flop U9. The enable pins of tri-state gates U6C and U3D are connected. The input pin of tri-state gate U6C is connected to SGND via resistor R21, and the input pin of tri-state gate U6C is also connected to the data receive control signal in the data transmit / receive control signal. The input pin of tri-state gate U3D is connected to SGND via resistor R23, and the input pin of tri-state gate U3D is also connected to the data transmit control signal in the data transmit / receive control signal. The GND terminal of D flip-flop U9 is connected to SGND. The D terminal of D flip-flop U9 is connected to the power supply VCC_3.3V through resistor R14. The D terminal of D flip-flop U9 is connected to SGND through resistor R13. The CLK terminal of D flip-flop U9 is connected to the bus device running status signal. The VCC terminal of D flip-flop U9 is connected to the power supply VCC_3.3V and one end of capacitor C10. The other end of capacitor C10 is connected to SGND. The Q terminal of the D flip-flop U9 is connected to one end of resistor R12 and the input terminal of tri-state gate U6B. The enable terminal of tri-state gate U6B is connected to the output terminal of OR gate U11B. One input terminal of OR gate U11B is connected to the output terminal of tri-state gate U6C, one end of resistor R16 and the first input terminal of OR gate U5D. The other input terminal of OR gate U11B is connected to the output terminal of tri-state gate U3D, one end of resistor R26 and the first input terminal of OR gate U11A. The other ends of resistor R16 and resistor R26 are both connected to SGND. The output of tri-state gate U6B is connected to the second input of OR gate U5D, one end of resistor R24 ​​and the second input of OR gate U11A. The other end of resistor R24 ​​is connected to SGND. The VCC terminal of OR gate U11A is connected to power supply VCC_3.3V and one end of capacitor C17. The other end of capacitor C17 and GND terminal of OR gate U11A are both connected to SGND. The output of OR gate U5D outputs a receive enable signal, and the output of OR gate U11A outputs a send enable signal.

10. The single-bus communication circuit according to claim 7, characterized in that, The receiving direction control signal generation unit includes an XOR gate U7A and a NOT gate U8A. The first input terminal of the XOR gate U7A and the input terminal of the NOT gate U8A are connected to the input terminal of the tri-state gate U6C. The second input terminal of the XOR gate U7A is connected to the input terminal of the tri-state gate U3D. The output terminal of the XOR gate U7A is connected to the first input terminal of the OR gate U5C. The second input terminal of the OR gate U5C is connected to the output terminal of the NOT gate U8B. The input terminal of the NOT gate U8B is connected to the output terminal of the OR gate U5D. The output of OR gate U5C is connected to the first input of AND gate U10A, the second input of AND gate U10A is connected to the output of NOT gate U8A, the output of AND gate U10A is connected to the first input of AND gate U10B, and the second input of AND gate U10B is connected to the Q terminal of D flip-flop U9. The receiving direction control signal can be output through the output of AND gate U10B. The VCC terminal of NOT gate U8A is connected to power supply VCC_3.3V and one end of capacitor C12. The other end of capacitor C12 and the GND terminal of NOT gate U8A are both connected to SGND. The VCC terminal of XOR NOT gate U7A is connected to power supply VCC_3.3V and one end of capacitor C8. The other end of capacitor C8 and the GND terminal of XOR NOT gate U7A are both connected to SGND. The VCC terminal of AND gate U10A is connected to power supply VCC_3.3V and one end of capacitor C9. The other end of capacitor C9 and the GND terminal of AND gate U10A are both connected to SGND. The transmission direction control signal generation unit includes AND gate U10C, AND gate U12A, and AND gate U12B, wherein, The first input of AND gate U10C is connected to the output of OR gate U5D, and the second input of AND gate U10C is connected to the output of OR gate U11A; the first input of AND gate U12A is connected to the output of XOR NOT gate U7A, the second input of AND gate U12A is connected to the output of NOT gate U13C, and the input of NAND gate U13C is connected to the input of tri-state gate U3D. One input of AND gate U12B is connected to the output of AND gate U10C, and the other input of AND gate U12B is connected to the output of AND gate U12A. The output of AND gate U12B outputs the transmission direction control signal.

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