An i2c slave, master and interrupt detection system

Abstract

The utility model discloses a kind of I2C slave device, master device and interrupt detection system, belong to I2C communication technical field, comprising: bus state detection module, for input SDA line and SCL line level, judge whether I2C bus is in idle state;Programmable pulse width generator is connected with the enable end of the bus state detection module, for generating the low level pulse of predetermined width;Open-drain drive circuit, for outputting low level pulse as interrupt signal through SDA line when bus is idle.The utility model realizes that slave device can actively trigger interrupt without additional pin, saves special INT pin, reduces package size, compatible standard I2C protocol.

Description

Technical Field

[0001] This utility model relates to the field of I2C communication technology, and in particular to an I2C slave device, master device and interrupt detection system. Background Technology

[0002] In the traditional I2C protocol, slave devices rely on polling by the master device to transmit data, resulting in poor real-time performance. Existing technologies sometimes implement slave-initiated interrupt requests by adding a dedicated interrupt (INT) pin, but this additional pin increases the packaging cost and PCB area of ​​small devices. Therefore, there is an urgent need for a slave interrupt solution that requires no additional pins and is compatible with the standard I2C protocol. Utility Model Content

[0003] The purpose of this invention is to provide an I2C slave device, master device, and interrupt detection system. By sending a low-level pulse with a configurable width during the bus idle phase, the master device identifies the pulse and starts communication through a Schmitt trigger and a pulse width counter. This eliminates the need for a dedicated interrupt pin, is compatible with the standard I2C protocol, and is especially suitable for miniaturized devices such as sensors.

[0004] To solve the above-mentioned technical problems, this utility model provides an I2C slave device, comprising: The bus status detection module determines whether the I2C bus is in an idle state by receiving the SDA and SCL line levels. A programmable pulse width generator is connected to the enable terminal of the bus status detection module to generate a low-level pulse of a predetermined width. An open-drain drive circuit outputs a low-level pulse as an interrupt signal via the SDA line when the bus is idle. The open-drain drive circuit includes: an NMOS transistor N1, a current-limiting resistor R1, and a pull-up resistor R... P The gate of the NMOS transistor N1 is connected to one end of a current-limiting resistor R1, and the other end of the current-limiting resistor R1 serves as the input terminal INPUT. The source of the NMOS transistor N1 is grounded to GND, and the drain of the NMOS transistor N1 is connected to a pull-up resistor R. P One end of the pull-up resistor RP is connected to the output terminal OUTPUT, and the other end of the pull-up resistor RP is connected to the power supply VCC.

[0005] In one implementation, the I2C slave device uses the GPIO port of an STM32F042 MCU to simulate an I2C bus and configures the open-drain driver circuit as an open-drain output.

[0006] In one embodiment, the I2C slave device further includes a configuration register through which the programmable pulse width generator sets the pulse width.

[0007] In one embodiment, the NMOS transistor N1 is an N-channel MOSFET.

[0008] This utility model also provides an I2C master device, including: An RC filter circuit is used to filter the input pulse signal. A Schmitt trigger, connected to the output of the RC filter circuit, converts the filtered signal into a steep-edge signal. A level conversion circuit, connected to the output of the Schmitt trigger, is responsible for signal level adaptation. A pulse width counter, connected to the output of the level conversion circuit, is used to measure the shaped pulse width and trigger an interrupt.

[0009] In one embodiment, the Schmitt trigger is a 74HC14 chip.

[0010] In one embodiment, the level conversion circuit is a TXB0104 chip.

[0011] This utility model also provides an I2C master-slave device interruption detection system, including: an I2C slave device and an I2C master device, wherein the I2C master device and the I2C slave device are connected by an SDA line and an SCL line.

[0012] This utility model provides an I2C slave device, master device, and interrupt detection system. During the I2C bus idle phase (when both SDA and SCL are high), the I2C slave device sends a low-level pulse with a configurable width as an interrupt signal via the SDA line. The I2C master device has a built-in pulse detection circuit that identifies the pulse and initiates the standard I2C communication process. This allows the slave device to actively trigger an interrupt without additional pins, saving a dedicated INT pin, reducing package size (suitable for small packages such as SOT23), and ensuring compatibility with the standard I2C protocol. Attached Figure Description

[0013] Fig. 1 This is a structural block diagram of an I2C master-slave device interruption detection system according to this utility model.

[0014] Fig. 2 This is a schematic diagram of the open-drain drive circuit in this utility model.

[0015] Fig. 3 This is a waveform diagram of the I2C bus in this utility model. Detailed Implementation

[0016] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the I2C slave device, master device, and interrupt detection system proposed in this utility model. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0017] like Figs. 1-3 As shown, this utility model embodiment specifically provides an I2C slave device, including: The bus status detection module is used to input the SDA (Serial Clock Line) and SCL (Synchronous Data Transfer) line levels to determine whether the I2C bus is in an idle state. A programmable pulse width generator, connected to the enable terminal of the bus status detection module, is used to generate low-level pulses of a predetermined width. An open-drain drive circuit is used to output a low-level pulse as an interrupt signal via the SDA line when the bus is idle.

[0018] The I2C slave device uses the GPIO port of an STM32F042 MCU to simulate an I2C bus and configures the open-drain driver circuit as an open-drain output; the I2C slave device also includes a configuration register, through which the programmable pulse width generator sets the pulse width.

[0019] The open-drain drive circuit includes: an NMOS transistor N1, a current-limiting resistor R1, and a pull-up resistor R. P The gate of the NMOS transistor N1 is connected to one end of a current-limiting resistor R1, and the other end of the current-limiting resistor R1 serves as the input terminal INPUT. The source of the NMOS transistor N1 is grounded to GND, and the drain of the NMOS transistor N1 is connected to a pull-up resistor R. P One end of the pull-up resistor R is used as the output terminal OUTPUT. P The other end is connected to the power supply VCC.

[0020] The NMOS transistor N1 is an N-channel MOSFET.

[0021] The open-drain drive circuit also includes the following working principle: (1) Input high level (conduct) When the input signal is high, the MOSFET is turned on, the drain (D) and source (S) are short-circuited, and the output is pulled low to GND level.

[0022] Output level: Low level (≈0V).

[0023] (2) Input low level (off) When the input signal is low, the MOSFET is turned off, the drain (D) is connected to VCC through the pull-up resistor Rp, and the output is pulled high.

[0024] Output level: High level (≈VCC voltage).

[0025] This utility model embodiment also provides an I2C master device, including: An RC filter circuit is used to filter the input pulse signal. A Schmitt trigger, connected to the output of the RC filter circuit, converts the filtered signal into a steep-edge signal. A level conversion circuit, connected to the output of the Schmitt trigger, is responsible for signal level adaptation. A pulse width counter, connected to the output of the level conversion circuit, is used to measure the shaped pulse width and trigger an interrupt.

[0026] Input signal shaping: After the noisy signal passes through the RC filter circuit and Schmitt trigger, a clean square wave signal is output. The hysteresis threshold ensures that the signal does not jump multiple times under noise interference.

[0027] Pulse width measurement steps: Step 1: Detect the rising edge of the square wave and start the counter.

[0028] Step 2: Detect the falling edge of the square wave, stop the counter and read the count value.

[0029] Step 3: Calculate the actual pulse width time based on the count value and clock frequency.

[0030] This utility model embodiment also provides an I2C master-slave device interrupt detection system, including: an I2C slave device and an I2C master device, which are connected via SDA and SCL lines. The slave device uses the GPIO of an STM32F042 (MCU model) to simulate I2C, configured as an open-drain output. After detecting bus idle (continuous 1ms high level), it pulls the SDA line low for 150μs. The master device initiates I2C communication after detecting a 100-200μs pulse.

[0031] It also includes the following circuit module selection and principles: Module 1: RC Filtering and Signal Shaping Function: Suppress high-frequency noise (such as switching power supply noise and EMI interference).

[0032] Typical parameters: R=10kΩ, C=100pF (cutoff frequency≈ 160kHz).

[0033] If the input pulse frequency is low (e.g., below 1kHz), the C value can be increased (e.g., 1nF) to enhance the filtering effect.

[0034] Module 2: Schmitt Trigger (74HC14) Function: Converts the filtered pulse into a steep edge signal to prevent signal jitter from causing false triggering.

[0035] Typical threshold voltage (5V supply): Positive threshold (Vt+): ≈3.3V, negative threshold (Vt-): ≈1.7V, hysteresis voltage: ≈1.6V.

[0036] Module 3: Level Conversion Application scenario: When the voltage of the MCU and the pulse source are inconsistent (e.g., the pulse source is 5V, and the MCU is 3.3V).

[0037] Recommended chip: TXB0104 (bidirectional automatic level conversion, supports 1.2V~5.5V).

[0038] Module 4: MCU Connection Configuration requirements: Interrupt mode: rising edge / falling edge triggered (selected according to pulse polarity).

[0039] If using low-speed pulses (e.g., <10kHz), the internal pull-up resistor (e.g., 10kΩ) can be enabled.

[0040] The core process of pulse detection circuit triggering I2C communication: 1. Pulse detection and interrupt triggering 1.1 Pulse Shaping: The input pulse is shaped by a Schmitt trigger (such as 74HC14) to eliminate noise interference and output a stable edge signal.

[0041] 1.2 Interrupt Trigger: The shaped pulse is connected to the external interrupt pin of the MCU (such as falling edge / rising edge trigger) to trigger the interrupt service routine to start I2C communication.

[0042] 2. I2C communication startup 2.1 Start Signal (START) As the master device, the MCU pulls the SDA line low during the SCL high level to generate the START signal, indicating that the bus has entered the communication state.

[0043] 2.2 Address Frame Transmission Send a 7-bit slave address (e.g., EEPROM address 0xA0) and a 1-bit read / write flag (0 indicates a write operation).

[0044] Data is switched when SCL is low and remains stable when SCL is high, ensuring that the receiver samples correctly.

[0045] 2.3 Acknowledgment Detection (ACK) The slave device pulls SDA low in the 9th clock cycle to return ACK. If there is no response (NACK), the master device needs to terminate or retry the communication.

[0046] 3. Data transmission process 3.1 Write operation: The master device sends the target register address (such as the EEPROM storage address), followed by the data bytes to be written.

[0047] After each byte is transmitted, wait for an ACK response from the slave device.

[0048] 3.2 Read operation: After the master device sends the register address, it switches to read mode by repeating the START signal, receives data, and returns ACK / NACK.

[0049] 4. Communication terminated 4.1 Stop signal (STOP): During the SCL high level, the master device pulls the SDA line high to generate a STOP signal and releases bus control.

[0050] The bus returns to an idle state (both SDA and SCL are high).

[0051] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An I2C slave device, characterized in that, include: The bus status detection module determines whether the I2C bus is in an idle state by receiving the SDA and SCL line levels. A programmable pulse width generator is connected to the enable terminal of the bus status detection module to generate a low-level pulse of a predetermined width. The open-drain drive circuit outputs a low-level pulse as an interrupt signal through the SDA line when the bus is idle; The open-drain drive circuit includes: an NMOS transistor N1, a current-limiting resistor R1, and a pull-up resistor R. P The gate of the NMOS transistor N1 is connected to one end of a current-limiting resistor R1, and the other end of the current-limiting resistor R1 serves as the input terminal INPUT. The source of the NMOS transistor N1 is grounded to GND, and the drain of the NMOS transistor N1 is connected to a pull-up resistor R. P One end of the pull-up resistor RP is connected to the output terminal OUTPUT, and the other end of the pull-up resistor RP is connected to the power supply VCC.

2. The I2C slave device as described in claim 1, characterized in that, The I2C slave device uses the GPIO port of an STM32F042 MCU to simulate an I2C bus and configures the open-drain driver circuit as an open-drain output.

3. An I2C slave device as described in claim 1, characterized in that, The I2C slave device also includes a configuration register, through which the programmable pulse width generator sets the pulse width.

4. An I2C slave device as described in claim 1, characterized in that, The NMOS transistor N1 is an N-channel MOSFET.

5. An I2C master device, characterized in that, include: An RC filter circuit is used to filter the input pulse signal. A Schmitt trigger, connected to the output of the RC filter circuit, converts the filtered signal into a steep-edge signal. A level conversion circuit, connected to the output of the Schmitt trigger, is responsible for signal level adaptation. A pulse width counter, connected to the output of the level conversion circuit, is used to measure the shaped pulse width and trigger an interrupt.

6. An I2C master device as described in claim 5, characterized in that, The Schmitt trigger is a 74HC14 chip.

7. An I2C master device as described in claim 5, characterized in that, The level conversion circuit is a TXB0104 chip.

8. An I2C master-slave device interruption detection system, characterized in that, include: An I2C slave device as described in any one of claims 1 to 4 and an I2C master device as described in any one of claims 5 to 7, wherein the I2C master device and the I2C slave device are connected via an SDA line and an SCL line.

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