An AI chip, a computing system and an electronic device
Patent Information
- Application Number
- CN202522120817.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2026-09-25
- Estimated Expiration
- 2035-09-30
AI Technical Summary
然而，这些解决方案是为追求极致性能和高通道数的服务器市场设计的，其高昂的成本、巨大的功耗和较大的物理尺寸，使其完全不适用于消费电子领域
[0007]本申请提供的AI芯片，通过在内部集成AI推理引擎、上游外设部件互连高速端口及下游外设部件互连高速端口，其中，上游外设部件互连高速端口及下游外设部件互连高速端口也可集成为一数据互连单元，使得主处理器仅配置有一个外设部件互连高速接口的情况下，既能实现AI推理引擎和其他外接设备均可以享受外设部件互连高速端口带来的高带宽和低延迟，同时并未以大幅增加电子产品的成本或牺牲其尺寸为代价，解决了现有技术中主处理器外设部件互连高速端口数量受限，进而制约主处理器及相应电子产品性能的问题，进而提高了芯片及电子设备的性能。
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Figure CN224803458U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of artificial intelligence technology, specifically to an AI chip, computing system, and electronic device. Background Technology
[0002] In recent years, with the rapid development of artificial intelligence technology, AI inference capabilities have become a core component of modern computing devices such as smartphones, laptops, and personal computers. To meet the ever-increasing computing power demands of AI models, dedicated AI inference chips or accelerators are widely adopted. These AI accelerators typically need to connect to the main processor (e.g., a central processing unit, CPU, or system-on-a-chip) via a high-speed interface to ensure low latency and high bandwidth for data transmission. Among these, the PCIe (Peripheral Component Interconnect) interface has become the preferred choice due to its superior performance.
[0003] At the same time, modern wireless communication technologies, especially new standards such as Wi-Fi 6 / 7, are increasingly using PCIe interfaces to connect to the main processor in order to achieve gigabit-level transmission rates.
[0004] However, in consumer electronics where cost, power consumption, and physical size are extremely sensitive, the main processor SoC typically provides only one or a very limited number of PCIe ports for design and economic reasons. This creates a serious technical bottleneck: system designers face a dilemma—they can only choose between a PCIe-based AI accelerator and a PCIe-based Wi-Fi module, while the other device has to degrade to a lower-performance interface (such as USB, MIPI, or SDIO), severely limiting the overall performance of the device.
[0005] In existing technologies, data centers and high-performance computing (HPC) use discrete, large PCIe switch chips to expand the number of PCIe ports. However, these solutions are designed for the server market, which demands extreme performance and high lane counts. Their high cost, enormous power consumption, and large physical size make them completely unsuitable for the consumer electronics sector. Directly applying such discrete switch chips to mobile phones or laptops would significantly increase bill of materials (BOM) costs, power budgets, and printed circuit board (PCB) area, which is impractical. Therefore, there is an urgent need in the field for a low-cost, low-power, and highly integrated innovative solution to address the technical challenge of the scarcity of PCIe ports on consumer-grade main processors. Utility Model Content
[0006] To address the above issues, this application provides an AI chip, comprising: an upstream peripheral component interconnect high-speed port configured to connect to a main processor; an AI inference engine communicatively connected to the upstream peripheral component interconnect high-speed port to process tasks assigned by the main processor; and at least one downstream peripheral component interconnect high-speed port configured to communicate with an external device.
[0007] The AI chip provided in this application integrates an AI inference engine, an upstream peripheral component interconnection high-speed port, and a downstream peripheral component interconnection high-speed port internally. The upstream and downstream peripheral component interconnection high-speed ports can also be integrated into a data interconnection unit. This allows the AI inference engine and other external devices to enjoy the high bandwidth and low latency provided by the peripheral component interconnection high-speed port, even when the main processor is only configured with one peripheral component interconnection high-speed interface. At the same time, it does not significantly increase the cost of electronic products or sacrifice their size. This solves the problem in the prior art where the number of peripheral component interconnection high-speed ports of the main processor is limited, which restricts the performance of the main processor and corresponding electronic products. This improves the performance of the chip and electronic devices.
[0008] Optionally, the AI chip is a system-on-a-chip (SoC).
[0009] This design can further reduce manufacturing costs and power consumption for inter-chip communication, and achieve higher integration, based on the above solutions.
[0010] Optionally, the AI chip is packaged using a system-in-package (SIP) process, including a first chip integrating the AI inference engine and a second chip integrating the upstream peripheral component interconnect high-speed port and the at least one downstream peripheral component interconnect high-speed port.
[0011] This design maintains a high degree of functional integration while improving manufacturing flexibility, making it easier to integrate chips with different characteristics using different processes.
[0012] Optionally, the downstream peripheral component interconnection high-speed interface uses PCIe as the communication protocol.
[0013] Optionally, the high-speed interconnection interface for the upstream peripheral components uses the PCIe communication protocol.
[0014] Optionally, the AI chip also includes an arbitrator configured to manage data traffic between the upstream peripheral interconnect high-speed port and the downstream peripheral interconnect high-speed port based on a quality of service policy.
[0015] This design optimizes system performance, ensures that data transmission for high-priority tasks (such as low-latency AI inference) is prioritized, and improves user experience.
[0016] Optionally, the quality of service policy prioritizes processing data traffic flowing to the AI inference engine.
[0017] Optionally, the external device is a Wi-Fi module, and the Quality of Service (QoS) policy prioritizes processing data traffic flowing to the Wi-Fi module.
[0018] This design ensures low latency for AI inference tasks, making it particularly suitable for AI application scenarios with high real-time requirements.
[0019] Optionally, the AI chip further includes a power management unit configured to selectively power the downstream peripheral interconnect high-speed port when an external device connected to the downstream peripheral interconnect high-speed port is inactive.
[0020] This design enables sophisticated system-level power management, significantly reducing power consumption in standby or inactive states while maintaining high performance.
[0021] To achieve the aforementioned utility model objectives, this application also provides a computing system, including a main processor for peripheral connection and providing a single peripheral component interconnect high-speed interface, and also including the AI chip described above, wherein an upstream peripheral component interconnect high-speed port of the AI chip is coupled to the single peripheral component interconnect high-speed interface of the main processor; and a Wi-Fi module coupled to the AI chip through a downstream peripheral component interconnect high-speed interface.
[0022] Optionally, in the computing system, the AI chip also includes at least one additional downstream peripheral component interconnect high-speed port, which is configured to connect to an additional external device.
[0023] Optionally, in the computing system, the additional external device is a high-speed storage device.
[0024] In order to achieve the above-mentioned utility model objectives, this application also provides an electronic device that uses the AI chip or the computing system described above. Attached Figure Description
[0025] Figure 1 A diagram illustrating connection conflicts when configuring a main processor with a single PCIe port in the prior art. Figure 2 This is a schematic diagram of the structure of the AI chip in one embodiment of this application; Figure 3 This is a schematic diagram of the computing system in one embodiment of this application; Figure 4 This is a schematic diagram of the computing system in another embodiment of this application. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0027] like Figure 1 As shown, this embodiment provides an AI chip 100, including: an upstream peripheral component interconnect high-speed port 110 configured to connect to a main processor 200; an AI inference engine 120 integrated within the AI chip 100, which is communicatively connected to the upstream peripheral component interconnect high-speed port 110 to process tasks assigned by the main processor 200; and a downstream peripheral component interconnect high-speed port 110 configured to communicate with external devices.
[0028] Among them, the AI inference engine 120 is able to perform matrix operations and inference after receiving AI task data from the main processor 200, and send the results back to the main processor 200 through the high-speed port 110 for interconnecting upstream peripheral components.
[0029] Among them, the high-speed peripheral interconnect port, also referred to as PCIe (peripheral component interconnect express) port in the following text and the attached figures, is a communication port based on the high-speed serial computer expansion bus standard. It has excellent performance and can guarantee low latency and high bandwidth for data transmission. However, it is relatively large in size and expensive. Therefore, in the price and size sensitive consumer electronics field, it is not advisable to improve the overall performance by directly increasing its number.
[0030] The AI chip 100 provided in this embodiment integrates the upstream peripheral component interconnect high-speed port 110 and the downstream peripheral component interconnect high-speed port 130 of the AI inference engine 120 internally. This allows the main processor 200 to enjoy the high bandwidth and low latency of the peripheral component interconnect high-speed port even when the main processor 200 is only configured with one peripheral component interconnect high-speed port. This does not come at the cost of significantly increasing the cost of electronic products or sacrificing their size. It solves the problem in the prior art where the number of peripheral component interconnect high-speed ports 110 of the main processor is limited, which restricts the performance of the main processor and corresponding electronic products. This improves the performance of the chip and electronic equipment.
[0031] Specifically, the other external devices mentioned above can be Wi-Fi modules, high-speed storage devices, or other external devices required by the system.
[0032] Optionally, AI chip 100 is a system-on-a-chip (SoC).
[0033] This design can further reduce manufacturing costs and power consumption for inter-chip communication, and achieve higher integration, based on the above solutions.
[0034] Optionally, the AI chip is packaged using a system-in-package (SIP) process, including a first chip integrating an AI inference engine 120 and a second chip integrating an upstream peripheral component interconnect high-speed port 110 and a downstream peripheral component interconnect high-speed port 130.
[0035] This design maintains a high degree of functional integration while improving manufacturing flexibility, making it easier to integrate chips with different characteristics using different processes.
[0036] The AI chip 100 provided in this embodiment, by integrating the first chip and the second chip into a system-on-a-chip or by using a system-level packaging process, avoids the use of discrete PCIe switching chips, thereby significantly reducing the system's BOM cost, simplifying PCB design, and reducing the occupied area.
[0037] Optionally, such as Figure 3 As shown, the AI chip 100 also includes an arbitrator 140 configured to manage data traffic between the upstream peripheral component interconnect high-speed port 110 and the downstream peripheral component interconnect high-speed port 130 based on a quality of service policy.
[0038] This design optimizes system performance, ensures that data transmission for high-priority tasks (such as low-latency AI inference) is prioritized, and improves user experience.
[0039] Optionally, the quality of service policy prioritizes data traffic flowing to the AI inference engine 110.
[0040] This design ensures low latency for AI inference tasks, making it particularly suitable for AI application scenarios with high real-time requirements.
[0041] Alternatively, in some implementations, the quality of service policy prioritizes data traffic flowing to external devices (such as Wi-Fi modules).
[0042] Optionally, the AI chip 100 also includes a power management unit 150 configured to selectively gate power to the corresponding downstream peripheral component interconnect (PCI) port when the external device connected to the PCI port is inactive.
[0043] Specifically, the power management unit 150 is connected to the high-speed interconnect ports of each downstream peripheral component and can control the power supply to the corresponding downstream peripheral component interconnect port when the external device corresponding to the downstream logic port is inactive, and correspondingly, restore the power supply to the corresponding downstream peripheral component interconnect port when the activity of the corresponding external device is detected.
[0044] This design enables sophisticated system-level power management, significantly reducing power consumption in standby or inactive states while maintaining high performance.
[0045] like Figure 3 As shown, this embodiment also provides a computing system, including a main processor 200 that provides only a single peripheral component interconnect high-speed interface 210 for peripheral connections, and an AI chip 100, wherein an upstream peripheral component interconnect high-speed port 110 of the AI chip 100 is coupled to the single peripheral component interconnect high-speed interface 210 of the main processor 200; and a Wi-Fi module 700, which is coupled to a downstream peripheral component interconnect high-speed port 130 of the AI chip 100 through a peripheral component interconnect high-speed interface.
[0046] The low-cost, high-energy-efficiency consumer electronics device system architecture provided by this embodiment economically and feasiblely resolves the contradiction between the scarcity of main processor PCIe ports and the high-speed connection of AI acceleration engine / Wi-Fi module.
[0047] Optionally, such as Figure 4 As shown, the AI chip 100 also includes at least one additional downstream peripheral component interconnect high-speed port 160, which is configured to connect to an additional external peripheral component interconnect high-speed interface device, which may be a Wi-Fi device, a high-speed storage device 800, or other devices.
[0048] Optionally, this embodiment also provides an electronic device configured with the AI chip or computing system provided in this embodiment. Specifically, the electronic device can be a consumer electronics product such as a mobile phone or computer.
[0049] The technical solution of this utility model has now been described in conjunction with the accompanying drawings. However, it will be readily understood by those skilled in the art that the protection scope of this utility model is obviously not limited to the specific embodiments described above. Without departing from the principles of this utility model, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions resulting from these changes or substitutions will all fall within the protection scope of this utility model.
Claims
1. An AI chip, characterized in that, include: An upstream peripheral interconnect high-speed port is configured for connection to the main processor; An AI inference engine, communicating via a high-speed interconnect port with the upstream peripheral components, to process tasks assigned by the main processor; and At least one downstream peripheral component interconnect high-speed port is configured for communication connection with external devices.
2. The AI chip according to claim 1, characterized in that, The upstream peripheral components are interconnected via high-speed ports, and the communication protocol used is PCIe.
3. The AI chip according to claim 1, characterized in that, The downstream peripheral components are interconnected via high-speed ports, and the communication protocol used is PCIe.
4. The AI chip according to claim 1, characterized in that, The AI chip is packaged using a system-in-package (SIP) process and includes a first chip that integrates the AI inference engine and a second chip that integrates the upstream peripheral component interconnect high-speed port and the at least one downstream peripheral component interconnect high-speed port.
5. The AI chip according to claim 1 or 4, characterized in that, It also includes an arbitrator configured to manage data traffic between the upstream peripheral interconnect high-speed port and the downstream peripheral interconnect high-speed port based on a quality of service policy.
6. The AI chip according to claim 5, characterized in that, The quality of service policy prioritizes processing data traffic flowing to the AI inference engine.
7. The AI chip according to claim 5, characterized in that, The external device is a Wi-Fi module, and the quality of service policy prioritizes processing data traffic flowing to the Wi-Fi module.
8. The AI chip according to claim 1 or 4, characterized in that, It also includes a power management unit configured to selectively power the downstream peripheral interconnect high-speed port when an external device connected to the downstream peripheral interconnect high-speed port is inactive.
9. A computing system comprising a main processor for connecting peripherals and providing a high-speed interface for interconnecting single peripheral components, characterized in that, It also includes an AI chip according to any one of claims 1-8, wherein an upstream peripheral component interconnect high-speed port of the AI chip is coupled to a single peripheral component interconnect high-speed interface of the main processor; and a Wi-Fi module coupled to the AI chip via a downstream peripheral component interconnect high-speed interface.
10. The computing system according to claim 9, characterized in that, The AI chip also includes at least one additional downstream peripheral component interconnect high-speed port, which is configured to connect to an additional external device.
11. The computing system according to claim 10, characterized in that, The additional external device is a high-speed storage device.
12. An electronic device, characterized in that, The AI chip according to any one of claims 1-8, or the computing system according to any one of claims 9-11.