Micro-module chip based on dual-system architecture

Abstract

The utility model discloses a kind of micro module core based on double system architecture, including substrate, control micro module, signal processing micro module and EMMC;Signal processing micro module includes signal processor, first DDR3, second DDR3, power supply one, flash one;Control micro module includes control processor, third DDR3, fourth DDR3, fifth DDR3, power supply two, power supply three, flash two and flash three;Control processor built-in PS processing system and PL programmable logic system;Signal processing micro module and control micro module are highly consistent, each micro module and substrate are covered with metal heat dissipation cover.This application will signal processor, control processor, DDR3, power supply, flash etc. are highly integrated, reduce peripheral device, save area and cost;Double micro module is highly consistent and shares heat dissipation, test is convenient;Adopt double system architecture, limit device quantity, testability is strong, yield is high.

Description

Technical Field

[0001] This utility model relates to the field of electronic chip architecture technology, specifically to a micro-module chip based on a dual-system architecture. Background Technology

[0002] As electronic equipment rapidly evolves towards shorter, smaller, lighter, thinner, more reliable, higher-performance, and lower-cost designs, the demand for miniaturized and modularized communication digital signal processing and control systems is becoming increasingly urgent. Therefore, multi-chip component technology is needed to interconnect and assemble microprocessors, FPGAs, memory, and interface ICs on a high-density multilayer interconnect substrate, forming a fully functional and highly reliable electronic component system, thereby achieving miniaturization and high-density integration of signal processing and control systems.

[0003] Currently, most existing integrated systems for processing, control, and storage adopt the following approach: control is achieved using an MCU controller or a PSOC containing an ARM processor, signal processing is performed using a dedicated high-performance FPGA, and both the processor and FPGA are connected to external DDR memory for storage. All of these implementations are discrete device designs, resulting in large overall area, low integration, and significant challenges in resisting electromagnetic interference.

[0004] Therefore, there is an urgent need for a highly integrated, high-performance digital signal processing and control chip based on SIP technology to effectively save the board area of ​​embedded boards, reduce hardware costs, reduce the difficulty of board design, and achieve miniaturization, high integration, and high reliability of embedded boards. Utility Model Content

[0005] To address the aforementioned issues, the purpose of this invention is to provide a micro-module chip based on a dual-system architecture. By highly integrating signal processors, control processors, DDR3, power supplies, resistors, capacitors, flash memory, etc., it reduces peripheral components and saves area and cost. The two micro-modules are highly consistent and share a common metal heat sink, which effectively dissipates heat and facilitates testing. The dual-system architecture limits the number of components in a single micro-module, resulting in strong testability and high yield.

[0006] The specific technical solution is as follows: A micro-module chip based on a dual-system architecture includes a substrate, a control micro-module, and a signal processing micro-module and an EMMC connected to the control micro-module. The control micro-module, signal processing micro-module, and EMMC are all soldered onto the substrate using a flip-chip bonding process (FC). The signal processing micro-module includes a signal processor, a first DDR3, a second DDR3, a power supply, and a flash memory. The signal processor connects to the first DDR3 via its own banks 18 and 19, to the second DDR3 via its own banks 12 and 13, and to flash memory via its own bank 31. The power supply is connected to the first DDR3, the second DDR3, and the signal processor. The control micro-module includes a control processor, a third DDR3, a fourth DDR3, a fifth DDR3, a second power supply, a third power supply, flash memory, and flash memory. The control processor's built-in PS processing system is connected to the third DDR3, the fourth DDR3, and flash memory. The control processor's built-in PL programmable logic system is connected to the fifth DDR3 via HP banks 33 and 34. The PL programmable logic system is also connected to HP... The BANK is connected to flash memory 3; power supply 2 is connected to the control processor, the third DDR3, and the fourth DDR3 respectively; power supply 3 is connected to the fifth DDR3.

[0007] Preferably, each DDR3 is provided with a corresponding VTT termination power supply, and each DDR3 power supply pin and each VTT termination power supply are connected in parallel with a grounded decoupling capacitor; the address pin, command pin and control signal pin of each DDR3 are connected to the corresponding VTT termination power supply by a corresponding termination resistor.

[0008] Preferably, the signal processing micro-module is soldered onto the substrate using EHS-FCBGA packaging technology. The substrate includes multiple solder balls with a diameter of 0.6 mm and a spacing of 1.0 mm between each solder ball.

[0009] Preferably, the signal processing micro-module and the control micro-module are at the same height, and each micro-module and the bottom of the substrate are covered with a corresponding metal heat sink.

[0010] Preferably, each flash memory uses a QSPI interface to connect to its corresponding bank.

[0011] Preferably, each flash memory has the same storage capacity; flash memory one uses a 256M flash memory with a power supply voltage of 1.8V; flash memory two and three both use a 256M flash memory with a power supply voltage of 3.3V.

[0012] Preferably, the substrate has a length and width of 56mm × 56mm and a thickness of 5.698mm, and the number of solder balls on the substrate is greater than 2000.

[0013] Preferably, the control micro-module further includes a GTX high-speed serial transceiver, which is connected to the PS processing system and PL programmable logic system of the control processor; the signal processing micro-module further includes a GTH high-speed serial transceiver, which is connected to the signal processor.

[0014] Preferably, the control micro-module is provided with multiple PS BANKs, and the EMMC is connected to at least one PS BANK.

[0015] Preferably, the control micro-module is connected to the dedicated loading interface of the signal processing micro-module through the IO interface, and the dedicated loading interface adopts the SSMP8 protocol for loading.

[0016] The advantages of this utility model compared with the prior art are: This invention integrates a signal processor, control processor, DDR3, power supply, terminating resistors, and flash memory, reducing additional peripheral configurations at the board-level design level. This effectively saves board area, reduces hardware costs, and lowers the complexity of board design, achieving miniaturization, high integration, and high reliability of embedded boards. It also features a metal heat sink, and the two micro-modules maintain the same package height, eliminating the need for a separate heat sink for the overall micro-module. This reduces chip size and weight while maintaining convenient chip testing and good heat dissipation performance. Furthermore, the dual-system architecture limits the number of components within a single micro-module, and the two micro-modules can undergo separate functional and environmental tests before integration into the overall micro-module, effectively eliminating defective products and improving overall product yield. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an overall prototype of a micro-module chip based on a dual-system architecture. Figure 2 This is a schematic diagram of the overall layout of a micro-module chip based on a dual-system architecture; Figure 3 This is a prototype schematic diagram of a signal processing micromodule in a micromodule chip based on a dual-system architecture; Figure 4 This is a schematic diagram of the layout of a signal processing micromodule in a micromodule chip based on a dual-system architecture; Figure 5 This is a prototype schematic diagram of the control micromodule in a micromodule chip based on a dual-system architecture; Figure 6 This is a schematic diagram of the layout of the control micromodule in a micromodule chip based on a dual-system architecture. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0019] like Figure 1 The diagram shown is a schematic representation of an overall prototype of a micro-module chip based on a dual-system architecture; as shown... Figure 2 The diagram shown is an overall layout schematic of a micro-module chip based on a dual-system architecture. Label 1 represents the signal processing micro-module, label 2 represents the control micro-module, label 3 represents the flash bare die (containing multiple flash chips), and label 4 represents the eMMC. Figure 1 and Figure 2 As shown, the micro-module chip is mainly constructed using a dual-micro-module system architecture, which highly integrates signal processors, control processors, DDR3, power supplies, resistors and capacitors, flash memory and other devices, reducing peripheral devices and greatly saving the area and cost of the substrate.

[0020] Specifically, a micro-module chip based on a dual-system architecture includes a substrate, a control micro-module, and a signal processing micro-module and an EMMC respectively connected to the control micro-module. The control micro-module, the signal processing micro-module, and the EMMC are all soldered onto the substrate using a flip-chip bonding process. The substrate includes multiple 0.6mm diameter solder balls with a spacing of 1.0mm between each solder ball.

[0021] EMMC, or Embedded Multimedia Card, can use the SMFC32GBMP model sold by Shenzhen Guowei Electronics Co., Ltd., with a storage capacity of 32GB, a chip power supply voltage of 3.3V, and an I / O voltage of 1.8V. The FC flip-chip soldering process can be used with the EHS-FCBGA package type, which is a flip-chip BGA package with an external heatsink.

[0022] like Figure 3 The diagram shown is a prototype schematic of a signal processing micromodule in a micromodule chip based on a dual-system architecture. Figure 1 and Figure 3 As shown, the signal processing micro-module includes a signal processor, a first DDR3, a second DDR3, a power supply, and a flash memory. The signal processor uses an FPGA (e.g., the JFM7VX690T bare die sold by Shanghai Fudan Microelectronics Group Co., Ltd.). The FPGA is connected to the first DDR3, the second DDR3, the power supply, and the flash memory through its various banks.

[0023] The FPGA includes HP BANK and BANK0 types. HP BANK is a high-performance BANK, with multiple HP BANKs supporting the transmission of 378 logic signals. BANK0 is a BANK used to connect to external configurations, supporting the transmission of 19 logic signals. Each BANK connects to a corresponding BALL on the substrate, where BALL stands for solder ball. Specifically, the FPGA connects to the first DDR3 memory via HP BANK18 and HP BANK19, to the second DDR3 memory via its own HP BANK12 and HP BANK13, and to flash memory via its own HP BANK31. Power supply 1 connects to the first DDR3 memory, the second DDR3 memory, and the signal processor for power supply.

[0024] The signal processing micro-module also includes a GTH high-speed serial transceiver, which connects to the signal processor and supports serial signal transmission and reception between the signal processor and other external devices. The GTH high-speed serial transceiver includes multiple Quads, where Quad represents a four-channel group. The GTH high-speed serial transceiver can be connected to multiple solder balls on the substrate via multiple Quads and corresponding SERDES serial-to-parallel converters. The number of Quads and the number of SERDES serial-to-parallel converters are consistent.

[0025] like Figure 4 The diagram shown is a layout schematic of a signal processing micromodule in a micromodule chip based on a dual-system architecture. It specifically illustrates the actual layout of the signal processing micromodule on the substrate. Figure 4 In the diagram, 1.1 represents the signal processor, 1.2 represents the first DDR3 (16-bit data width, 4Gb storage capacity), 1.3 represents the second DDR3 (16-bit data width, 4Gb storage capacity), 1.4 represents power supply chip 1, and 1.5 represents flash memory chip 1. When the signal processing micromodule adopts the EHS-FCBGA package type, its structural dimensions are 26 mm * 46.6 mm * 3.216 mm. It adopts a SIP (System-in-Package) layout, and the bottom structure of the package substrate includes 1150 solder balls.

[0026] like Figure 5The diagram shows a prototype schematic of a control micromodule in a micromodule chip based on a dual-system architecture. The control micromodule includes a control processor (model FMQL45T900 bare die sold by Shanghai Fudan Microelectronics Group Co., Ltd.), a third DDR3, a fourth DDR3, a fifth DDR3, a second power supply, a third power supply, a second flash, and a third flash. The control processor uses a PSOC, which has a built-in PS processing system, a PL programmable logic system, multiple HP banks, and multiple HR banks. Each bank is also connected to each solder ball on the substrate. The HR banks are high-voltage range banks.

[0027] like Figure 6 The diagram shows the layout of the control micromodule in a dual-system architecture micromodule chip. It illustrates the actual layout of the control micromodule on the substrate. Label 2.1 represents the control processor; label 2.2 represents the third DDR3 (32-bit data width, 8Gb storage capacity); label 2.3 represents the fourth DDR3 (32-bit data width, 8Gb storage capacity); label 2.4 represents power supply 2; label 2.5 represents the flash chip (both flash 2 and flash 3 can use, for example, the EFM25QL256 die sold by Shanghai Fudan Microelectronics Group Co., Ltd.); label 2.6 represents the fifth DDR3 (16-bit data width, 4Gb storage capacity); and label 2.7 represents power supply 3.

[0028] The control processor's built-in PS processing system and PL programmable logic system are connected to the third DDR3, fourth DDR3, and flash memory 2, respectively. The PL programmable logic system is connected to the fifth DDR3 via two HP banks, and also to flash memory 3 via any HP bank. Power supply 2 is connected to the control processor, the third DDR3, and the fourth DDR3, and power supply 3 is connected to the fifth DDR3 for power supply, specifically responsible for providing the VTT termination power required by the PS processing system and the corresponding DDR3. Figure 1 , 3 Both the 51200 in 5 and 51200 are VTT-terminated power supplies.

[0029] The control micro-module has multiple PS BANKs, for example Figure 5 In the designation PS500, PS501, and PS502, PS BANK represents the processor system BANK, and the EMMC connects to at least one PS BANK. The control micromodule also includes a GTX high-speed serial transceiver, which connects to the PS processing system and the PL programmable logic system of the control processor. The GTX high-speed serial transceiver can also connect to corresponding solder balls via its own interface and the corresponding SERDES serial-to-parallel converter. In this embodiment, each DDR3 has a corresponding VTT termination power supply, and each DDR3 power supply pin and each VTT termination power supply are connected in parallel with a grounded decoupling capacitor. The decoupling capacitor is used to filter noise and stabilize voltage. The address pin, command pin, and control signal pin of each DDR3 are connected to the corresponding VTT termination power supply by a corresponding termination resistor; the termination resistor is used for impedance matching, so that the corresponding pins in the DDR3 can work normally.

[0030] In this embodiment, the signal processing micro-module and the control micro-module are at the same height, and each micro-module is covered with a corresponding metal heat sink cover on both the top and the bottom of the substrate. With the two micro-modules at the same height, a single, complete metal heat sink can cover both simultaneously, eliminating the need for separate metal heat sinks for each micro-module when their heights are different. Furthermore, simultaneous heat dissipation on both the top of the micro-module and the bottom of the substrate effectively increases the heat dissipation efficiency.

[0031] Each flash memory can be equipped with a QSPI interface, and each can connect to its corresponding bank using the QSPI interface. Each flash memory has the same storage capacity. For example, flash one uses a 256MB flash memory with a 1.8V power supply; flash two and three both use 256MB flash memory with a 3.3V power supply, such as the EFM25QL256 die sold by Shanghai Fudan Microelectronics Group Co., Ltd.

[0032] The substrate has dimensions of 56mm x 56mm and a thickness of 5.698mm, and the substrate has more than 2000 solder balls.

[0033] The control micro-module is connected to the dedicated loading interface of the signal processing micro-module through the IO interface. The dedicated loading interface adopts the SSMP8 protocol. SSMP8 (Small-Size Multi-Pin, 8-pin) is a miniature coaxial connector protocol / interface standard designed for high-speed digital signal transmission and loading. It is the eighth version of SSMP. Using any dedicated loading interface that supports the SSMP8 protocol, such as the SSMP series connectors that support this protocol, can effectively ensure the high efficiency of transmission.

[0034] In summary, this application integrates a signal processor, control processor, DDR3, power supply, terminating resistors, and flash memory, reducing additional peripheral configurations at the board-level design level. This effectively saves board area, reduces hardware costs, and lowers the complexity of board design, achieving miniaturization, high integration, and high reliability of embedded boards. Furthermore, it features a metal heat sink with both micro-modules having the same package height, eliminating the need for a separate heat sink for the overall micro-module. This reduces chip size and weight while also ensuring convenient chip testing and good heat dissipation. In addition, the dual-system architecture limits the number of components within a single micro-module, and the two micro-modules can undergo separate functional and environmental tests before integration into the overall micro-module, effectively eliminating defective products and improving overall product yield, demonstrating significant advancements.

[0035] The above embodiments are only for illustrating the technical concept of this utility model and should not be construed as limiting the scope of protection of this utility model. Any modifications made to the technical solution based on the technical concept proposed by this utility model shall fall within the scope of protection of this utility model.

Claims

1. A micro-module chip based on a dual-system architecture, characterized in that, It includes a substrate, a control micro-module, and a signal processing micro-module and an EMMC connected to the control micro-module respectively. The control micro-module, the signal processing micro-module, and the EMMC are all soldered onto the substrate using the FC flip-chip bonding process. The signal processing micro-module includes a signal processor, a first DDR3, a second DDR3, a power supply, and a flash memory. The signal processor is connected to the first DDR3 via its own BANK18 and BANK19, and to the second DDR3 via its own BANK12 and BANK13, and to the flash memory via its own BANK31. The power supply is connected to the first DDR3, the second DDR3, and the signal processor. The control micro-module includes a control processor, a third DDR3, a fourth DDR3, a fifth DDR3, a second power supply, a third power supply, a second flash memory, and a third flash memory. The built-in PS processing system of the control processor is connected to the third DDR3, the fourth DDR3, and the second flash memory. The built-in PL programmable logic system of the control processor is connected to the fifth DDR3 via HP BANK33 and HP BANK34. The PL programmable logic system is also connected to the third flash memory via HP BANK. The second power supply is connected to the control processor, the third DDR3, and the fourth DDR3. The third power supply is connected to the fifth DDR3.

2. A micro-module chip based on a dual-system architecture according to claim 1, characterized in that, Each DDR3 has its own VTT termination power supply. Each DDR3 power supply pin and each VTT termination power supply are connected in parallel with a grounded decoupling capacitor. The address pin, command pin, and control signal pin of each DDR3 are connected to the corresponding VTT termination power supply by their respective termination resistors.

3. A micro-module chip based on a dual-system architecture according to claim 1, characterized in that, The signal processing micro-module is soldered onto a substrate using EHS-FCBGA packaging technology. The substrate includes multiple 0.6mm diameter solder balls with a spacing of 1.0mm between each solder ball.

4. A micro-module chip based on a dual-system architecture according to claim 3, characterized in that, The signal processing micro-module and the control micro-module are at the same height, and each micro-module and the bottom of the substrate are covered with a corresponding metal heat sink.

5. A micro-module chip based on a dual-system architecture according to claim 1, characterized in that, Each flash memory uses a QSPI interface to connect to its corresponding bank.

6. A micro-module chip based on a dual-system architecture according to claim 1, characterized in that, Each flash memory has the same storage capacity; flash one uses a 256MB flash memory with a power supply voltage of 1.8V; flash two and three both use a 256MB flash memory with a power supply voltage of 3.3V.

7. A micro-module chip based on a dual-system architecture according to claim 3, characterized in that, The substrate has dimensions of 56mm x 56mm and a thickness of 5.698mm, and the substrate has more than 2000 solder balls.

8. A micro-module chip based on a dual-system architecture according to claim 1, characterized in that, The control micro-module also includes a GTX high-speed serial transceiver, which connects to the PS processing system and PL programmable logic system of the control processor; the signal processing micro-module also includes a GTH high-speed serial transceiver, which connects to the signal processor.

9. A micro-module chip based on a dual-system architecture according to claim 1, characterized in that, The control micro-module has multiple PS BANKs, and the EMMC is connected to at least one PS BANK.

10. A micro-module chip based on a dual-system architecture according to claim 1, characterized in that, The control micro-module is connected to the dedicated loading interface of the signal processing micro-module through the IO interface. The dedicated loading interface uses the SSMP8 protocol for loading.

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