Sub-pixel and display device

Abstract

The present disclosure relates to a sub-pixel and a display device. The sub-pixel includes a sixth transistor including a gate, a source electrode, and a drain electrode, wherein the gate of the sixth transistor is connected to one of a second transistor and a second node, and wherein the source electrode and the drain electrode of the sixth transistor are connected to the other of the second transistor and the second node. The sub-pixel further includes a seventh transistor including a gate, a source electrode, and a drain electrode, wherein the gate of the seventh transistor is connected to one of the second node and a fourth power line, and wherein the source electrode and the drain electrode of the seventh transistor are connected to the other of the second node and the fourth power line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0067341, filed on May 23, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This utility model relates to a sub-pixel, and more specifically, to a sub-pixel and a display device including the sub-pixel. Background Technology

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information is becoming increasingly apparent. Therefore, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) displays is constantly increasing.

[0005] Furthermore, for various purposes, sub-pixels of the displayed image in a display device may be provided with capacitors. Capacitors can typically be formed through a process separate from the process of forming transistors. For example, a method can be employed where one electrode of the capacitor is first formed together with the transistor, and then the other electrode of the capacitor is formed.

[0006] However, when transistors and capacitors are formed through separate processes as described above, additional masks are required for forming the capacitors, and additional time may be needed for forming the capacitors. Utility Model Content

[0007] This invention includes a sub-pixel comprising a transistor capable of performing the function of a capacitor and a display device including the sub-pixel.

[0008] In an embodiment, a sub-pixel includes: a light-emitting element connected between a first node and a second power line; a first transistor connected between the first power line and the first node and including a gate connected to the second node; a second transistor connected to a data line and including a gate connected to a first scan line; a third transistor connected between the first node and the second node and including a gate connected to the second scan line; a fourth transistor connected between the first node and the light-emitting element and including a gate connected to a light-emitting control line; a fifth transistor connected between the fourth transistor and the third power line and including a gate connected to the third scan line; a sixth transistor including a gate, a source electrode, and a drain electrode, wherein the gate of the sixth transistor is connected to one of the second transistor and the second node, and the source electrode and drain electrode of the sixth transistor are connected to the other of the second transistor and the second node; and a seventh transistor including a gate, a source electrode, and a drain electrode, wherein the gate of the seventh transistor is connected to one of the second node and the fourth power line, and wherein the source electrode and drain electrode of the seventh transistor are connected to the other of the second node and the fourth power line.

[0009] In an embodiment, the first to fifth transistors may include a P-type semiconductor layer.

[0010] In one embodiment, the sixth transistor may include a P-type semiconductor layer.

[0011] In one embodiment, the sixth transistor may include an N-type semiconductor layer.

[0012] In one embodiment, the seventh transistor may include a P-type semiconductor layer.

[0013] In one embodiment, the seventh transistor may include an N-type semiconductor layer.

[0014] In an embodiment, each of the first to seventh transistors may include a semiconductor layer formed on a silicon substrate.

[0015] In an embodiment, the thickness of the gate insulating layer disposed between the gate of the first transistor and the semiconductor layer of the first transistor may be greater than the thickness of the gate insulating layer disposed between the gate of at least one of the second to seventh transistors and the semiconductor layer of at least one of the second, third, fourth, fifth, sixth and seventh transistors.

[0016] In an embodiment, the semiconductor layer of each of the first to fifth transistors may be disposed in an N-well.

[0017] In one embodiment, the semiconductor layer of each of the sixth and seventh transistors may be disposed in an N-well.

[0018] In an embodiment, the semiconductor layer of at least one of the sixth and seventh transistors may be disposed in a P-well.

[0019] In an embodiment, the N-well may be deeper than the P-well.

[0020] In this embodiment, a first-first power voltage can be applied to a first power line, and a second power voltage can be applied to a second power line. The level of the first-first power voltage can be greater than the level of the second power voltage.

[0021] In one embodiment, a first-second power voltage that is higher than the second power voltage can be applied to the fourth power line.

[0022] In an embodiment, the display device includes: a display panel including a plurality of sub-pixels disposed on a substrate and further including a plurality of data lines connected to the plurality of sub-pixels; and a data driver configured to supply a reference voltage or data signal to the plurality of data lines, wherein at least one of the plurality of sub-pixels includes: a light-emitting element connected between a first node and a second power line; a first transistor connected between the first power line and the first node and including a gate connected to the second node; a second transistor connected to one of the plurality of data lines and including a gate connected to a first scan line; a third transistor connected between the first node and the second node and including a gate connected to the second scan line; and a fourth transistor connected between the first node and the second node. The light-emitting elements are located between and include a gate connected to a light-emitting control line; a fifth transistor is connected between a fourth transistor and a third electric field line and includes a gate connected to a third scan line; a sixth transistor includes a gate, a source electrode, and a drain electrode, wherein the gate of the sixth transistor is connected to one of a second transistor and a second node, and wherein the source electrode and drain electrode of the sixth transistor are connected to the other of the second transistor and the second node; and a seventh transistor includes a gate, a source electrode, and a drain electrode, wherein the gate of the seventh transistor is connected to one of a second node and a fourth electric field line, and wherein the source electrode and drain electrode of the seventh transistor are connected to the other of the second node and the fourth electric field line.

[0023] In an embodiment, the display panel may further include: a substrate including a semiconductor layer; a gate insulating layer disposed on the substrate; and a gate electrode configured to overlap with a channel region of the semiconductor layer. The gate of each of the first to seventh transistors may include a gate electrode.

[0024] In an embodiment, each of the first to seventh transistors may include a P-type semiconductor layer.

[0025] In this embodiment, each of the first through fifth transistors and the seventh transistor may include a P-type semiconductor layer. The sixth transistor may include an N-type semiconductor layer.

[0026] In this embodiment, each of the first through sixth transistors may include a P-type semiconductor layer. The seventh transistor may include an N-type semiconductor layer. Attached Figure Description

[0027] Figure 1 A block diagram of a display device according to an embodiment is shown.

[0028] Figure 2 Illustrations according to embodiments Figure 1 A schematic block diagram of one of the sub-pixels.

[0029] Figure 3 Illustrations according to embodiments Figure 2 The equivalent circuit diagram of the sub-pixels.

[0030] Figure 4 A diagram illustrating an example of a driving timing diagram for a sub-pixel according to an embodiment.

[0031] Figure 5 This is a description based on embodiments. Figure 3 Equivalent circuit diagram and used to describe Figure 4 The driving timing diagram.

[0032] Figure 6 This is a description based on embodiments. Figure 3 Equivalent circuit diagram and used to describe Figure 4 The driving timing diagram.

[0033] Figure 7 This is a description based on embodiments. Figure 3 Equivalent circuit diagram and used to describe Figure 4 The driving timing diagram.

[0034] Figure 8 This is a description based on embodiments. Figure 3 Equivalent circuit diagram and used to describe Figure 4 The driving timing diagram.

[0035] Figure 9 Schematic illustration according to an embodiment Figure 3 A diagram of the semiconductor layer and gate of each of the first type transistor and the second type transistor.

[0036] Figure 10 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0037] Figure 11 This illustrates the formation according to an embodiment. Figure 9A diagram showing the steps of the gate of each of the first and second type transistors.

[0038] Figure 12 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0039] Figure 13 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0040] Figure 14 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0041] Figure 15 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0042] Figure 16 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0043] Figure 17 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0044] Figure 18 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0045] Figure 19 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0046] Figure 20 This illustrates the formation according to an embodiment. Figure 9 A diagram showing the steps of the gate of each of the first and second type transistors.

[0047] Figure 21 An illustration according to another embodiment Figure 2 The equivalent circuit diagram of the sub-pixels.

[0048] Figure 22 Schematic illustration according to an embodiment Figure 21 A diagram of the semiconductor layer and gate of each of the first type transistor, the second type transistor, and the third type transistor.

[0049] Figure 23 An illustration according to another embodiment Figure 2 The equivalent circuit diagram of the sub-pixels.

[0050] Figure 24 Schematic illustration according to an embodiment Figure 23 A diagram of the semiconductor layer and gate of each of the first type transistor, the second type transistor, and the third type transistor.

[0051] Figure 25 Illustrations according to embodiments Figure 1 A top view of the display panel.

[0052] Figure 26 Illustrations according to embodiments Figure 25 An exploded perspective view of a portion of the display panel.

[0053] Figure 27 Illustrations according to embodiments Figure 26 A top view of one of the pixels.

[0054] Figure 28 The following is shown according to the embodiment. Figure 27 The vertical cross-section diagram taken from line I-I'.

[0055] Figure 29 The illustration includes, according to the embodiment, Figure 28 A cross-sectional view of the light-emitting structure in one of the first to third light-emitting elements.

[0056] Figure 30 The illustration shows, according to another embodiment, including Figure 28 A cross-sectional view of the light-emitting structure in one of the first to third light-emitting elements.

[0057] Figure 31 An illustration according to another embodiment Figure 26 A top view of one of the pixels.

[0058] Figure 32 An illustration according to another embodiment Figure 26 A top view of one of the pixels.

[0059] Figure 33 A block diagram of a display system according to an embodiment is shown.

[0060] Figure 34 Illustrations according to embodiments Figure 33 A perspective view of an application example of the display system.

[0061] Figure 35 A diagram showing a head-mounted display device worn on a user according to an embodiment. Detailed Implementation

[0062] In the following description, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following description is intended to provide only sufficient disclosure to enable an understanding of the operation of the present invention, and any other disclosure is omitted to avoid obscuring the scope of the present invention. Furthermore, the present invention may be embodied in different forms and is not limited to the embodiments set forth herein. For the purpose of describing the technical concept of the present invention in sufficient detail, the embodiments described herein are provided to those skilled in the art for easy practice of it.

[0063] Throughout this specification, when an element is described as being “connected” to another element, this includes not only a “direct connection” but also an “indirect connection” between said element and said other element by another means. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the scope of the invention. Throughout this specification, unless explicitly stated otherwise, the word “comprising” and variations such as “including” or “containing” will be understood to implicitly include the stated elements but do not exclude any other elements. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0064] Although the terms first, second, etc., may be used herein to describe various constituent elements, these constituent elements should not be limited by these terms. These terms are used to distinguish one constituent element from another. Therefore, without departing from the teachings of this disclosure, the first constituent element discussed below may be referred to as the second constituent element.

[0065] For descriptive purposes, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would subsequently be oriented “above” other elements or features. Thus, the term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0066] Various embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments. Thus, variations in the shapes illustrated will be expected due to factors such as manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the specific shapes of the areas shown, but should include, for example, deviations in shape due to manufacturing processes. Consequently, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to be limiting.

[0067] Figure 1 A block diagram of a display device 100 according to an embodiment is shown.

[0068] In the embodiments and referenced Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0069] The display panel 110 includes sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm, respectively. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn, respectively. Here, m and n are each positive integers.

[0070] In an embodiment, each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Therefore, the sub-pixels SP can each generate light of a specific color, such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels SP can constitute a pixel PXL. For example, as... Figure 1 As shown, three sub-pixels can form a pixel PXL.

[0071] In one embodiment, gate driver 120 is connected to sub-pixels SP arranged in the row direction via gate lines GL1 to GLm. Gate driver 120 may output gate signals to gate lines GL1 to GLm in response to gate control signal GCS. In one embodiment, gate control signal GCS may include a start signal indicating the start of each frame and a horizontal synchronization signal for timing-synchronizing the output of gate signals with applied data signals, etc.

[0072] In some embodiments, light emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction may be further provided. In this case, the gate driver 120 may include a light emission control driver configured to control the light emission control lines EL1 to ELm, and the light emission control driver may operate under the control of the controller 150.

[0073] In one embodiment, the gate driver 120 may be disposed on one side of the display panel 110. However, the present invention is not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separate drivers, wherein these drivers may be disposed on one side of the display panel 110 and on the opposite side of the display panel 110. As described above, according to the embodiment, the gate driver 120 may be disposed around the display panel 110 in various forms.

[0074] In one embodiment, the data driver 130 is connected to sub-pixels SP arranged in the column direction via data lines DL1 to DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In one embodiment, the data control signal DCS may include a source start pulse signal, a source shift clock signal, and a source output enable signal, etc.

[0075] In this embodiment, the data driver 130 can use the voltage from the voltage generator 140 to apply a data signal having a grayscale voltage corresponding to the image data DATA to the data lines DL1 to DLn. When a gate signal is applied to each of the gate lines GL1 to GLm, a data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image is displayed in the display panel 110.

[0076] In one embodiment, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0077] In an embodiment, voltage generator 140 may operate in response to a voltage control signal VCS from controller 150, wherein voltage generator 140 is configured to generate multiple voltages and provide the generated voltages to components of display device 100. For example, voltage generator 140 may be configured to generate multiple voltages by receiving an input voltage from outside display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0078] Voltage generator 140 can generate a first power voltage ELVDD, a second power voltage ELVSS, and an initialization voltage VINT. The first power voltage ELVDD, the second power voltage ELVSS, and the initialization voltage VINT generated by voltage generator 140 can be provided to the sub-pixel SP. The first power voltage ELVDD can have a relatively high voltage level, and the second power voltage ELVSS and the initialization voltage VINT can have lower voltage levels than the first power voltage ELVDD. In other embodiments, the first power voltage ELVDD or the second power voltage ELVSS can be provided by an external device of the display device 100.

[0079] Furthermore, voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage that can be applied to the sub-pixel SP. For example, during sensing operation that senses the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SP, a predetermined reference voltage can be applied to data lines DL1 to DLn, and voltage generator 140 can generate the reference voltage.

[0080] In this embodiment, the controller 150 controls various operations of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling the display of the input image data from an external source. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0081] The controller 150 can convert the input image data IMG into image data DATA suitable for display device 100 or display panel 110. In an embodiment, the controller 150 can output image data DATA by aligning the input image data IMG to sub-pixels SP suitable for row units.

[0082] In one embodiment, two or more components of the data driver 130, voltage generator 140, and controller 150 may be mounted on a single integrated circuit. For example... Figure 1As shown, the data driver 130, voltage generator 140, and controller 150 can be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 can be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 can be provided as a component separate from the driver integrated circuit (DIC).

[0083] In one embodiment, the display device 100 may include at least one temperature sensor 160, wherein the temperature sensor 160 is configured to sense the ambient temperature and generate temperature data TEP representing the sensed temperature. In another embodiment, the temperature sensor 160 may be positioned adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0084] In one embodiment, controller 150 may control various operations of display device 100 in response to temperature data TEP. In another embodiment, controller 150 may adjust the brightness of the image output from display panel 110 in response to temperature data TEP. For example, controller 150 may control data signals and power voltages ELVDD and ELVSS by controlling components such as data driver 130 and / or voltage generator 140.

[0085] Figure 2 Illustrations according to embodiments Figure 1 A block diagram of one of the sub-pixels SP.

[0086] exist Figure 2 In Figure 1 Among the sub-pixels SP, the sub-pixel SPij set in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0087] In the embodiments and referenced Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0088] In this embodiment, the light-emitting element (LD) is connected between the first power voltage node (VDDN) and the second power voltage node (VSSN). In this case, the first power voltage node (VDDN) is the transmission... Figure 1 The first power voltage ELVDD node, and the second power voltage node VSSN are the transmission nodes. Figure 1 The second power voltage ELVSS node.

[0089] In this embodiment, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via a sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be connected to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0090] In this embodiment, the sub-pixel circuit SPC can be connected to Figure 1 Among the gate lines GL1 to GLm, the i-th gate line GLi, Figure 1 The i-th light emission control line ELi among the light emission control lines EL1 to ELm, and Figure 1 The j-th data line DLj is one of the data lines DL1 to DLn. The sub-pixel circuit SPC is configured to control the light-emitting element LD based on the signals received through these signal lines.

[0091] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi, wherein the i-th gate line GLi may include one or more sub-gate lines. In an embodiment, as shown... Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through sub-gate lines SGL1 and SGL2. Thus, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the corresponding sub-gate lines.

[0092] The sub-pixel circuit SPC can operate in response to an emission control signal received via the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to an emission control signal received via the corresponding sub-emission control line.

[0093] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via sub-gate lines SGL1 and SGL2. In response to a light emission control signal received via the i-th light emission control line ELi, the SPC can adjust the current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN based on the stored voltage. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0094] Figure 3 Illustrations according to embodiments Figure 2 The equivalent circuit diagram of the sub-pixel SPij.

[0095] In the embodiments and referenced Figure 3 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0096] In an embodiment, the sub-pixel circuit SPC can be connected to the i-th gate line GLi', the i-th light emission control line ELi, and the j-th data line DLj. Figure 2 Compared to the i-th gate line GLi, the i-th gate line GLi' may also include a third sub-gate line SGL3.

[0097] In an embodiment, the sub-pixel circuit SPC may include a first transistor T1 to a seventh transistor T7, respectively.

[0098] In one embodiment, the first transistor T1 may be connected between the first power line PL1 and the first node N1. The node to which the first transistor T1 and the first power line PL1 are connected may correspond to... Figure 2 The first power voltage node is VDDN. The gate of the first transistor T1 can be connected to the second node N2. The amount of current flowing through the first transistor T1 can be controlled according to the voltage level applied to the second node N2. The first transistor T1 can be referred to as the driving transistor.

[0099] In one embodiment, a first power voltage ELVDD can be applied to a first power line PL1. In another embodiment, a first-first power voltage ELVDD1 can be applied to the first power line PL1.

[0100] In one embodiment, the second transistor T2 is connected to the j-th data line DLj. In another embodiment, the second transistor T2 may be connected between the j-th data line DLj and the gate of the sixth transistor T6. In yet another embodiment, the second transistor T2 may be connected between the j-th data line DLj and the source and drain electrodes of the sixth transistor. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1. The operating timing of the second transistor T2 can be controlled in response to a first gate signal GW[i] applied to the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0101] In this embodiment, a third transistor T3 is connected between a first node N1 and a second node N2, and the gate of the third transistor T3 can be connected to a second sub-gate line SGL2. The operating timing of the third transistor T3 can be controlled in response to a second gate signal GC[i] applied to the second sub-gate line SGL2.

[0102] In this embodiment, the fourth transistor T4 is connected between the first node N1 and the anode electrode AE ​​of the light-emitting element LD. The gate of the fourth transistor T4 can be connected to the i-th light-emitting control line ELi. In response to the light-emitting control signal EM[i] applied to the i-th light-emitting control line ELi, the operating timing of the fourth transistor T4 can be controlled.

[0103] In one embodiment, the fifth transistor T5 can be connected between the fourth transistor T4 and the third power line PL3. In another embodiment, the fifth transistor T5 can be connected between the first node N1 and the third power line PL3. In yet another embodiment, the fifth transistor T5 can be connected between the anode electrode AE ​​and the third power line PL3. An initialization voltage VINT can be applied to the third power line PL3. In another embodiment, the initialization voltage VINT can be... Figure 1 The voltage generator 140 provides the initial voltage. In other embodiments, the initial voltage may be provided to the display device 100 by an external device. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3. The operating timing of the fifth transistor T5 may be controlled in response to the third gate signal GB[i] applied to the third sub-gate line SGL3.

[0104] In one embodiment, the sixth transistor T6 may include a gate, a source electrode, and a drain electrode, wherein the source and drain electrodes of the sixth transistor T6 may be connected. In another embodiment, the gate of the sixth transistor T6 may be connected to the second transistor T2, and the source and drain electrodes of the sixth transistor T6 may be connected to the second node N2. In yet another embodiment, the gate of the sixth transistor T6 may be connected to the second node N2, and the source and drain electrodes of the sixth transistor T6 may be connected to the second transistor T2. When a conduction level voltage is applied to the gate of the sixth transistor T6, the source and drain electrodes can be connected to each other through the channel region. Therefore, the gate of the sixth transistor T6 can be used as one electrode of a capacitor, and the channel region of the sixth transistor T6 can be used as the other electrode of a capacitor.

[0105] In one embodiment, the seventh transistor T7 may include a gate, a source electrode, and a drain electrode, wherein the source and drain electrodes of the seventh transistor T7 may be connected. In another embodiment, the gate of the seventh transistor T7 may be connected to the second node N2, and the source and drain electrodes of the seventh transistor T7 may be connected to the fourth power line PL4. In another embodiment, the gate of the seventh transistor T7 may be connected to the fourth power line PL4, and the source and drain electrodes of the seventh transistor T7 may be connected to the second node N2. When a conduction level voltage is applied to the gate of the seventh transistor T7, the source and drain electrodes of the seventh transistor T7 can be connected to each other through the channel region. Therefore, the gate of the seventh transistor T7 can be used as one electrode of a capacitor, and the channel region of the seventh transistor T7 can be used as the other electrode of a capacitor.

[0106] A constant voltage can be applied to the fourth power line PL4. In one embodiment, a first power voltage ELVDD can be applied to the fourth power line PL4. In another embodiment, a first-second power voltage ELVDD2 can be applied to the fourth power line PL4. In yet another embodiment, an initialization voltage VINT can be applied to the fourth power line PL4.

[0107] In an embodiment where the gate of the seventh transistor T7 is connected to the fourth power line PL4, an initialization voltage VINT can be applied to the fourth power line PL4.

[0108] As described above, the sub-pixel circuit SPC can include a first transistor T1 to a seventh transistor T7, respectively. However, the present invention is not limited thereto. The sub-pixel circuit SPC can be implemented as one of various types of circuits including multiple transistors. Depending on the embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' can vary. In some embodiments, the i-th light emission control line ELi can include sub-light emission control lines. In the above embodiments, the number of sub-light emission control lines included in the i-th light emission control line ELi can be two or more.

[0109] In this embodiment, transistors T1 to T7 may be P-type transistors, wherein P-type transistors can turn on in response to a low-level signal and turn off in response to a high-level signal. Each of transistors T1 to T7 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). However, the present invention is not limited thereto. For example, in another embodiment, at least one of transistors T1 to T7 may be replaced by an N-type transistor. An N-type transistor can turn on in response to a high-level signal and turn off in response to a low-level signal.

[0110] In the embodiments, transistors T1 to T7 may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, and metal oxide semiconductors, etc.

[0111] In an embodiment, the light-emitting element LD may include a first electrode, a second electrode, and a light-emitting layer. The first electrode may be an anode electrode AE, and the second electrode may be a cathode electrode CE. The light-emitting layer may be disposed between the anode electrode AE ​​and the cathode electrode CE. After the data signal transmitted via the j-th data line DLj is reflected in the voltage of the second node N2, the fourth transistor T4 may be turned on when the light-emitting control signal EM[i] of the i-th light-emitting control line ELi is enabled to a low level. Furthermore, the first transistor T1 may be turned on according to the voltage of the second node N2, and thus current may flow from the first power line PL1 to the second power line PL2. The light-emitting element LD may emit light according to the amount of the flowing current (e.g., drive current).

[0112] Figure 4 A diagram illustrating an example of a driving timing diagram for a sub-pixel according to an embodiment.

[0113] In the embodiments and referenced Figure 4 The first time point TM1 to the sixth time point TM6 (or the first time series to the sixth time series) are shown respectively, and the first period PR1 to the fourth period PR4 are shown respectively. Figure 4 The timing diagram shown can illustrate the supply to Figure 3 The timing of the signal of the sub-pixel SPij.

[0114] It should be understood that the description will assume that the high-level voltage applied to the sub-gate lines SGL1 to SGL3 and the i-th light-emitting control line ELi is the cut-off voltage, and the low-level voltage applied to the sub-gate lines SGL1 to SGL3 and the i-th light-emitting control line ELi is the turn-on voltage.

[0115] In this embodiment, at a first time point TM1, a high-level voltage can be applied to the first sub-gate line SGL1, the second sub-gate line SGL2, and the third sub-gate line SGL3. The i-th light-emitting control line ELi can transition from a low-level voltage to a high-level voltage.

[0116] In this embodiment, at the second time point TM2, the first sub-gate line SGL1 can transition from a high-level voltage to a low-level voltage, the second sub-gate line SGL2 can transition from a high-level voltage to a low-level voltage, and the third sub-gate line SGL3 can transition from a high-level voltage to a low-level voltage. A high-level voltage can be applied to the i-th light-emitting control line ELi.

[0117] In this embodiment, at the third time point TM3, a low-level voltage can be applied to the first sub-gate line SGL1, and a low-level voltage can be applied to the second sub-gate line SGL2. The third sub-gate line SGL3 can transition from a low-level voltage to a high-level voltage. The high-level voltage can be applied to the i-th light-emitting control line ELi.

[0118] In this embodiment, at the fourth time point TM4, a low-level voltage can be applied to the first sub-gate line SGL1, and a high-level voltage can be applied to the third sub-gate line SGL3. The second sub-gate line SGL2 can transition from a low-level voltage to a high-level voltage. The high-level voltage can be applied to the i-th light-emitting control line ELi.

[0119] In this embodiment, at the fifth time point TM5, the first sub-gate line SGL1 can transition from a low-level voltage to a high-level voltage. The high-level voltage can be applied to the second sub-gate line SGL2, and the high-level voltage can be applied to the third sub-gate line SGL3. The high-level voltage can also be applied to the i-th light-emitting control line ELi.

[0120] In this embodiment, at the sixth time point TM6, a high-level voltage can be applied to the first sub-gate line SGL1, a high-level voltage can be applied to the second sub-gate line SGL2, and a high-level voltage can be applied to the third sub-gate line SGL3. The i-th light-emitting control line ELi can transition from a high-level voltage to a low-level voltage.

[0121] The period between the second time point TM2 and the third time point TM3 is the first period PR1, and this period can correspond to the initialization period.

[0122] The period between the third time point TM3 and the fourth time point TM4 is the second period PR2, and this period can correspond to the compensation period.

[0123] The period between the fourth time point TM4 and the fifth time point TM5 is the third period PR3, and this period can correspond to the data writing period.

[0124] The period following the sixth time point TM6 (e.g., the predetermined period) is the fourth period PR4, and this period can correspond to the emission period.

[0125] In this embodiment, the reference voltage Vref can be applied to the j-th data line DLj during the first cycle PR1 and the second cycle PR2. The data signal Vdata can be applied to the j-th data line DLj during the third cycle PR3. For better understanding and ease of description, the voltages applied to the data line DLj during the remaining cycles are omitted.

[0126] Figures 5 to 8This is a description based on embodiments. Figure 3 Equivalent circuit diagram and Figure 4 The driving timing diagram.

[0127] In the embodiments and referenced Figure 5 During the first cycle PR1, the second transistor T2, the third transistor T3, and the fifth transistor T5 can be in the on state. The fourth transistor T4 can be in the off state.

[0128] A reference voltage Vref is applied to the j-th data line DLj. The j-th data line DLj and the gate of the sixth transistor T6 can be electrically connected through the second transistor T2. The gate of the sixth transistor T6 can be initialized with the reference voltage Vref. The reference voltage Vref can be the voltage at the on-level of the sixth transistor T6.

[0129] When the fifth transistor T5 is turned on, the first node N1 can be electrically connected to the third power line PL3. An initialization voltage VINT can be applied to the first node N1. When the third transistor T3 is turned on, the second node N2 can be initialized to the initialization voltage VINT. The initialization voltage VINT can be the voltage at the turn-on level of the seventh transistor T7. The initialization voltage VINT can also be the initialization voltage of the first transistor T1.

[0130] In an embodiment, when the sixth transistor T6 and the seventh transistor T7 are turned on, each of the sixth transistor T6 and the seventh transistor T7 can be used as a capacitor.

[0131] In the embodiments and referenced Figure 6 During the second cycle PR2, the second transistor T2 and the third transistor T3 can be in the on state, and the fourth transistor T4 and the fifth transistor T5 can be in the off state.

[0132] In this configuration, the fourth transistor T4 and the fifth transistor T5 are in the off state, and the first transistor T1 can be connected as a diode. The voltage at the second node N2 can be varied from the initial voltage VINT according to Equation 1 shown below:

[0133] V(N2)=ELVDD1+(Vth of T1) (Equation 1),

[0134] In Equation 1, V(N2) indicates the voltage of the second node N2, ELVDD1 indicates the level of the voltage applied to the first power line PL1, and (Vth of T1) indicates the threshold voltage of the first transistor T1.

[0135] In one embodiment, the voltage reflecting the threshold voltage of the first transistor T1 can be stored in the second node N2, wherein the magnitude of the voltage applied to the second node N2 during the second period PR2 can be the on-state voltage of the seventh transistor T7.

[0136] In the embodiments and referenced Figure 7 The second transistor T2 can be in the on state, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 can be in the off state.

[0137] The gate of the sixth transistor T6 can be connected to the j-th data line DLj via the second transistor T2, so that the data signal Vdata can be applied. The data signal Vdata can be the on-state voltage of the sixth transistor T6.

[0138] As the voltage applied to the gate of the sixth transistor T6 changes from the reference voltage Vref to the data signal Vdata corresponding to the grayscale value, the voltage of the second node N2 can also change. The voltage of the second node N2 can vary based on the ratio between the capacitance formed by the sixth transistor T6 and the capacitance formed by the seventh transistor T7. The voltage of the second node N2 can vary as shown in Equation 2 below:

[0139]

[0140] In Equation 2, V(N2) indicates the voltage of the second node N2, (ELVDD1+T1's Vth) indicates the voltage of the second node N2 during the second cycle PR2, TC1 is the capacitance of the sixth transistor T6 and represents the size of the capacitance formed by the gate and channel regions of the sixth transistor T6, TC2 is the capacitance of the seventh transistor T7 and represents the size of the capacitance formed by the gate and channel regions of the seventh transistor T7, Vref represents the level of the reference voltage applied to the j-th data line DLj during the second cycle PR2, and Vdata represents the level of the data signal applied to the j-th data line DLj during the third cycle PR3. During the third cycle PR3, the voltage of the second node N2 can be the on-state voltage of the seventh transistor T7.

[0141] In this embodiment, the voltage that can compensate for the change in the threshold voltage of the first transistor T1 can be stored in the second node N2.

[0142] In the embodiments and referenced Figure 8 During the fourth cycle PR4, the second transistor T2, the third transistor T3, and the fifth transistor T5 can be in the off state, and the fourth transistor T4 can be in the on state.

[0143] The amount of drive current flowing through the first transistor T1 in the saturation region during the fourth cycle PR4 is expressed by the following equation 3:

[0144]

[0145] In Equation 3, I D The value represents the amount of drain current or drive current flowing through the first transistor T1, μ represents the mobility of the first transistor T1, and C represents the amount of drain current or drive current flowing through the first transistor T1. ox Let L represent the gate capacitance per unit area of ​​the first transistor T1, L represent the length of the channel region of the first transistor T1, and W represent the width of the channel region of the first transistor T1. The remaining symbols are as described by Equation 2.

[0146] Therefore, in the embodiment, during the fourth cycle PR4, the change in the threshold voltage of the first transistor T1 can be compensated, and the drive current can be supplied.

[0147] Figure 9 Schematic illustration according to an embodiment Figure 3 A diagram of the semiconductor layer and gate of each of the first type transistor TR1 and the second type transistor TR2.

[0148] Reference Figure 9 An embodiment is shown in which the semiconductor layer of the first type transistor TR1 and the semiconductor layer of the second type transistor TR2 are respectively formed directly on the substrate SUB.

[0149] In an embodiment, each of the first type transistor TR1 and the second type transistor TR2 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0150] The source region (SRA) and drain region (DRA) can be disposed within the substrate (SUB). A trap formed by ion implantation can also be disposed within the substrate (SUB). In an embodiment, the trap can be configured as an N-trap N-WL. However, the present invention is not limited thereto.

[0151] In an embodiment, the source region SRA and the drain region DRA can be configured to be spaced apart from each other within the well. For example, the region between the source region SRA and the drain region DRA within an N-well N-WL can be defined as a channel region.

[0152] In one embodiment, the gate electrode GE may overlap with a channel region disposed between the source region SRA and the drain region DRA, wherein the gate electrode GE may be spaced apart from the well or channel region by a gate insulating layer comprising an insulating material. The gate electrode GE may comprise a conductive material.

[0153] The gate electrode GE of the first type transistor TR1 can be disposed on the first gate insulating layer GI1, and the gate electrode GE of the second type transistor TR2 can be disposed on the second gate insulating layer GI2.

[0154] In an embodiment, the first gate insulating layer GI1 may have a first thickness DEP1, and the second gate insulating layer GI2 may have a second thickness DEP2. The second thickness DEP2 may be greater than the first thickness DEP1 (the second thickness DEP2 may be thicker than the first thickness DEP1).

[0155] In this embodiment, transistors T2 through T7 can be implemented as a first-type transistor TR1. Therefore, it is possible to achieve... Figure 3 The proposed sub-pixel circuit SPC eliminates the need to form separate capacitors on the transistors. Therefore, the formation of the sub-pixel circuit SPC can be simplified.

[0156] In an embodiment, the first transistor T1 can be implemented as a second type transistor TR2. By increasing the second thickness DEP2, the gate capacitance C per unit area of ​​the first transistor T1, as described in Equation 3, is... ox The value can be increased. Therefore, the length L of the channel region of the first transistor T1 can be relatively shortened. By shortening the length of the channel region of the first transistor T1, the integration density of transistors T1 to T7 can be increased. Therefore, a small display device 100 (see [reference]) can be provided by integrating transistors at high density within the same area without forming separate capacitors on the transistors. Figure 1 ).

[0157] Figures 10 to 20 The formation is shown in detail separately. Figure 9 The steps of the gate of each of the first type transistor TR1 and the second type transistor TR2.

[0158] In the embodiments and referenced Figure 10 In step S1000 of forming the insulating layer INS, the insulating layer INS comprising insulating material can be formed on the substrate SUB.

[0159] In this embodiment, the substrate SUB may be a silicon substrate, but is not limited thereto.

[0160] In the embodiments and referenced Figure 11In step S1100, the photoresist PR is patterned using a mask MSK. The photoresist PR can be disposed on an insulating layer INS. The photoresist PR can be either a positive or negative photoresist. In an embodiment, when light shines on the photoresist PR through an opening area of ​​the mask MSK, the photoresist PR can be removed from the light-illuminated area, allowing the photoresist PR to be patterned.

[0161] In the embodiments and referenced Figure 12 In the initial removal step S1200 of the insulating layer INS, the insulating layer INS can be removed (e.g., etched) according to the pattern of the patterned photoresist PR.

[0162] In the embodiments and referenced Figure 13 In step S1300, the photoresist PR can be removed. Figure 12 A patterned photoresist PR is used. Therefore, a first insulating layer INS1 and a second insulating layer INS2 can be formed.

[0163] In the embodiments and referenced Figure 14 In step S1400, the photoresist PR can be patterned using a mask MSK. In this embodiment, the patterned photoresist PR can expose the upper surface of the first insulating layer INS1.

[0164] In the embodiments and referenced Figure 15 In the second step S1500 of removing the insulating layer INS, at least a portion of the first insulating layer INS1 can be removed (e.g., etched) according to the pattern of the patterned photoresist PR.

[0165] In the embodiments and referenced Figure 16 In step S1600, the photoresist PR can be removed. Figure 15 The patterned photoresist PR is used. Therefore, a first insulating layer INS1 and a second insulating layer INS2 with different thicknesses can be exposed.

[0166] In the embodiments and referenced Figure 17 In step S1700 of forming the gate electrode GE, conductive materials constituting the gate electrode GE may be disposed on the first insulating layer INS1 and the second insulating layer INS2.

[0167] In the embodiments and referenced Figure 18In step S1800, the photoresist PR can be patterned using a mask MSK. In an embodiment, the patterned photoresist PR can be retained on the first insulating layer INS1 and the second insulating layer INS2.

[0168] In the embodiments and referenced Figure 19 In step S1900, when removing the gate electrode GE, at least a portion of the conductive material constituting the gate electrode GE can be removed according to the pattern of the patterned photoresist PR. Therefore, the side surfaces of the first insulating layer INS1 and the second insulating layer INS2 can be exposed.

[0169] In the embodiments and referenced Figure 20 In step S2000, when removing the photoresist PR, the gate electrode GE of the first type transistor TR1 and the gate electrode GE of the second type transistor TR2 can be exposed. The first insulating layer INS1 can be used as the first gate insulating layer GI1 of the first type transistor TR1. The second insulating layer INS2 can be used as the second gate insulating layer GI2 of the second type transistor TR2.

[0170] Figure 21 An illustration according to another embodiment Figure 2 The equivalent circuit diagram of the sub-pixel SPij.

[0171] Will Figure 21 The equivalent circuit diagram in Figure 3 Comparing the equivalent circuit diagrams, there is a difference in the configuration of the sixth transistor T6, while the rest of the configurations are generally the same.

[0172] In one embodiment, the sixth transistor T6 may include a gate connected to the second transistor T2, wherein the sixth transistor T6 may include a source electrode and a drain electrode connected to the second node N2.

[0173] Figure 22 Schematic illustration according to an embodiment Figure 21 A diagram of the semiconductor layer and gate of each of the first type transistor TR1, the second type transistor TR2, and the third type transistor TR3.

[0174] In this embodiment, the first type transistor TR1, the second type transistor TR2, and the third type transistor TR3 can be disposed on the substrate SUB.

[0175] The first type transistor TR1 and the second type transistor TR2 can be configured as transistors including a P-type semiconductor layer, and the third type transistor TR3 can be configured as a transistor including an N-type semiconductor layer.

[0176] The source region SRA and drain region DRA of the first type transistor TR1 and the source region SRA and drain region DRA of the second type transistor TR2 can be configured to be spaced apart from each other within the N-well N-WL.

[0177] The source region SRA and drain region DRA of the third type transistor TR3 can be configured to be spaced apart from each other within the P-well P-WL.

[0178] In an embodiment, within the substrate SUB, the N-well N-WL can be deeper than the P-well P-WL. For example, the N-well N-WL can be formed before the P-well P-WL.

[0179] A first-type transistor TR1 may include a first gate insulating layer GI1. A second-type transistor TR2 may include a second gate insulating layer GI2. A third-type transistor TR3 may include a third gate insulating layer GI3.

[0180] In an embodiment, the first thickness DEP1 of the first gate insulating layer GI1 may be the same as (or substantially the same as) the third thickness DEP3 of the third gate insulating layer GI3. In an embodiment, the second thickness DEP2 of the second gate insulating layer GI2 may be greater than the third thickness DEP3 of the third gate insulating layer GI3. (The second thickness DEP2 may be thicker than the third thickness DEP3).

[0181] Transistors T2, T3, T4, T5, and T7 can be implemented as a first-type transistor TR1. The first transistor T1 can be implemented as a second-type transistor TR2, and the sixth transistor T6 can be implemented as a third-type transistor TR3.

[0182] Figure 23 An illustration according to another embodiment Figure 2 The equivalent circuit diagram of the sub-pixel SPij.

[0183] Will Figure 23 The equivalent circuit diagram in Figure 3 Comparing the equivalent circuit diagrams, there is a difference in the configuration of the seventh transistor T7, while the rest of the configurations are generally the same.

[0184] The seventh transistor T7 may include a gate connected to the fourth power line PL4. The seventh transistor T7 may also include a source electrode and a drain electrode connected to the second node N2. In the above embodiment, the voltage applied to the fourth power line PL4 may be the on-state voltage of the seventh transistor T7.

[0185] In an embodiment, when the seventh transistor T7 is implemented as a transistor including an N-type semiconductor layer, a high-level voltage for turning on the seventh transistor T7 can be applied to the fourth power line PL4. In an embodiment, for example, the high-level voltage can be the first-second power voltage ELVDD2.

[0186] In another embodiment, when the seventh transistor T7 is implemented as a transistor including a P-type semiconductor layer, a low-level voltage for turning on the seventh transistor T7 can be applied to the fourth power line PL4, wherein, for example, the low-level voltage can be the initialization voltage VINT.

[0187] Figure 23 The equivalent circuit diagram shows an embodiment in which the seventh transistor T7 is implemented as a transistor including an N-type semiconductor layer as an example, but the present invention is not limited thereto.

[0188] Therefore, the seventh transistor T7 remains in the on state, allowing it to function similarly to a capacitor.

[0189] Figure 24 Schematic illustration according to an embodiment Figure 23 A diagram of the semiconductor layer and gate of each of the first type transistor TR1, the second type transistor TR2, and the third type transistor TR3.

[0190] Will Figure 24 The picture and Figure 22 The only difference between the transistors implemented as type 1 transistor TR1 and type 3 transistor TR3 is that the diagrams are compared.

[0191] In this embodiment, transistors T2 through T6 can be implemented as a first-type transistor TR1. The first transistor T1 can be implemented as a second-type transistor TR2. The seventh transistor T7 can be implemented as a third-type transistor TR3.

[0192] Figure 25 Illustrations according to embodiments Figure 1 A top view of the display panel 110.

[0193] Reference Figure 25 The display panel DP can be Figure 1 In an embodiment of the display panel 110, the display panel DP may include a display area DA and a non-display area NDA, wherein the display panel DP displays an image through the display area DA and wherein the non-display area NDA is disposed around the display area DA.

[0194] The display panel (DP) can include a substrate (SUB), subpixels (SP), and pads (PD).

[0195] When the display panel DP is used as a display screen for head-mounted displays (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices, the display panel DP can be positioned very close to the user's eyes. In this case, subpixels SP with relatively high integration are required. To increase the integration of subpixels SP, the substrate SUB can be provided as a silicon substrate. Subpixels SP and / or the display panel DP can be formed on the substrate SUB, which is a silicon substrate. A display device 100 including a display panel DP formed on a substrate SUB, which is a silicon substrate (see...) Figure 1 It can be referred to as an organic light-emitting diode (OLED) display device on silicon (OLEDoS).

[0196] In an embodiment, sub-pixels SP are disposed on a substrate SUB within a display area DA. The sub-pixels SP can be arranged in a matrix format along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the present invention is not limited thereto. For example, in an embodiment, the sub-pixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP can be arranged in a... Shape settings. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0197] In an embodiment, two or more of the multiple sub-pixels SP can constitute a pixel PXL.

[0198] The components controlling the sub-pixel SP can be set on the substrate SUB in the non-display area NDA. For example, such as Figure 1 The wiring connecting the gate lines GL1 to GLm and the data lines DL1 to DLn to the sub-pixel SP can be set in the non-display area NDA.

[0199] In this embodiment, alignment marks can be set in the non-display area NDA. The alignment marks can be configured to align with the display panel DP.

[0200] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 can be integrated into the non-display area NDA of the display panel DP. In an embodiment, Figure 1 The gate driver 120 can be mounted on the display panel DP and can also be located in the non-display area NDA. In an embodiment, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 can be located in the non-display area NDA to detect the temperature of the display panel DP.

[0201] In this embodiment, the pad PD is disposed on the substrate SUB in the non-display area NDA and can be electrically connected to the sub-pixel SP via wiring. For example, the pad PD can be connected to the sub-pixel SP via data lines DL1 to DLn.

[0202] The pad PD can connect the display panel DP interface to the display device 100 (see...). Figure 1 Other component elements. In an embodiment, the voltages and signals required for the operation of the component elements included in the display panel DP can be transmitted from the pads PD via... Figure 1 A driver integrated circuit (DIC) is provided. For example, data lines DL1 to DLn can be connected to the driver integrated circuit (DIC) via pad PD. For example, a first power voltage VDD and a second power voltage VSS can be received from the driver integrated circuit (DIC) via pad PD, respectively. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via pad PD.

[0203] In this embodiment, the circuit board can be electrically connected to the pads (PD) using a conductive adhesive component such as an anisotropic conductive film. In this case, the circuit board can be a flexible printed circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit (DIC) can be mounted on the circuit board to be electrically connected to the pads (PD).

[0204] In this embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including straight lines and / or curves. For example, the display area DA can have shapes such as polygonal shapes, circular shapes, semicircular shapes, and elliptical shapes.

[0205] In one embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially curved. In another embodiment, the display panel DP may be bendable, foldable, or rollable. In these embodiments, the display panel DP and / or the substrate SUB may comprise a material with flexible properties.

[0206] Figure 26 Illustrations according to embodiments Figure 25 An exploded perspective view of a portion of the display panel DP.

[0207] exist Figure 26 In the diagram, for clarity and conciseness, the display panel DP is schematically shown. Figure 25 A portion of two pixels PXL1 and PXL2 within the pixel PXL. The portions of the display panel DP corresponding to the remaining pixels can be configured similarly.

[0208] In the embodiments and referenced Figure 25 and Figure 26 Each of pixels PXL1 and PXL2 may include subpixels SP1 to SP3. However, the present invention is not limited thereto. For example, each of pixels PXL1 and PXL2 may include four subpixels or two subpixels.

[0209] exist Figure 26 In the diagram, subpixels SP1 to SP3 are shown as having a quadrilateral shape and having the same size when viewed in a third direction DR3 intersecting directions DR1 and DR2. However, the invention is not limited thereto, and subpixels SP1 to SP3 can be modified to have various shapes.

[0210] In an embodiment, the display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical functional layer OFL, an outer coating OC, and a cover window CW.

[0211] In one embodiment, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. In another embodiment, the substrate SUB may include a glass substrate. In yet another embodiment, the substrate SUB may include a polyimide (PI) substrate.

[0212] In one embodiment, a pixel circuit layer (PCL) is disposed on a substrate (SUB), wherein the substrate (SUB) and / or the pixel circuit layer (PCL) may include an insulating layer and a conductive pattern disposed between the insulating layer. The conductive pattern of the pixel circuit layer (PCL) may be used as at least some of circuit elements and wiring, etc.

[0213] In some embodiments, the conductive pattern may include copper, but the present invention is not limited thereto.

[0214] In an embodiment, the circuit elements may include a sub-pixel circuit SPC for each of sub-pixels SP1 to SP3 (see [link to SPC]). Figure 2The sub-pixel circuit (SPC) may include transistors. Each transistor may include a semiconductor portion comprising a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer (PCL) as a conductive pattern of the pixel circuit layer (PCL). In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer (PCL).

[0215] In an embodiment, the wiring of the pixel circuit layer PCL may include signal lines connected to each of the sub-pixels SP1 to SP3, such as gate lines, light emission control lines, and data lines. The wiring may also include connections to... Figure 2 The wiring for the first power voltage node VDDN. Additionally, the wiring may include connections to... Figure 2 Wiring of the second power voltage node VSSN.

[0216] In an embodiment, the light-emitting element layer LDL may include an anode electrode AE, a pixel-defining film PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0217] The anode electrode AE ​​can be disposed on the pixel circuit layer PCL and can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the present invention is not limited thereto.

[0218] A pixel-defining film (PDL) is disposed on the anode electrode AE ​​and may include an opening OP that exposes a portion of each of the anode electrodes AE. The opening OP of the pixel-defining film PDL can be understood as the light-emitting area corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0219] In this embodiment, the pixel-defining film (PDL) may include an inorganic material. In this case, the pixel-defining film (PDL) may include multiple stacked inorganic layers. For example, the pixel-defining film (PDL) may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x In another embodiment, the pixel-defining film (PDL) may include an organic material. However, the material of the pixel-defining film (PDL) is not limited to this.

[0220] The light-emitting structure (EMS) can be disposed on the anode electrode (AE) exposed by the opening (OP) of the pixel-defined film (PDL). The light-emitting structure (EMS) may include a light-emitting layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0221] In an embodiment, the light-emitting structure EMS can fill the opening OP of the pixel-defining film PDL and can be completely disposed on the upper portion of the pixel-defining film PDL. In other words, the light-emitting structure EMS can extend across sub-pixels SP1 to SP3. In this case, at least some of the functional layers in the light-emitting structure EMS can be broken or bent at the boundary located between sub-pixels SP1 to SP3. However, the present invention is not limited to this. For example, the portions of the light-emitting structure EMS corresponding to sub-pixels SP1 to SP3 are separated from each other, and each of the portions of the light-emitting structure EMS corresponding to sub-pixels SP1 to SP3 can be disposed in the opening OP of the pixel-defining film PDL.

[0222] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can extend across sub-pixels SP1 to SP3. In this way, the cathode electrode CE can be provided as a common electrode for sub-pixels SP1 to SP3.

[0223] The cathode electrode CE can be a thin metal layer with a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode electrode CE can be made of a metallic material or a transparent conductive material to have a relatively thin thickness. In embodiments, the cathode electrode CE may include at least one of various transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In another embodiment, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited to these.

[0224] One of the anode electrode AE, the overlapping portion of the light-emitting structure EMS with one of the anode electrode AE, and the overlapping portion of the cathode electrode CE with one of the anode electrode AE ​​can be understood as constituting a light-emitting element LD (see [link to LD]). Figure 2 In other words, each of the light-emitting elements in sub-pixels SP1 to SP3 may include an anode electrode, a portion of the light-emitting structure EMS overlapping with the anode electrode, and a portion of the cathode electrode CE overlapping with the anode electrode. In each of sub-pixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transported to the light-emitting layer of the light-emitting structure EMS to form excitons, and light can be generated when the excitons transition from the excited state to the ground state. The brightness of the light can be determined based on the amount of current flowing through the light-emitting layer. The wavelength range of the generated light can be determined based on the configuration of the light-emitting layer.

[0225] In an embodiment, the encapsulation layer TFE is disposed on the cathode electrode CE and may cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic films may include silicon nitride, silicon oxide, or silicon oxynitride (SiO2). x N y For example, organic films may include organic insulating materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). However, the materials of the organic films and inorganic films of the encapsulation layer TFE are not limited to these.

[0226] The encapsulation layer TFE may also include aluminum oxide (AlO) x A thin film containing aluminum oxide can be disposed on the upper surface of the TFE encapsulation layer facing the optical functional layer OFL and / or the lower surface of the TFE encapsulation layer facing the light-emitting element layer LDL to improve the encapsulation efficiency of the TFE encapsulation layer.

[0227] Thin films containing aluminum oxide can be formed by atomic layer deposition (ALD). However, the present invention is not limited thereto, and the encapsulation layer TFE may also include a thin film made of at least one of a variety of materials suitable for improving encapsulation efficiency.

[0228] In an embodiment, the optical functional layer OFL is disposed on the encapsulation layer TFE and may include a color filter layer CFL and a lens array LA.

[0229] A color filter layer (CFL) is disposed between the encapsulation layer (TFE) and the lens array (LA). The CFL is configured to selectively output light of a wavelength range or color corresponding to each sub-pixel by filtering light emitted from the light-emitting structure (EMS). The CFL includes color filters (CF) corresponding to sub-pixels SP1 through SP3, and each of the color filters (CF) can transmit light within the wavelength range corresponding to the sub-pixel. For example, the color filter corresponding to the first sub-pixel SP1 can transmit red light, the color filter corresponding to the second sub-pixel SP2 can transmit green light, and the color filter corresponding to the third sub-pixel SP3 can transmit blue light. Depending on the light emitted from the light-emitting structure (EMS) of each sub-pixel, at least some of the color filters (CF) can be omitted.

[0230] In an embodiment, a lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to sub-pixels SP1 to SP3, respectively. Each of the lenses LS can improve light output efficiency by outputting light emitted from the light-emitting structure EMS along a desired path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the outer coating OC. In an embodiment, the lenses LS may include organic materials. In an embodiment, the lenses LS may include acrylic materials. However, the materials of the lenses LS are not limited to these.

[0231] In this embodiment, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA can be shifted in a direction parallel to the plane defined by directions DR1 and DR2, compared to the opening OP of the pixel-defining film PDL. Specifically, in the central region of the display area DA, when viewed in the third direction DR3, the center of the color filter and the center of the lens can be aligned with or overlap with the center of the corresponding opening OP of the pixel-defining film PDL. For example, in the central region of the display area DA, the opening OP of the pixel-defining film PDL can completely overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter and the center of the lens can be shifted from the center of the corresponding opening OP of the pixel-defining film PDL in a planar direction. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel-defining film PDL can partially overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. Therefore, at the center of the display area DA, light emitted from the light-emitting structure EMS can be efficiently output in the normal direction of the display surface. Light emitted from the light-emitting structure EMS located outside the display area DA can be efficiently output in a direction inclined at a predetermined angle relative to the normal direction of the display surface.

[0232] In embodiments, the outer coating OC can be disposed on the lens array LA and can cover the optical functional layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include various materials suitable for protecting the underlying layer from foreign substances such as dust and moisture. For example, the outer coating OC can include at least one of inorganic and organic insulating films. For example, the outer coating OC can include epoxy resin, but the invention is not limited thereto. The outer coating OC can have a lower refractive index than the lens array LA.

[0233] In one embodiment, a cover window CW may be disposed on the outer coating OC and configured to protect the layer beneath the cover window CW. The cover window CW may have a higher refractive index than the outer coating OC. The cover window CW may include glass, but the present invention is not limited thereto. For example, the cover window CW may be encapsulation glass configured to protect the components disposed beneath the cover window CW. In other embodiments, the cover window CW may be omitted.

[0234] Figure 27 Illustrations according to embodiments Figure 26 A top view of one of the pixels.

[0235] In order to Figure 27 A clear and concise description is provided, illustrating the schematic representation. Figure 26 The first pixel, PXL1, is one of the pixels PXL1 and PXL2. The remaining pixels can be configured similarly to the first pixel, PXL1.

[0236] In the embodiments and referenced Figure 26 and Figure 27 The first pixel PXL1 may include sub-pixels SP1 to SP3 set on the first direction DR1.

[0237] The first sub-pixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA disposed around the first light-emitting region EMA1. The second sub-pixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA disposed around the second light-emitting region EMA2. The third sub-pixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA disposed around the third light-emitting region EMA3.

[0238] The first luminescent region EMA1 can be derived from the luminescent structure EMS (see...). Figure 26 The second emitting region EMA2 can be the region in the light-emitting structure EMS that emits light from the portion corresponding to the second sub-pixel SP1. The third emitting region EMA3 can be the region in the light-emitting structure EMS that emits light from the portion corresponding to the third sub-pixel SP3. (See reference...) Figure 26 As described, each light-emitting region can be understood as an opening OP of the pixel-defined film PDL corresponding to each of the sub-pixels SP1 to SP3.

[0239] Figure 28 The following is shown according to the embodiment. Figure 27 The vertical cross-section diagram taken from line I-I'.

[0240] In the embodiments and referenced Figure 28 It can provide a pixel circuit layer PCL set on the substrate SUB.

[0241] The substrate SUB may include a silicon wafer substrate formed using semiconductor processes. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0242] In an embodiment, a pixel circuit layer PCL is disposed on a substrate SUB, wherein the substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 for the first sub-pixel SP1, a transistor T_SP2 for the second sub-pixel SP2, and a transistor T_SP3 for the third sub-pixel SP3. The transistor T_SP1 for the first sub-pixel SP1 may be a sub-pixel circuit SPC included in the first sub-pixel SP1 (see [link to documentation]). Figure 2 One of the transistors in the second sub-pixel SP2, transistor T_SP2 can be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and transistor T_SP3 of the third sub-pixel SP3 can be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 28 For clarity and brevity, only one transistor for each subpixel is shown, and the rest of the circuitry is omitted.

[0243] In an embodiment, the transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0244] The source region (SRA) and drain region (DRA) can be disposed within the substrate (SUB). A well (WL) formed by ion implantation is disposed within the substrate (SUB), and the source region (SRA) and drain region (DRA) can be spaced apart from each other within the well (WL). The region between the source region (SRA) and drain region (DRA) within the well (WL) can be defined as a channel region.

[0245] The gate electrode GE overlaps with the channel region between the source region SRA and the drain region DRA, and can be disposed on the pixel circuit layer PCL. The gate electrode GE can be separated from the well WL or the channel region by an insulating material such as the gate insulating layer GI. The gate electrode GE may include a conductive material.

[0246] In an embodiment, the multiple layers included in the pixel circuit layer PCL include insulating layers and conductive patterns disposed between the insulating layers, and the conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 can be electrically connected to the drain region DRA through a drain connection portion DRC that penetrates one or more insulating layers. The second conductive pattern CP2 can be electrically connected to the source region SRA through a source connection portion SRC that penetrates one or more insulating layers.

[0247] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to other circuit elements and / or wiring, the transistor T_SP1 of the first sub-pixel SP1 can be provided as one of the transistors of the first sub-pixel SP1.

[0248] In an embodiment, each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0249] As described above, the substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the sub-pixels SP1 to SP3.

[0250] In one embodiment, a via layer VIAL is disposed on the pixel circuit layer PCL. The via layer VIAL covers the pixel circuit layer PCL and may have an overall flat surface. The via layer VIAL is configured to planarize the steps on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO2). x ), silicon nitride (SiN) x The embodiments may contain at least one of silicon carbonitride (SiCN) and silicon carbonitride (SiCN), but the embodiments are not limited thereto.

[0251] In this embodiment, the light-emitting element layer (LDL) is disposed on the via layer (VIAL). The light-emitting element layer (LDL) may include a first reflective electrode (RE1) to a third reflective electrode (RE3), a planarization layer (PLNL), a first anode electrode (AE1) to a third anode electrode (AE3), a pixel defining film (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0252] In this embodiment, reflective electrodes RE1 to RE3 are respectively disposed in sub-pixels SP1 to SP3 on the via layer VIAL. Each of the reflective electrodes RE1 to RE3 can be connected to a circuit element disposed on the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0253] The reflective electrodes RE1 to RE3 can be used as total reflection mirrors to reflect light emitted from the light-emitting structure EMS toward the display surface (or cover window CW). The reflective electrodes RE1 to RE3 may comprise a metallic material suitable for reflecting light. The reflective electrodes RE1 to RE3 may comprise at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys selected from two or more of these materials, but the present invention is not limited thereto.

[0254] In this embodiment, a connecting electrode may be disposed below each of the reflective electrodes RE1 to RE3, wherein the connecting electrode can improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connecting electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), and tantalum nitride (TaN), etc., but the embodiment is not limited thereto. In this embodiment, the corresponding reflective electrode may be disposed between the multiple layers of the connecting electrode.

[0255] In an embodiment, a buffer pattern BFP may be disposed below at least one of the reflective electrodes RE1 to RE3. The buffer pattern BFP may include inorganic materials such as silicon carbonitride, but the embodiment is not limited thereto. By providing the buffer pattern BFP, the height of the corresponding reflective electrode on the third-direction DR3 can be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0256] Reflecting electrodes RE1 to RE3 can be used as total reflection mirrors, and the cathode electrode CE can be used as a partial reflection mirror. Light emitted from the light-emitting layer of the light-emitting structure EMS can be at least partially amplified by reciprocating between the reflecting electrodes and the cathode electrode CE, and the amplified light can be output through the cathode electrode CE. Thus, the distance between each reflecting electrode and the cathode electrode CE can be understood as the resonant distance for light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0257] In this embodiment, due to the buffer pattern BFP, the first sub-pixel SP1 can have a shorter resonant distance than other sub-pixels. This resonant distance adjustment allows light within a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first sub-pixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0258] exist Figure 28 The diagram shows a buffer pattern BFP provided in the first sub-pixel SP1 and not provided in the second sub-pixel SP2 and the third sub-pixel SP3, respectively. However, the invention is not limited thereto. The buffer pattern BFP can also be provided in at least one of the sub-pixels SP2 and SP3, allowing adjustment of the resonant distance of at least one of the sub-pixels SP2 and SP3. For example, sub-pixels SP1 to SP3 can correspond to red, green, and blue, respectively, and the distance between the first reflective electrode RE1 and the cathode electrode CE can be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE can be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0259] In an embodiment, to flatten the step between reflective electrodes RE1 to RE3, a planarization layer PLNL can be disposed on the via layer VIAL and the reflective electrodes RE1 to RE3. The planarization layer PLNL can completely cover the reflective electrodes RE1 to RE3 and the via layer VIAL, and can have a flat surface. In an embodiment, the planarization layer PLNL can be omitted.

[0260] In this embodiment, anode electrodes AE1 to AE3, which overlap with reflective electrodes RE1 to RE3 respectively, are disposed on the planarization layer PLNL. When viewed on the third-direction DR3, anode electrodes AE1 to AE3 can be... Figure 27 The luminescent regions EMA1 to EMA3 have similar shapes. Anode electrodes AE1 to AE3 are respectively connected to reflective electrodes RE1 to RE3. The first anode electrode AE1 can be connected to the first reflective electrode RE1 through a first via VIA1 penetrating the planarization layer PLNL. The second anode electrode AE2 can be connected to the second reflective electrode RE2 through a second via VIA2 penetrating the planarization layer PLNL. The third anode electrode AE3 can be connected to the third reflective electrode RE3 through a third via VIA3 penetrating the planarization layer PLNL.

[0261] In embodiments, the anode electrodes AE1 to AE3 may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). X The materials are at least one of transparent conductive materials selected from indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the materials of the anode electrodes AE1 to AE3 are not limited to these. For example, the anode electrodes AE1 to AE3 may include titanium nitride.

[0262] In an embodiment, an insulating layer may be further provided for adjusting the height of one or more of the anode electrodes AE1 to AE3. The insulating layer may be disposed between one or more of the anode electrodes AE1 to AE3 and their corresponding reflective electrodes. In this case, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, sub-pixels SP1 to SP3 may correspond to red, green, and blue, respectively, the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE. A pixel defining film PDL is disposed on some of the anode electrodes AE1 to AE3 and the planarization layer PLNL. The pixel defining film PDL may include an opening OP exposing a portion of each of the anode electrodes AE1 to AE3. The opening OP of the pixel defining film PDL may define the light-emitting area of ​​each of the sub-pixels SP1 to SP3. Thus, the pixel defining film PDL may be disposed on... Figure 27 In the non-luminescent region NEA, to define Figure 27 The luminescent regions are EMA1 to EMA3.

[0263] In an embodiment, the pixel defining film (PDL) may include a plurality of inorganic insulating layers, wherein each of the plurality of inorganic insulating layers may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. For example, a pixel-defined film (PDL) may include a first to a third inorganic insulating layer stacked sequentially, wherein each of the first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon oxynitride. However, the present invention is not limited thereto. The inorganic insulating layer may have a stepped cross-section in a region adjacent to the opening OP.

[0264] In an embodiment, the separator SPR can be provided in the boundary region BDA located between sub-pixels that are arranged adjacent to each other. In other words, the separator SPR can be provided in the boundary region BDA located between adjacent sub-pixels. Figure 25 In each of the boundary regions between sub-pixels SP.

[0265] In an embodiment, the separator SPR can cause a discontinuity to be formed within the light-emitting structure EMS in the boundary region BDA. For example, the light-emitting structure EMS can be broken or bent by the separator SPR in the boundary region BDA.

[0266] The separator SPR can be provided in or on the pixel-defining film PDL, wherein the pixel-defining film PDL may include one or more trenches TRCH1 and TRCH2 serving as the separator SPR in the boundary region BDA. In embodiments and as shown Figure 28 As shown, one or more trenches TRCH1 and TRCH2 can penetrate the pixel defining film PDL and can partially penetrate the planarization layer PLNL. In other embodiments, one or more trenches TRCH1 and TRCH2 can penetrate the pixel defining film PDL and the planarization layer PLNL, and can partially penetrate the via layer VIAL. In still other embodiments, one or more trenches TRCH1 and TRCH2 can at least partially penetrate the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining film PDL can be disposed in one or more of the trenches TRCH1 and TRCH2.

[0267] According to an embodiment, Figure 28Two trenches, TRCH1 and TRCH2, are shown provided in the boundary region BDA. However, the present invention is not limited thereto. In one embodiment, for example, the pixel defining film PDL may include one trench in the boundary region BDA. In another embodiment, the pixel defining film PDL may include three or more trenches in the boundary region BDA.

[0268] In an embodiment, due to trenches TRCH1 and TRCH2, discontinuous portions such as the first gap VD1 and the second gap VD2 can be formed in the boundary region BDA within the light-emitting structure EMS. Some of the multiple layers stacked in the light-emitting structure EMS can be broken by gaps VD1 and VD2 or can be bent. For example, at least one charge-generating layer included in the light-emitting structure EMS can be broken by gaps VD1 and VD2. As described above, due to trenches TRCH1 and TRCH2, the portions of the light-emitting structure EMS included in sub-pixels SP1 to SP3 can be at least partially separated.

[0269] exist Figure 28 The illustration shows an embodiment in which gaps VD1 and VD2 are formed in the light-emitting structure EMS within the boundary region BDA; however, this is merely an example, and the invention is not limited thereto. For example, concave valleys can be formed in the light-emitting structure EMS within the boundary region BDA. The discontinuities formed in the light-emitting structure EMS can vary depending on the shapes of the trenches TRCH1 and TRCH2.

[0270] In this embodiment, the light-emitting structure EMS can be formed by a process such as vacuum deposition or inkjet printing. In this case, the same material as the light-emitting structure EMS can be disposed on the bottom surface of trenches TRCH1 and TRCH2 adjacent to the via layer VIAL.

[0271] In embodiments, the separator SPR can be deformed differently to allow the light-emitting structure EMS to have discontinuities in the boundary region BDA. In embodiments, inorganic insulating patterns additionally stacked on the pixel-defining film PDL can be provided in the boundary region BDA without trenches TRCH1 and TRCH2. The width of the uppermost inorganic insulating pattern among the additionally stacked inorganic insulating patterns can be larger than the width of the inorganic insulating pattern directly below the uppermost inorganic insulating pattern. For example, in the boundary region BDA, the inorganic insulating patterns are sequentially stacked from the pixel-defining film PDL, and the uppermost third inorganic insulating pattern can have a larger width than the second inorganic insulating pattern. For example, the pixel-defining film PDL can have a "T" or "I" shaped cross-section in the boundary region BDA. Depending on the shape of the pixel-defining film PDL, multiple layers included in the light-emitting structure EMS can be at least partially broken or bent in the boundary region BDA.

[0272] In an embodiment, the light-emitting structure EMS can be disposed on the anode electrode AE ​​exposed by the opening OP of the pixel-defining film PDL. The light-emitting structure EMS can fill the opening OP of the pixel-defining film PDL and can be disposed completely across sub-pixels SP1 to SP3. As described above, the light-emitting structure EMS can be at least partially broken or bent by the separator SPR in the boundary region BDA. Therefore, when the display panel DP (see...) Figure 25 During operation, the current leakage from each of the sub-pixels SP1 to SP3 to neighboring sub-pixels through the layers included in the light-emitting structure EMS can be reduced. Therefore, the light-emitting elements LD1 to LD3 can operate with relatively high reliability.

[0273] In one embodiment, the cathode electrode CE can be disposed on the light-emitting structure EMS, wherein the cathode electrode CE can be commonly provided for sub-pixels SP1 to SP3. The cathode electrode CE can serve as a semi-reflective mirror that partially transmits and partially reflects light emitted from the light-emitting structure EMS.

[0274] In this embodiment, the first anode electrode AE1, the portion of the light-emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 can constitute a first light-emitting element LD1. The second anode electrode AE2, the portion of the light-emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 can constitute a second light-emitting element LD2. The third anode electrode AE3, the portion of the light-emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 can constitute a third light-emitting element LD3.

[0275] In this embodiment, the encapsulation layer TFE is disposed on the cathode electrode CE and can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0276] An optical functional layer (OFL) is disposed on the encapsulation layer TFE, wherein the optical functional layer OFL is attached to the encapsulation layer TFE via an adhesive layer APL. For example, the optical functional layer OFL can be manufactured separately to be attached to the encapsulation layer TFE via the adhesive layer APL. The adhesive layer APL also performs the function of protecting the underlying layers, including the encapsulation layer TFE.

[0277] The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA). The color filter layer (CFL) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3) corresponding to sub-pixels (SP1 to SP3), respectively. Color filters (CF1 to CF3) can transmit light in different wavelength ranges. For example, color filters (CF1 to CF3) can transmit red, green, and blue light, respectively.

[0278] In one embodiment, color filters CF1 to CF3 may partially overlap in the boundary region BDA. In other embodiments, color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between color filters CF1 to CF3.

[0279] In this embodiment, the lens array LA is disposed on the color filter layer CFL and may include a first lens LS1, a second lens LS2, and a third lens LS3 corresponding to sub-pixels SP1 to SP3, respectively. Lenses LS1 to LS3 can improve light output efficiency by outputting light emitted from light-emitting elements LD1 to LD3 along a desired path, respectively.

[0280] Figure 29 The illustration includes, according to the embodiment, Figure 28 A cross-sectional view of the light-emitting structure EMS in one of the first light-emitting elements LD1 to the third light-emitting element LD3.

[0281] In the embodiments and referenced Figure 29 The light-emitting structure EMS can have a series structure in which the stacked light-emitting portions EU1 and EU2 are connected. Figure 28 In each of the light-emitting elements LD1 to LD3, the light-emitting structure EMS' (see Figure 30 It can be configured to be essentially the same.

[0282] In an embodiment, each of the light-emitting portions EU1 and EU2 may include at least one light-emitting layer that generates light according to a current applied to each of the light-emitting portions EU1 and EU2. The first light-emitting portion EU1 may include a first light-emitting layer EML1, a first electron transport portion ETU1, and a first hole transport portion HTU1, wherein the first light-emitting layer EML1 may be disposed between the first electron transport portion ETU1 and the first hole transport portion HTU1. The second light-emitting portion EU2 may include a second light-emitting layer EML2, a second electron transport portion ETU2, and a second hole transport portion HTU2, wherein the second light-emitting layer EML2 may be disposed between the second electron transport portion ETU2 and the second hole transport portion HTU2.

[0283] Each of the hole transport sections HTU1 and HTU2 may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer or an electron blocking layer as needed. The hole transport sections HTU1 and HTU2 may have the same configuration or different configurations.

[0284] Each of the electron transport units ETU1 and ETU2 may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer and a hole blocking layer as needed. The electron transport units ETU1 and ETU2 may have the same configuration or different configurations.

[0285] In an embodiment, a connecting layer, which can be provided in the form of a charge generation layer CGL, can be disposed between the first light-emitting portion EU1 and the second light-emitting portion EU2 to connect the first light-emitting portion EU1 and the second light-emitting portion EU2 to each other. In an embodiment, the charge generation layer CGL can have a stacked structure of a P-doped layer and an N-doped layer. For example, the P-doped layer can include P-type dopants such as hexacyanohexaazabenzophenanthrene derivative (HAT-CN), tetracyano-p-dimethylbenzoquinone (TCNQ), or tris(dicyanomethylene)cyclopropane (NDP-9). The N-doped layer can include alkali metals, alkaline earth metals, lanthanides, or combinations thereof. However, the present invention is not limited thereto.

[0286] In an embodiment, the first emissive layer EML1 and the second emissive layer EML2 can generate light of different colors. Light emitted from each of the first emissive layer EML1 and the second emissive layer EML2 can be mixed to be identified as white light. For example, the first emissive layer EML1 can generate blue light, and the second emissive layer EML2 can generate yellow light. In an embodiment, the second emissive layer EML2 may include a structure in which a first sub-emissive layer configured to generate red light and a second sub-emissive layer configured to generate green light are stacked. Red light and green light can be mixed to provide yellow light. In this case, an intermediate layer may be further provided between the first and second sub-emissive layers, the intermediate layer being configured to perform the function of transporting holes and / or preventing the transport of electrons.

[0287] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can generate light of the same color.

[0288] The light-emitting structure EMS can be formed by vacuum deposition or inkjet printing, but this invention is not limited to these methods.

[0289] Figure 30 The illustration shows, according to another embodiment, including Figure 28 A cross-sectional view of the light-emitting structure EMS' in one of the first light-emitting elements LD1 to the third light-emitting element LD3.

[0290] In the embodiments and referenced Figure 30 The light-emitting structure EMS' can have a series structure in which the stacked light-emitting portions EU1' to EU3' are arranged. The light-emitting structure EMS' can be configured to... Figure 28The light-emitting elements LD1 to LD3 are essentially the same.

[0291] In an embodiment, each of the light-emitting portions EU1' to EU3' may include a light-emitting layer that generates light according to a current applied to each of the light-emitting portions EU1' to EU3'. The first light-emitting portion EU1' may include a first light-emitting layer EML1', a first electron transport portion ETU1', and a first hole transport portion HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport portion ETU1' and the first hole transport portion HTU1'. The second light-emitting portion EU2' may include a second light-emitting layer EML2', a second electron transport portion ETU2', and a second hole transport portion HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport portion ETU2' and the second hole transport portion HTU2'. The third light-emitting portion EU3' may include a third light-emitting layer EML3', a third electron transport portion ETU3', and a third hole transport portion HTU3'. The third light-emitting layer EML3' may be disposed between the third electron transport portion ETU3' and the third hole transport portion HTU3'.

[0292] In an embodiment, each of the hole transport sections HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer or an electron blocking layer as needed. The hole transport sections HTU1' to HTU3' may have the same configuration or different configurations.

[0293] In an embodiment, each of the electron transport portions ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer and a hole blocking layer as needed. The first electron transport portions ETU1' to the third electron transport portions ETU3' may have the same configuration or different configurations.

[0294] In this embodiment, the first charge generation layer CGL1' may be disposed between the first light-emitting portion EU1' and the second light-emitting portion EU2'. The second charge generation layer CGL2' may be disposed between the second light-emitting portion EU2' and the third light-emitting portion EU3'.

[0295] In this embodiment, the light-emitting layers EML1' to EML3' can generate light of different colors. The light emitted from each of the light-emitting layers EML1' to EML3' can be mixed to be observed as white light. For example, the first light-emitting layer EML1' can generate blue light, the second light-emitting layer EML2' can generate green light, and the third light-emitting layer EML3' can generate red light.

[0296] In other embodiments, two or more of the light-emitting layers EML1' to EML3' can generate light of the same color.

[0297] Unlike Figure 29 and Figure 30 The embodiment shown, Figure 28 In the embodiments, the light-emitting structure EMS can include a light-emitting portion in each of the light-emitting elements LD1 to LD3. In this case, the light-emitting portions included in the light-emitting elements LD1 to LD3 can be configured to emit light of different colors. For example, the light-emitting portion of the first light-emitting element LD1 can emit red light, the light-emitting portion of the second light-emitting element LD2 can emit green light, and the light-emitting portion of the third light-emitting element LD3 can emit blue light. In this case, unlike... Figure 28 As shown, the light-emitting portions of sub-pixels SP1 to SP3 are separated from each other, and each of the light-emitting portions of sub-pixels SP1 to SP3 can be disposed in the opening OP of the pixel-defining film PDL. In this case, at least some of the color filters CF1 to CF3 can be omitted.

[0298] Figure 31 An illustration according to another embodiment Figure 26 A top view of one of the pixels.

[0299] In the embodiments and referenced Figure 31 The first pixel PXL1' may include the first sub-pixel SP1' to the third sub-pixel SP3'.

[0300] The first sub-pixel SP1' may include a first luminous region EMA1' and a non-luminous region NEA' surrounding the first luminous region EMA1'. The second sub-pixel SP2' may include a second luminous region EMA2' and a non-luminous region NEA' surrounding the second luminous region EMA2'. The third sub-pixel SP3' may include a third luminous region EMA3' and a non-luminous region NEA' surrounding the third luminous region EMA3'.

[0301] The first sub-pixel SP1' and the second sub-pixel SP2' can be set on the second direction DR2. The third sub-pixel SP3' can be set on the first direction DR1 relative to each of the first sub-pixel SP1' and the second sub-pixel SP2'.

[0302] The second sub-pixel SP2' can have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' can have a larger area than the second sub-pixel SP2'. Therefore, the second light-emitting region EMA2' can have a larger area than the first light-emitting region EMA1', and the third light-emitting region EMA3' can have a larger area than the second light-emitting region EMA2'. However, the present invention is not limited thereto. In embodiments, for example, sub-pixels SP1' and SP2' can have substantially the same area, and the third sub-pixel SP3' can have a larger area than each of sub-pixels SP1' and SP2'. Thus, the areas of sub-pixels SP1' to SP3' can be varied depending on the embodiment.

[0303] Figure 32 An illustration according to another embodiment Figure 26 A top view of one of the pixels.

[0304] In the embodiments and referenced Figure 32 The first sub-pixel SP1" may include a first light-emitting region EMA1" and a non-light-emitting region NEA" surrounding the first light-emitting region EMA1". The second sub-pixel SP2" may include a second light-emitting region EMA2" and a non-light-emitting region NEA" surrounding the second light-emitting region EMA2". The third sub-pixel SP3" may include a third light-emitting region EMA3" and a non-light-emitting region NEA" surrounding the third light-emitting region EMA3".

[0305] When viewed on a third-party DR3, subpixels SP1" to SP3 can have polygonal shapes. For example, the shapes of subpixels SP1" to SP3 can be as follows: Figure 32 The hexagonal shape shown.

[0306] When viewed on a third-party DR3, the luminescent regions EMA1" to EMA3 may have a circular shape. However, the present invention is not limited thereto. For example, each of the luminescent regions EMA1" to EMA3 may have a polygonal shape.

[0307] Subpixels SP1" and SP3" can be set on the first direction DR1. The second subpixel SP2" can be set relative to the first subpixel SP1" in a direction that is tilted at an acute angle (or diagonal) relative to the second direction DR2.

[0308] Figure 27 , Figure 31 and Figure 32 The subpixel settings shown are merely examples, and the present invention is not limited thereto.

[0309] Each pixel may include two or more sub-pixels, which may be set differently. Each of the sub-pixels may have various shapes, and each of the light-emitting areas of the sub-pixels may also have various shapes.

[0310] Figure 33 A block diagram of a display system 3300 according to an embodiment is shown.

[0311] In the embodiments and referenced Figure 33 The display system 3300 may include a processor 3310 and one or more display devices 3322 and 3324.

[0312] The processor 3310 can perform various tasks and calculations. In embodiments, the processor 3310 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, and a central processing unit (CPU), etc. The processor 3310 can be connected to and control other components of the display system 3300 via a bus system.

[0313] exist Figure 33 In the diagram, display system 3300 is shown as including display devices 3322 and 3324. Processor 3310 is connected to the first display device 3322 via a first channel CH1 and to the second display device 3324 via a second channel CH2.

[0314] Through the first channel CH1, the processor 3310 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 3322, wherein the first display device 3322 can display an image based on the first image data IMG1 and the first control signal CTRL1. (See also similar...) Figure 1 The described display device 100 is used to configure the first display device 3322. In this case, the first image data IMG1 and the first control signal CTRL1 can be provided as follows: Figure 1 The input image data is IMG and the control signal is CTRL.

[0315] Through the second channel CH2, the processor 3310 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 3324, wherein the second display device 3324 can display an image based on the second image data IMG2 and the second control signal CTRL2. (See also similar references.) Figure 1 The described display device 100 is used to configure the second display device 3324. In this case, the second image data IMG2 and the second control signal CTRL2 can be provided as follows: Figure 1 The input image data is IMG and the control signal is CTRL.

[0316] Display system 3300 may include computing systems that provide image display capabilities, such as portable computers, mobile phones, smartphones, tablet PCs, smartwatches, watch phones, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). Furthermore, display system 3300 may include at least one of head-mounted display devices (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0317] Figure 34 Illustrations according to embodiments Figure 33 A perspective view of an application example of the display system 3300.

[0318] In the embodiments and referenced Figure 34 , Figure 33 The display system 3300 can be applied to a head-mounted display device 3400, wherein the head-mounted display device 3400 can be a wearable electronic device that can be worn on a user's head.

[0319] The head-mounted display device 3400 may include a headband 3410 and a display device housing 3420. The headband 3410 may be connected to the display device housing 3420. The headband 3410 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 3400 to a user's head. The horizontal strap may be configured to surround the side portion of the user's head, and the vertical strap may be configured to surround the upper portion of the user's head. However, the present invention is not limited thereto. For example, the headband 3410 may be implemented in the form of an eyeglass frame or a helmet, etc.

[0320] The display device housing 3420 can accommodate Figure 33 The first display device 3322 and the second display device 3324. The display device housing 3420 can further accommodate... Figure 33 The processor is 3310.

[0321] Figure 35 A diagram showing a head-mounted display device 3400 worn on a user according to an embodiment.

[0322] In the embodiments and further referenced Figure 35 First display device 3322 (see Figure 33 The first display panel DP1 and the second display device 3324 (see) Figure 33 The second display panel DP2 is disposed in the head-mounted display device 3400. The head-mounted display device 3400 may also include one or more lenses LLNS and RLNS.

[0323] In the display device housing 3420, the right eye lens RLNS can be disposed between the first display panel DP1 and the user's right eye. In the display device housing 3420, the left eye lens LLNS can be disposed between the second display panel DP2 and the user's left eye.

[0324] The image output from the first display panel DP1 can be displayed to the user's right eye through the right eye lens RLNS. The right eye lens RLNS can refract light from the first display panel DP1 to guide it towards the user's right eye. The right eye lens RLNS can perform optical functions to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0325] The image output from the second display panel DP2 can be displayed to the user's left eye through the left eye lens LLNS. The left eye lens LLNS can refract light from the second display panel DP2 to guide it towards the user's left eye. The left eye lens LLNS can perform optical functions to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0326] In one embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens with a pancake-shaped cross-section. In another embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens comprising sub-regions with different optical properties. In this case, each display panel outputs an image corresponding to a sub-region of the multi-channel lens, and the output image can pass through the sub-region and be observed by the user.

[0327] According to the embodiments disclosed herein, a transistor capable of performing the function of a capacitor can be provided.

[0328] Although specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Exemplary embodiments have been disclosed herein, and although specific terminology has been used, such terminology is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some cases, unless specifically indicated otherwise, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this invention. Thus, while various embodiments have been described above, those skilled in the art will appreciate that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this invention.

Claims

1. A sub-pixel, characterized in that, The sub-pixels include: A light-emitting element is connected between the first node and the second electric line; A first transistor is connected between a first power line and the first node and includes a gate connected to a second node; The second transistor is connected to the data line and includes a gate connected to the first scan line; A third transistor is connected between the first node and the second node and includes a gate connected to the second scan line; A fourth transistor is connected between the first node and the light-emitting element and includes a gate connected to the light-emitting control line; The fifth transistor is connected between the fourth transistor and the third power line and includes a gate connected to the third scan line; A sixth transistor includes a gate, a source electrode, and a drain electrode, wherein the gate of the sixth transistor is connected to one of the second transistor and the second node, and the source electrode and the drain electrode of the sixth transistor are connected to the other of the second transistor and the second node; and A seventh transistor includes a gate, a source electrode, and a drain electrode, wherein the gate of the seventh transistor is connected to one of the second node and the fourth electric field line, and the source electrode and the drain electrode of the seventh transistor are connected to the other of the second node and the fourth electric field line.

2. The sub-pixel according to claim 1, characterized in that, The thickness of the gate insulating layer disposed between the gate of the first transistor and the semiconductor layer of the first transistor is greater than the thickness of the gate insulating layer disposed between the gate of at least one of the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor and the semiconductor layer of the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor.

3. The sub-pixel according to claim 1, characterized in that, The semiconductor layer of each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor is disposed in an N-well.

4. The sub-pixel according to claim 3, characterized in that, The semiconductor layer of each of the sixth and seventh transistors is disposed in the N-well.

5. The sub-pixel according to claim 3, characterized in that, The semiconductor layer of at least one of the sixth transistor and the seventh transistor is disposed in the P-well.

6. The sub-pixel according to claim 5, characterized in that, The N-well is deeper than the P-well.

7. The sub-pixel according to claim 1, characterized in that, A first-1 electrical voltage is applied to the first electrical line, and a second electrical voltage is applied to the second electrical line, wherein... The level of the first-1 power voltage is greater than the level of the second power voltage.

8. The sub-pixel according to claim 7, characterized in that, A first-second power voltage, which is greater than the second power voltage, is applied to the fourth power line.

9. A display device, characterized in that, The display device includes: A display panel includes a plurality of sub-pixels disposed on a substrate, wherein the display panel further includes a plurality of data lines connected to the plurality of sub-pixels; and A data driver configured to supply a reference voltage or data signal to the plurality of data lines. Wherein, at least one of the plurality of sub-pixels includes: A light-emitting element is connected between the first node and the second electric line; A first transistor is connected between a first power line and the first node and includes a gate connected to a second node; The second transistor is connected to one of the plurality of data lines and includes a gate connected to the first scan line; A third transistor is connected between the first node and the second node and includes a gate connected to the second scan line; A fourth transistor is connected between the first node and the light-emitting element and includes a gate connected to the light-emitting control line; The fifth transistor is connected between the fourth transistor and the third power line and includes a gate connected to the third scan line; A sixth transistor includes a gate, a source electrode, and a drain electrode, wherein the gate of the sixth transistor is connected to one of the second transistor and the second node, and wherein the source electrode and the drain electrode of the sixth transistor are connected to the other of the second transistor and the second node; and A seventh transistor includes a gate, a source electrode, and a drain electrode, wherein the gate of the seventh transistor is connected to one of a second node and a fourth electric field line, and wherein the source electrode and the drain electrode of the seventh transistor are connected to the other of the second node and the fourth electric field line.

10. The display device according to claim 9, characterized in that, The display panel also includes: The substrate includes a semiconductor layer; A gate insulating layer is disposed on the substrate; and The gate electrode is configured to overlap with the channel region of the semiconductor layer. The gate of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor includes the gate electrode.

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