Charging acceleration circuit and detection circuit board

Abstract

The present disclosure provides a charging acceleration circuit and a detection circuit board. The charging acceleration circuit comprises a charging sub-circuit, a switch sub-circuit and a comparison sub-circuit. The charging sub-circuit comprises a first transistor, a first electrode of the first transistor is electrically connected to a first power supply end, and a second electrode and a control electrode of the first transistor are electrically connected to a first node. The switch sub-circuit comprises a second transistor and the comparison sub-circuit. A first electrode of the switch sub-circuit is electrically connected to the first node, a second electrode of the switch sub-circuit is electrically connected to an acceleration output end, and a control electrode of the switch sub-circuit is electrically connected to an output end of the comparison sub-circuit. A first input end of the comparison sub-circuit is connected to a reference voltage, a second input end of the comparison sub-circuit is electrically connected to the acceleration output end, and the output end of the comparison sub-circuit is electrically connected to the control electrode of the second transistor. The charging acceleration circuit is configured to turn on the second transistor based on a signal of the output end when a potential of the acceleration output end is greater than the reference voltage, so that the switch sub-circuit outputs a constant first current signal to the first node. The charging acceleration circuit can complete charging acceleration according to a signal state of the acceleration output end.

Description

Technical Field

[0001] This disclosure relates to the field of testing technology, and in particular to a charging acceleration circuit and a testing circuit board. Background Technology

[0002] In the testing program, the motherboard is connected to the Device Under Test (DUT) via a cable, and the Inter-Integrated Circuit (I2C) bus is used. 2 C) Communicate via the interface and measure relevant parameters of the DUT. Typically, I... 2 The operating voltage of C is +1.2V, while the transmission I... 2 The C signal has a longer cable length and a larger parasitic capacitance, resulting in I... 2 The rising edge of the C signal rises relatively slowly, exceeding the rise of I. 2 Within the C specification range, for example, during fast mode communication (e.g., 400kHz), random errors may occur, affecting the communication success rate. However, current detection structures cannot effectively improve charging speed without affecting power consumption or the actual low-level voltage value.

[0003] Therefore, a circuit is needed that can operate without changing the existing environment I. 2 C effectively accelerates the signal rise speed without affecting the low-level output state by adjusting the pull-up resistor and cable length. Utility Model Content

[0004] To address at least one of the aforementioned problems, this disclosure provides a charging acceleration circuit, comprising: The charging electronic circuit includes a first transistor, wherein the first electrode of the first transistor is electrically connected to a first power supply terminal, and the second electrode and the control electrode are electrically connected to a first node. The switching sub-circuit includes a second transistor and a comparator sub-circuit. The first electrode of the second transistor is electrically connected to the first node, and the second electrode is electrically connected to the acceleration output terminal. The control electrode is electrically connected to the output terminal of the comparator sub-circuit. The comparator sub-circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to a reference voltage, the second input terminal is electrically connected to the acceleration output terminal, and the output terminal is electrically connected to the control electrode of the second transistor. The charging acceleration circuit is configured such that when the signal at the acceleration output terminal is greater than the reference voltage, the second transistor turns on based on the signal at the output terminal, so that the charging sub-circuit outputs a first current signal to the acceleration output terminal.

[0005] Optionally, the first transistor is an N-type transistor, with its first electrode being the drain and its second electrode being the source; and / or the second transistor is an N-type transistor, with its first electrode being the drain and its second electrode being the source.

[0006] Optionally, the comparator circuit includes: an operational amplifier, a first resistor, and a second resistor. The non-inverting input of the operational amplifier is electrically connected to the acceleration output, and the negative input is electrically connected to the reference node. The first end of the first resistor is electrically connected to the first voltage terminal, and the second end is electrically connected to the reference node. The first end of the second resistor is electrically connected to the reference node, and the second end is electrically connected to ground. The signal of the reference node is the reference voltage. The output of the operational amplifier is used as the output of the comparator circuit.

[0007] Optionally, the potential of the first power supply terminal is less than or equal to 2V, and the potential of the reference voltage is greater than or equal to 20% and less than or equal to 30% of the potential of the first power supply terminal; or the potential of the first power supply terminal is greater than 2V, and the potential of the reference voltage is 0.4V.

[0008] Optionally, the first transistor is a junction field-effect transistor.

[0009] Optionally, the absolute value of the pinch-off voltage of the first transistor is less than the minimum set value of the voltage at the first power supply terminal.

[0010] Optionally, the charging electronic circuit also includes a third resistor, and the control electrode of the first transistor is electrically connected to the first node via the third resistor connected in series between the control electrode and the first node.

[0011] A second aspect of this disclosure provides a testing circuit board, comprising: N charging acceleration circuits as described above, where N is an integer greater than or equal to 1; and The open-circuit output interface includes a second power supply terminal, at least one open-circuit output terminal, and a ground terminal. The second power supply terminal has the same signal potential as the first power supply terminal. N open-circuit output terminals are electrically connected to N charging acceleration circuits one by one.

[0012] Optionally, the sum of the saturation drain current of the first transistor and the current from the second power supply terminal to the open output terminal of the corresponding electrically connected open output interface is less than the interface specification current value of the open output interface.

[0013] Optionally, at least one open-circuit output terminal includes a clock signal terminal and a data signal terminal; The detection circuit board includes two charging acceleration circuits. The second transistor of one of the two charging acceleration circuits is electrically connected to the clock signal terminal, and the second transistor of the other is electrically connected to the data signal terminal.

[0014] The beneficial effects of this disclosure are as follows: This disclosure addresses existing problems by providing a charging acceleration circuit and a detection circuit board. It offers a charging sub-circuit and a switching sub-circuit. When the signal input to the acceleration output terminal exceeds a reference voltage, a first current signal is applied to the acceleration output terminal under the control of the switching sub-circuit. This enables charging acceleration at the rising edge of the signal under defined conditions, allowing the circuit to operate without altering existing environmental conditions. 2 The C-type serial bus effectively accelerates the signal rise speed without affecting the low-level output state by adjusting pull-up resistors and cable length, and has broad application prospects. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This diagram shows a block diagram of an open-circuit output detection system based on related technologies. Figure 2 A schematic block diagram of a detection system applying a charging acceleration circuit according to an embodiment of the present disclosure is shown. Figure 3 A schematic diagram of a charging acceleration circuit according to an embodiment of the present disclosure is shown; Figure 4 A circuit diagram of a charging acceleration circuit according to an embodiment of the present disclosure is shown; Figure 5 The diagram shows an equivalent circuit schematic when a charging acceleration circuit according to an embodiment of the present disclosure is used for detection. Figure 6 A schematic diagram of a detection circuit board according to an embodiment of the present disclosure is shown. Detailed Implementation

[0017] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0018] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising," "including," etc., mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms "connected," "linked," etc., are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0019] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0020] As used in this disclosure, "parallel," "perpendicular," and "equal" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equal items being less than or equal to 5% of either one.

[0021] Reference Figure 1 As shown, when a test board is used to test the product under test (DUT), the test board and the DUT are typically connected via a cable. Both the test board and the DUT have cable interfaces, typically I... 2 C interface, and each end I 2 The C interface signal port is either an open-drain output or an open-collector output, where Rp represents the pull-up resistor and Cb represents the cable parasitic capacitance. Currently, when considering improving I... 2There are at least three difficulties in controlling the rise speed of the C signal's rising edge. First, the cable length is limited by the automated mechanism and cannot be shortened, thus preventing an effective reduction in the cable's parasitic capacitance. Second, the pull-up resistor Rp is the internal equivalent resistance of the product under test (DUT), an inherent value that cannot be changed or reduced. Third, if in Figure 1 Adding an external resistor in parallel with the pull-up resistor Rp to the existing circuit theoretically reduces the equivalent pull-up resistance and increases the total pull-up current. However, in the I of the product under test... 2 When the C output is low, the current to ground of its internal open-drain output MOSFET increases, which will affect its low power consumption performance. At the same time, with the same on-resistance of the open-drain output MOSFET, the increased current will also raise the actual voltage value of the low output level, which is equivalent to reducing the margin between the actual voltage and the maximum output voltage (VOL) at the low level. This increases the risk that the low output voltage is too high (especially under the combined effect of external environmental interference) and will not be correctly recognized.

[0022] To address at least one of the above problems, this disclosure provides a charging acceleration circuit, comprising: The charging electronic circuit includes a first transistor, wherein the first electrode of the first transistor is connected to a first power supply terminal, the second electrode is connected to a first node, and the control electrode is connected to the first node. The switching sub-circuit includes a second transistor and a comparator sub-circuit. The first electrode of the second transistor is electrically connected to the first node, and the second electrode is electrically connected to the acceleration output terminal. The control electrode is electrically connected to the output terminal of the comparator sub-circuit. The comparator sub-circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to a reference voltage, the second input terminal is electrically connected to the acceleration output terminal, and the output terminal is electrically connected to the control electrode of the second transistor. The charging acceleration circuit is configured such that when the potential at the acceleration output terminal is greater than the reference voltage, the second transistor turns on based on the signal at the output terminal, so that the charging sub-circuit outputs a first current signal to the acceleration output terminal.

[0023] In this embodiment, by providing a charging sub-circuit and a switching sub-circuit, and when the signal connected to the acceleration output terminal is greater than the reference voltage, a first current signal is applied to the acceleration output terminal under the control of the switching sub-circuit, thereby achieving charging acceleration at the rising edge of the signal under limited conditions, so that the circuit can operate without changing the existing environment. 2 C effectively accelerates the signal rise speed without affecting the low-level output state by adjusting the pull-up resistor and cable length.

[0024] To facilitate understanding of the charging acceleration circuit in the embodiments of this disclosure, firstly based on... Figure 2 The system block diagram shown illustrates the structural relationship between the charging acceleration circuit and the product under test in a typical application.

[0025] Reference Figure 2 As shown in the system block diagram, when performing various electrical tests on the DUT using the detection circuit board 1, it is done through I... 2 Communication is achieved via the C bus. 2 The C bus may include clock signal lines for transmitting clock signals and data signal lines for transmitting data signals. The clock signal lines are typically called SCL, and the data signal lines are typically called SDA. 2 The C bus can be accessed via I 2 The C bus interface is electrically connected to both the detection circuit board 1 and the DUT, based on I... 2 The C bus interface protocol, after the data signal line and clock signal line are electrically connected to the detection circuit board 1 and DUT respectively, constitutes an open-drain output or an open-collector output.

[0026] For ease of illustration, this disclosure uses an open-drain output configuration as an example. Those skilled in the art should understand that this disclosure is not limited to this, and open-collector output configurations should also be covered by this disclosure. It should be understood that the difference for open-collector output configurations lies only in that the charging output terminal Vo of the charging acceleration circuit is electrically connected to the open-collector output terminal and receives or charges the open-collector signal; this will not be elaborated upon further.

[0027] in addition, Figure 2 An example is shown of the equivalent circuit diagram of one of the data signal lines and the clock signal line after connecting the detection board 1 to the DUT. Va represents the equivalent signal terminal of the signal line on the detection board 1, hereinafter referred to as "open-drain output terminal Va".

[0028] Continue to refer to Figure 2 As shown, the charging output terminal of the charging acceleration circuit 2 is electrically connected to the open-drain output terminal Va for use in charging I. 2 The parasitic capacitance Cb of the C bus is charged. In this example, the charging acceleration circuit 2 is a circuit board independent of the detection circuit board 1. It is connected to the detection circuit board 1 via a connector, thereby electrically connecting the acceleration output terminal Vo to the open-drain output terminal Va. Those skilled in the art will understand that when the charging acceleration circuit 2 is electrically connected to the detection circuit board 1 in this manner, the connector can be pre-connected to the open-drain output terminal Va via jumpers or traces arranged on the detection circuit board 1. Alternatively, the charging acceleration circuit 2 can also be electrically connected to the relevant open-drain output terminal Va simply via jumpers.

[0029] When the charging acceleration circuit 2 is implemented using a separate circuit board, it can provide rising edge charging acceleration to the open-drain output terminal Va without affecting the overall layout of the existing detection circuit board 1, and provide rising edge charging acceleration function for any number of open-drain output terminals Va.

[0030] It should be noted that, although Figure 2 The charging acceleration circuit 2 and the detection circuit board 1 are shown as having discrete structures, but this disclosure is not intended to be limited thereto. They can also be implemented as a whole, as will be described below.

[0031] The structure and function of the charging acceleration circuit of this disclosure embodiment are described below with reference to specific examples.

[0032] Combination Figure 3 As shown, the charging acceleration circuit 2 includes a charging sub-circuit 21 and a switching sub-circuit 22.

[0033] The charging sub-circuit 21 includes a first transistor Q1. The first electrode of the first transistor Q1 is electrically connected to the first power supply terminal V1, and the second electrode and control electrode are electrically connected to the first node N1. The switching sub-circuit 22 includes a second transistor Q2 and a comparator sub-circuit 220. The first electrode of the second transistor Q2 is electrically connected to the first node N1, and the second electrode is electrically connected to the acceleration output terminal Vo. When it is electrically connected to the open-drain output terminal Va, its potential is the potential Vo1 of the open-drain output signal. The control electrode of the second transistor Q2 is electrically connected to the output terminal of the comparator sub-circuit 220. The comparator sub-circuit 220 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to a reference voltage Vref1, the second input terminal is electrically connected to the acceleration output terminal Vo, and the output terminal is electrically connected to the control electrode of the second transistor Q2. Note that, for clarity, the potential or signal of a port is indicated by adding the number "1" after the letter of the corresponding port.

[0034] The charging acceleration circuit 2 is configured such that when the potential Vo1 of the acceleration output terminal Vo is greater than the reference voltage Vref1, the second transistor Q2 is turned on based on the signal at the output terminal of the comparator circuit 220, so that the charging sub-circuit 21 outputs a constant first current signal I to the acceleration output terminal Vo. Optionally, the reference voltage Vref1 is the voltage value when the output is in a low-level state, so that the comparator circuit 220 determines whether the potential of the acceleration output terminal Vo, i.e., the open-drain output signal of the open-drain output terminal Va, is in a low-level output state.

[0035] In other words, when the open-drain output terminal Va is not in a low-level output state, the first transistor Q1 outputs a constant first current signal to the acceleration output terminal Vo by controlling the second transistor Q2 to turn on, thereby charging and accelerating the open-drain output signal of the open-drain output terminal Va.

[0036] Specifically, in combination Figure 3 and Figure 4 As shown, the comparator circuit 220 includes: operational amplifier A1, first resistor R1, and second resistor R2.

[0037] The non-inverting input of operational amplifier A1 is electrically connected to the acceleration output Vo, and the negative input is electrically connected to the reference node Vref. The first end of the first resistor R1 is electrically connected to the first voltage terminal, and the second end is electrically connected to the reference node Vref. The first end of the second resistor R2 is electrically connected to the reference node Vref, and the second end is electrically connected to ground GND. The potential of the reference node Vref is the reference voltage Vref1. The output of operational amplifier A1 serves as the output of the comparator circuit. In this example, the first voltage terminal is electrically connected to the first power supply terminal V1, and therefore is identified by the same symbol. However, this disclosure is not limited to this; other voltage signals can also be connected to the first voltage terminal, as long as they can provide a signal with a fixed amplitude greater than the voltage value of the open-drain output signal of the open-drain output terminal Va corresponding to the acceleration output terminal Vo in its low-level output state.

[0038] Reference Figure 4 As can be seen, a comparator is constructed using operational amplifier A1, first resistor R1, and second resistor R2. Utilizing the "virtual open" principle of operational amplifier A1, the first resistor R1 and second resistor R2 form a voltage divider on the voltage signal v1 at the first voltage terminal, with the reference voltage... The identifier "v1" distinguishes it from the port symbol. By properly setting the relationship between the resistance values ​​of the first resistor R1 and the second resistor R2, the reference voltage Vref1 can be obtained as the voltage value of the open-drain output signal connected to the acceleration output terminal Vo when it is in a low-voltage state. Typically, the product under test is a low-voltage product, and the value of the first power supply terminal V1 is generally less than or equal to 2V. In this case, the voltage value of the open-drain output terminal Va in the low-voltage state is 20% and less than or equal to 30% of the potential of the first power supply terminal V1. If the product under test is not a low-voltage product, and the value of the first power supply terminal V1 is greater than 2V, considering I... 2 According to the voltage specification of C, the voltage of the product under test in the low voltage output state is a fixed value of 0.4V, and the potential of the reference voltage is 0.4V at this time.

[0039] Additionally, exemplarily, operational amplifier A1 also needs to provide a bias signal, with its positive power supply terminal electrically connected to the third power supply terminal V3 and its negative power supply terminal electrically connected to ground GND. When the potential of the open-drain output signal Vo1 connected to the acceleration output terminal Vo is greater than the reference voltage Vref1 of the reference node Vref, i.e., Vo1>Vref1, the signal output by the comparator circuit 220 is equal to the potential of the third power supply terminal V3, so that the second transistor Q2 is turned on.

[0040] Continue to refer to Figure 4As shown, the second transistor Q2 is electrically connected between the first power supply terminal V1 and the open-drain output terminal Vo. Specifically, the first electrode of the second transistor Q2 is electrically connected to the first node N1, the second electrode is electrically connected to the acceleration output terminal Vo to receive the open-drain output signal Vo1, and the control electrode is electrically connected to the output terminal of the comparator circuit 220.

[0041] In this example, the second transistor Q2 is an N-type transistor. To ensure that the second transistor Q2 conducts when the open-circuit output voltage signal Vo1 is greater than the reference voltage Vref1, the first terminal of the second transistor Q2 is the drain (D), and the second terminal is the source (S). However, this disclosure is not limited to this; the second transistor Q2 can also be a P-type transistor. When the second transistor Q2 is a P-type transistor, its first terminal is the source (S), and its second terminal is the drain (D), thus ensuring that the second transistor Q2 can electrically connect the first node N1 to the open-drain output terminal Vo according to the aforementioned conduction logic. Optionally, the second transistor Q2 can also be a high-speed analog switch to improve switching speed.

[0042] In embodiments of this disclosure, the first electrode of the first transistor Q1 is electrically connected to the first power supply terminal V1, and the control electrode and the second electrode are electrically connected to the first node N1, so that the first transistor Q1 operates in the constant current region.

[0043] Optionally, refer to Figure 4 As shown, the first transistor Q1 is a junction field-effect transistor (JFET). By setting the first transistor Q1 as a JFET, it is possible to make the first transistor Q1 work in the constant current region through a simple circuit connection and without complex timing control, so as to serve as a constant current source to output a constant first current signal I to the acceleration output terminal Vo during the period when the second transistor Q2 is turned on.

[0044] Furthermore, by using junction field-effect transistors, compared to other methods that use complex structures such as parallel pull-up resistors, the signal rise time can be accelerated faster, and the impact of parasitic capacitance on the signal rise time during signal transmission can be reduced.

[0045] Continue to refer to Figure 4 As shown, in this example, the first transistor Q1 is an N-type transistor, with the first terminal being the drain (D), the second terminal being the source (S), and the control terminal being the gate. When the gate and source of the first transistor Q1 are directly electrically connected, Vgs = 0V, and the first transistor Q1 can be critically turned on. Optionally, the second terminal of the first transistor Q1 is electrically connected to the first node N1 via a third resistor R3. This third resistor R3 is a current-limiting resistor. Through the series connection of the third resistor R3, the gate-source voltage Vgs of the first transistor Q1 is made to be less than 0V and close to 0V.

[0046] To ensure that the first transistor Q1 can operate in the constant current region as a constant current source, the absolute value of its pinch-off voltage Vgs(off) is less than the minimum set value of the voltage at the first power supply terminal V1. Of course, when selecting the first transistor Q1, it should be as small as possible while still meeting the above condition to ensure its operation in the constant current region. With this setting, as the open-drain output signal voltage at the open-drain output terminal Va corresponding to the acceleration output terminal Vo rises, the drain-source voltage Vds of the first transistor Q1 gradually decreases, yet it still satisfies the constant current region operating condition of Vds ≥ Vgs - Vgs(off).

[0047] Optionally, considering the application scenario, the total current after charging should not exceed I when the constant current of the first transistor Q1 operating in the constant current region is used to charge the open-drain output signal of the open-drain output terminal Va. 2 The specification for C requires that the sum of the saturation leakage current and the current I1 flowing through the equivalent pull-up resistance of the product under test be less than or equal to I. 2 The specifications for C are required. Additionally, considering the two-terminal nature of the serial interface, the sum of the saturation drain current of the first transistor Q1 and the current from the second power supply terminal to the open-drain output terminal of its corresponding electrically connected open-drain output interface must be less than or equal to the interface specification current value of the open-drain output interface. This open-drain output interface can be either the open-drain output interface of the product under test or the open-drain output interface of the test circuit board.

[0048] Currently, I 2 The standard current of C is 3mA. Optionally, when the saturation leakage current of the first transistor Q1 is greater than or equal to 0.2mA and less than or equal to 1mA, it can meet the current specification requirements.

[0049] To further understand the working process and function of the charging acceleration circuit in the embodiments of this disclosure, the working process is described in detail below with reference to the equivalent circuit diagram after the charging acceleration circuit 2 is electrically connected to the product under test and the test circuit board.

[0050] Reference Figure 5 As shown in the figure, resistor Rp represents the equivalent pull-up resistor of the product under test. The open-drain output terminal of the product under test is not shown in the equivalent circuit diagram.

[0051] When the open-drain output interface starts working, the potential of the open-drain output terminal Va is divided into a low-level operating state and a non-low-level operating state. In the non-low-level operating state, there are three situations: the potential of the open-drain output terminal Va is at the rising edge, high level, and falling edge. A complete working process is a change from low level to rising edge to high level to falling edge and then back to low level.

[0052] When the open-drain output terminal Va is inactive and in the low-level operating state, since the potential Vo1 is low, Vo1 < Vref1, the potential at the output terminal of the comparison sub-circuit 220 is 0V, and the gate-source voltage of the second transistor Q2 is Vgs=0V-Vo1, so the second transistor Q2 is turned off. Accordingly, the charging acceleration circuit 2 does not exert any influence on the potential of the open-drain output terminal Va at this time.

[0053] When the potential Vo1 of the open-drain output terminal Va is at the above rising edge and is greater than the reference voltage Vref1, that is, the potential Vo1 of the acceleration output terminal Vo satisfies Vo1 > Vref1, the potential at the output terminal of the comparison sub-circuit 220 controls the second transistor Q2 to conduct, so as to connect the first node N1 and the acceleration output terminal Vo into conduction. The constant first current signal I is used to charge the open-drain output terminal Va corresponding to the acceleration output terminal Vo, thereby providing an additional current path, accelerating the charging speed of the parasitic capacitor Cb, further accelerating the change speed of the signal at the open-drain output terminal Va from low level to high level, and realizing rising edge charging acceleration of the open-drain output terminal Va.

[0054] When the potential Vo1 of the open-drain output terminal Va is at the rising edge but the potential Vo1 of the acceleration output terminal Vo is equal to or slightly less than the potential v1 of the first power supply terminal V1, that is, the potential Vo1 of the acceleration output terminal Vo satisfies Vo1 > Vref1, the potential at the output terminal of the comparison sub-circuit 220 controls the second transistor Q2 to conduct. However, at the same time, the potential Vo1 is already high enough that the first transistor Q1 cannot satisfy the condition of operating in a constant current source state, which is equivalent to the absence of a constant current source, thereby not affecting the voltage value of the high level at the acceleration output terminal Vo.

[0055] When the potential Vo1 of the open-drain output terminal Va outputs the above high level, the potential Vo1 is close to v1, the drain-source voltage Vds of the first transistor Q1 is v1-Vo1 which is close to 0V, and the current flowing through the first transistor Q1 is close to zero, which has no influence on the potential Vo1.

[0056] When the potential Vo1 of the open-drain output terminal Va is during the falling edge transition from high level to low level, that is, the potential Vo1 of the acceleration output terminal Vo satisfies Vo1 > Vref1, the potential at the output terminal of the comparison sub-circuit 220 controls the second transistor Q2 to conduct, so as to connect the first node N1 and the acceleration output terminal Vo into conduction. The constant first current signal I still charges the open-drain output terminal Va corresponding to the acceleration output terminal Vo. However, since the internal transistor of the open-drain output terminal is conducted to ground and the on-resistance of the transistor is far less than the pull-up resistor Rp, the fast discharge of the parasitic capacitor Cb is realized, and the discharge speed is much greater than the combined effect of the aforementioned charging current and the current I1 on the pull-up resistor Rp, so that the influence of the constant first current signal I on the falling edge can be almost ignored.

[0057] As can be seen from the above process, when using the charging acceleration circuit of this disclosure, the resistance ratio of the first resistor R1 and the second resistor R2 can be used to change the current source and I. 2 The connection time of the C signal line can be adjusted to change the acceleration start point of the signal rising edge as needed, thus flexibly conditioning the signal waveform.

[0058] Based on the same inventive concept, this disclosure also provides a detection circuit board, comprising: N charging acceleration circuits as described above, where N is an integer greater than or equal to 1; and The open-circuit output interface includes a second power supply terminal, at least one open-circuit output terminal, and a ground terminal. The second power supply terminal has the same signal potential as the first power supply terminal. N open-circuit output terminals are electrically connected to the N charging acceleration circuits one by one.

[0059] The open-circuit output terminal can be an open-drain output terminal or an open-collector output terminal.

[0060] The specific structure and function of the charging acceleration circuit included in the above detection circuit board have been described in detail in the above embodiments, and will not be repeated here. Furthermore, the operation process of the detection circuit board during operation has also been described in detail in the above description of the charging acceleration process, and will not be repeated here either.

[0061] In this embodiment, by providing a detection circuit board with a power supply acceleration circuit, when the detection circuit board is connected to the product under test via a serial bus for product electrical testing, the charging acceleration of the signal rising edge is achieved under certain conditions, so that the circuit can operate without changing the existing environment. 2 C. Pull-up resistor and cable length, effectively accelerating signal rise speed without affecting the low-level output state.

[0062] Reference Figure 6 As shown in the figure, the connection between a charging acceleration circuit 2 and the open-drain output terminal Va in the detection circuit board 1 is illustrated. However, it should be noted that the detection circuit board of this embodiment is not limited to this. For serial bus interfaces, for example, I... 2 The C-bus interface and the detection circuit board 1 include at least a clock signal terminal and a data signal terminal. At this time, the detection circuit board 1 may include two charging acceleration circuits 2. The second electrode of the second transistor Q2 of one of the two charging acceleration circuits is electrically connected to the clock signal terminal, and the second electrode of the second transistor Q2 of the other is electrically connected to the data signal terminal.

[0063] This setting ensures that the rising speed of the interface's rising edge remains consistent, thereby guaranteeing accurate output clock and data timing.

[0064] Optionally, the sum of the saturation drain current of the first transistor and the current from the second power supply terminal to the open-circuit output terminal of the corresponding electrically connected open-circuit output interface is less than the interface specification current value of the open-circuit output interface.

[0065] This configuration ensures that while the charging acceleration circuit accelerates the charging of the open-circuit output, it also meets the serial longitudinal specifications, thus ensuring that the output can function properly.

[0066] This disclosure addresses existing problems by providing a charging acceleration circuit and a detection circuit board. It includes a charging sub-circuit and a switching sub-circuit. When the signal input to the acceleration output terminal exceeds a reference voltage, a first current signal is applied to the acceleration output terminal under the control of the switching sub-circuit. This achieves charging acceleration at the rising edge of the signal under defined conditions, allowing the circuit to operate without altering existing environmental conditions. 2 The pull-up resistors and cable lengths of buses with open-drain or open-collector outputs (such as C-type buses) can effectively accelerate the signal rise speed without affecting the low-level output state, and have broad application prospects.

[0067] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A charging acceleration circuit, characterized in that, include: The charging electronic circuit includes a first transistor, wherein the first electrode of the first transistor is electrically connected to a first power supply terminal, and the second electrode and the control electrode are electrically connected to a first node; The switching sub-circuit includes a second transistor and a comparator sub-circuit. The first electrode of the second transistor is electrically connected to the first node, the second electrode is electrically connected to the acceleration output terminal, and the control electrode is electrically connected to the output terminal of the comparator sub-circuit. The comparator sub-circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to a reference voltage, the second input terminal is electrically connected to the acceleration output terminal, and the output terminal is electrically connected to the control electrode of the second transistor. The charging acceleration circuit is configured such that when the signal at the acceleration output terminal is greater than the reference voltage, the second transistor turns on based on the signal at the output terminal, so that the charging sub-circuit outputs a first current signal to the acceleration output terminal.

2. The charging acceleration circuit according to claim 1, characterized in that, The first transistor is an N-type transistor, with its first electrode being the drain and its second electrode being the source. and / or The second transistor is an N-type transistor, with its first electrode being the drain and its second electrode being the source.

3. The charging acceleration circuit according to claim 1, characterized in that, The comparator circuit includes: an operational amplifier, a first resistor, and a second resistor. The first input terminal of the operational amplifier is electrically connected to the acceleration output terminal, and the second input terminal is electrically connected to the reference node. The first terminal of the first resistor is electrically connected to the first voltage terminal, and the second terminal is electrically connected to the reference node. The first terminal of the second resistor is electrically connected to the reference node, and the second terminal is electrically connected to ground. The signal of the reference node is the reference voltage. The output terminal of the operational amplifier serves as the output terminal of the comparator circuit.

4. The charging acceleration circuit according to claim 3, characterized in that, The potential of the first power supply terminal is less than or equal to 2V, and the potential of the reference voltage is greater than or equal to 20% and less than or equal to 30% of the potential of the first power supply terminal; or The potential of the first power supply terminal is greater than 2V, and the potential of the reference voltage is 0.4V.

5. The charging acceleration circuit according to claim 1, characterized in that, The first transistor is a junction field-effect transistor.

6. The charging acceleration circuit according to claim 5, characterized in that, The absolute value of the pinch-off voltage of the first transistor is less than the minimum set value of the voltage at the first power supply terminal.

7. The charging acceleration circuit according to claim 1, characterized in that, The charging sub-circuit also includes a third resistor, and the control electrode of the first transistor is electrically connected to the first node via the third resistor connected in series between the control electrode and the first node.

8. A testing circuit board, characterized in that, include: N charging acceleration circuits as described in any one of claims 1-7, where N is an integer greater than or equal to 1; as well as The open-circuit output interface includes a second power supply terminal, at least one open-circuit output terminal, and a ground terminal. The second power supply terminal has the same signal potential as the first power supply terminal. N open-circuit output terminals are electrically connected to the N charging acceleration circuits one by one.

9. The detection circuit board according to claim 8, characterized in that, The sum of the saturation drain current of the first transistor and the current from the second power supply terminal to the open output terminal of the corresponding open output interface is less than the interface specification current value of the open output interface.

10. The detection circuit board according to claim 8, characterized in that, The at least one open-circuit output terminal includes a clock signal terminal and a data signal terminal. The detection circuit board includes two charging acceleration circuits. The second electrode of the second transistor in one of the two charging acceleration circuits is electrically connected to the clock signal terminal, and the second electrode of the second transistor in the other is electrically connected to the data signal terminal.

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